Device Having Semiconductor Body Comprising Silicon Carbide (sic) (epo) Patents (Class 257/E21.054)
  • Patent number: 10147797
    Abstract: A silicon carbide semiconductor device, including a silicon carbide semiconductor structure, an insulated gate structure, an interlayer insulating film formed on the insulated gate structure, a poly-silicon film formed on the interlayer insulating film, and a main electrode formed on the poly-silicon film and in electrical connection with the silicon carbide semiconductor structure. The insulated gate structure includes a gate insulating film, which is a silicon dioxide film contacting the silicon carbide semiconductor structure, and a gate electrode formed on the gate insulating film.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: December 4, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takumi Fujimoto, Naoki Kumagai
  • Patent number: 10067084
    Abstract: A device, apparatus and method for trapping metal ions and detecting metal ion contamination in a solution provide a semiconductor device formed on a semiconductor substrate and including an N-well formed over a P-type substrate and at least a contact portion of the N-well in electrical contact with the solution. When the semiconductor device is optically illuminated, a P/N junction is formed as a result of photovoltaic phenomena. Metal ions from the solution migrate to the contact area due to the voltage created at the P/N junction. The semiconductor device includes a conductive structure with conductive features separated by a gap and therefore in an initially electrically open state. When the ions migrate to the contact area, they precipitate, at least partially bridging the gap and creating conductance through the conductive structure. The conductance may be measured to determine the amount of metal ion contamination.
    Type: Grant
    Filed: March 19, 2015
    Date of Patent: September 4, 2018
    Assignee: WAFERTECH, LLC
    Inventors: Re-Long Chiu, Jason Higgins
  • Patent number: 10050411
    Abstract: The method includes the steps of: preparing a single crystal SiC including an upper surface 10a and a lower surface 10b and provided with a micropipe 11 penetrating from the upper surface 10a to the lower surface 10b; forming a first seed layer 21 made of a metal material on the upper surface 10a of the single crystal SiC; and forming a first plated layer 31 on the first seed layer 21 so as to close an upper end of the micropipe 11, using an electroplating method.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: August 14, 2018
    Assignee: NICHIA CORPORATION
    Inventors: Akinori Yoneda, Shinya Sonobe, Hiroaki Yuto
  • Patent number: 10032690
    Abstract: A thermally conductive and electrically insulating layer is provided over a semiconductor structure.
    Type: Grant
    Filed: February 24, 2015
    Date of Patent: July 24, 2018
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Nathan Perkins, Thomas Dungan
  • Patent number: 9806182
    Abstract: III-nitride materials are generally described herein, including material structures comprising III-nitride material regions and silicon-containing substrates. Certain embodiments are related to gallium nitride materials and material structures comprising gallium nitride material regions and silicon-containing substrates.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: October 31, 2017
    Assignee: MACOM Technology Solutions Holdings, Inc.
    Inventor: Kevin J. Linthicum
  • Patent number: 9490214
    Abstract: A semiconductor device may include a substrate having a lower via-hole, an epitaxial layer having an opening exposing a top surface of the substrate, a semiconductor chip disposed on the top surface of the substrate and including first, second, and third electrodes, an upper metal layer connected to the first electrode, a supporting substrate disposed on the upper metal layer and having an upper via-hole, an upper pad disposed on the substrate and extending into the upper via-hole, a lower pad connected to the second electrode in the opening, and a lower metal layer covering a bottom surface of the substrate and connected to the lower pad through the lower via-hole.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: November 8, 2016
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Byoung-Gue Min, Sang Choon Ko, Jong-Won Lim, Hokyun Ahn, Hyung Sup Yoon, Jae Kyoung Mun, Eun Soo Nam
  • Patent number: 9276067
    Abstract: An SiC semiconductor device having a p-type 4H—SiC region formed on a part of a surface portion of an SiC substrate, a defect reduction layer formed in a surface portion of the 4H—SiC region, the defect reduction layer having C defect density <1015 cm?3 by introduction of carbon, a thickness of the defect reduction layer being equal to or less than 5 nm from a surface of the SiC substrate, a gate insulating film formed on the defect reduction layer, and a gate electrode formed on the gate insulating film.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: March 1, 2016
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Tatsuo Shimizu, Tetsuo Hatakeyama
  • Patent number: 9040345
    Abstract: A method of laser ablation for electrical contact to a buried electrically conducting layer in diamond comprising polishing a single crystal diamond substrate having a first carbon surface, implanting the diamond with a beam of 180 KeV followed by 150 KeV C+ ions at fluencies of 4×1015 ions/cm2 and 5×1015 ions/cm2 respectively, forming an electrically conducting carbon layer beneath the first carbon surface, and ablating the single crystal diamond which lies between the electrically conducting layer and the first carbon surface.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: May 26, 2015
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Bradford B. Pate, Matthew P. Ray, Jeffrey W. Baldwin
  • Patent number: 9029177
    Abstract: An optoelectronic semiconductor chip has a first semiconductor layer sequence which comprises a multiplicity of microdiodes, and a second semiconductor layer sequence which comprises an active region The first semiconductor layer sequence and the second semiconductor layer sequence are based on a nitride compound semiconductor material, the first semiconductor layer sequence is before the first semiconductor layer sequence in the direction of growth, and the microdiodes form an ESD protection for the active region.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: May 12, 2015
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Rainer Butendeich, Alexander Walter, Matthias Peter, Tobias Meyer, Tetsuya Taki, Hubert Maiwald
  • Patent number: 9029945
    Abstract: A semiconductor device includes a drift layer having a first conductivity type, a well region in the drift layer having a second conductivity type opposite the first conductivity type, and a source region in the well region. The source region has the first conductivity type and defines a channel region in the well region. The source region includes a lateral source region adjacent the channel region and a plurality of source contact regions extending away from the lateral source region opposite the channel region. A body contact region having the second conductivity type is between at least two of the plurality of source contact regions and is in contact with the well region. A source ohmic contact overlaps at least one of the source contact regions and the body contact region. A minimum dimension of a source contact area of the semiconductor device is defined by an area of overlap between the source ohmic contact and the at least one source contact region.
    Type: Grant
    Filed: May 6, 2011
    Date of Patent: May 12, 2015
    Assignee: Cree, Inc.
    Inventors: Sei-Hyung Ryu, Doyle Craig Capell, Lin Cheng, Sarit Dhar, Charlotte Jonas, Anant Agarwal, John Palmour
  • Patent number: 9012922
    Abstract: A substrate is provided with a main surface having an off angle of 5° or smaller relative to a reference plane. The reference plane is a {000-1} plane in the case of hexagonal system and is a {111} plane in the case of cubic system. A silicon carbide layer is epitaxially formed on the main surface of the substrate. The silicon carbide layer is provided with a trench having first and second side walls opposite to each other. Each of the first and second side walls includes a channel region. Further, each of the first and second side walls substantially includes one of a {0-33-8} plane and a {01-1-4} plane in the case of the hexagonal system and substantially includes a {100} plane in the case of the cubic system.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: April 21, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Toru Hiyoshi, Takeyoshi Masuda, Keiji Wada
  • Patent number: 9012923
    Abstract: A semiconductor device of an embodiment includes: an n-type first SiC epitaxial layer; a p-type second SiC epitaxial layer on the first SiC epitaxial layer containing a p-type impurity and an n-type impurity, the p-type impurity being an element A, the n-type impurity being an element D, the element A and the element D forming a combination of Al, Ga, or In and N, and/or a combination of B and P, the ratio of the concentration of the element D to the element A being higher than 0.33 but lower than 1.0; a surface region at the surface of the second SiC epitaxial layer containing the element A at a lower concentration than in the second SiC epitaxial layer, the ratio being higher than in the second SiC epitaxial layer; n-type first and second SiC regions; a gate insulating film; a gate electrode; a first electrode; and a second electrode.
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: April 21, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Johji Nishio, Tatsuo Shimizu, Ryosuke Iijima, Chiharu Ota, Takashi Shinohe
  • Patent number: 9000448
    Abstract: A MOSFET having a high mobility may be obtained by introducing nitrogen to the channel region or the interface between the gate dielectric film and the SiC substrate of the SiC MOSFET, but there is a problem that a normally-on MOSFET is obtained. For realizing both a high mobility and normally-off, and for providing a SiC MOSFET having further high reliability, nitrogen is introduced to the channel region of the SiC substrate or the interface between the gate dielectric film and the SiC substrate, and furthermore a metal oxide film having a thickness of 10%, or less of the total thickness of the gate dielectric film is inserted in the gate dielectric film.
    Type: Grant
    Filed: March 29, 2011
    Date of Patent: April 7, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Hirotaka Hamamura, Yasuhiro Shimamoto, Hiroyuki Okino
  • Patent number: 8993447
    Abstract: An apparatus includes a wafer with a number of openings therein. For each opening, an LED device is coupled to a conductive carrier and the wafer in a manner so that each of the coupled LED device and a portion of the conductive carrier at least partially fill the opening. A method of fabricating an LED device includes forming a number of openings in a wafer. The method also includes coupling light-emitting diode (LED) devices to conductive carriers. The LED devices with conductive carriers at least partially fill each of the openings.
    Type: Grant
    Filed: April 8, 2013
    Date of Patent: March 31, 2015
    Assignee: TSMC Solid State Lighting Ltd.
    Inventors: Hsing-Kuo Hsia, Chih-Kuang Yu, Hung-Yi Kuo, Chyi Shyuan Chern
  • Patent number: 8987753
    Abstract: Provided is a light emitting device, which includes a second conductive type semiconductor layer, an active layer, a first conductive type semiconductor layer, and a intermediate refraction layer. The active layer is disposed on the second conductive type semiconductor layer. The first conductive type semiconductor layer is disposed on the active layer. The intermediate refraction layer is disposed on the first conductive type semiconductor layer. The intermediate refraction layer has a refractivity that is smaller than that of the first conductive type semiconductor layer and is greater than that of air.
    Type: Grant
    Filed: July 1, 2013
    Date of Patent: March 24, 2015
    Assignee: LG Innotek Co., Ltd.
    Inventor: Hyo Kun Son
  • Patent number: 8981384
    Abstract: There are provided a high-quality semiconductor device having stable characteristics and a method for manufacturing such a semiconductor device. The semiconductor device includes a substrate having a main surface, and a silicon carbide layer. The silicon carbide layer is formed on the main surface of the substrate. The silicon carbide layer includes a side surface as an end surface inclined relative to the main surface. The side surface substantially includes one of a {03-3-8} plane and a {01-1-4} plane in a case where the silicon carbide layer is of hexagonal crystal type, and substantially includes a {100} plane in a case where the silicon carbide layer is of cubic crystal type.
    Type: Grant
    Filed: July 14, 2011
    Date of Patent: March 17, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Takeyoshi Masuda
  • Patent number: 8975156
    Abstract: A method of sealing a first wafer and a second wafer each made of semiconducting materials, including: implanting a metallic species in at least the first wafer, assembling the first wafer and the second wafer by molecular bonding, and after the molecular bonding, forming a metallic ohmic contact including alloys formed between the implanted metallic species and the semiconducting materials of the first wafer and the second wafer, the metallic ohmic contact being formed at an assembly interface between the first wafer and the second wafer, wherein the forming includes causing the implanted metallic species to diffuse towards the interface between the first wafer with the second wafer and beyond the interface.
    Type: Grant
    Filed: December 21, 2004
    Date of Patent: March 10, 2015
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Stephane Pocas, Hubert Moriceau, Jean-Francois Michaud
  • Patent number: 8957426
    Abstract: Embodiments of the invention provide a crystalline aluminum carbide layer, a laminate substrate having the crystalline aluminum carbide layer formed thereon, and a method of fabricating the same. The laminate substrate has a GaN layer including a GaN crystal and an AlC layer including an AlC crystal. Further, the method of fabricating the laminate substrate, which has the AlN layer including the AlN crystal and the AlC layer including the AlC crystal, includes supplying a carbon containing gas and an aluminum containing gas to grow the AlC layer.
    Type: Grant
    Filed: May 17, 2011
    Date of Patent: February 17, 2015
    Assignee: Seoul Viosys Co., Ltd.
    Inventor: Shiro Sakai
  • Patent number: 8952391
    Abstract: A silicon carbide vertical MOSFET having low ON-resistance and high blocking voltage. A first deposition film of low concentration silicon carbide of a first conductivity type is formed on the surface of a high concentration silicon carbide substrate of a first conductivity type. Formed on the first deposition film is a second deposition film that includes a high concentration gate region of a second conductivity type, with a first region removed selectively. A third deposition film is formed on the second deposition film, which includes a second region that is wider than the selectively removed first region, a high concentration source region of a first conductivity type, and a low concentration gate region of a second conductivity type. A low concentration base region of a first conductivity type is formed in contact with the first deposition film in the first and second regions.
    Type: Grant
    Filed: October 3, 2003
    Date of Patent: February 10, 2015
    Assignees: National Institute of Advanced Industrial Science and Technology, Sanyo Electric Co., Ltd.
    Inventors: Shinsuke Harada, Tsutomu Yatsuo, Kenji Fukuda, Mitsuo Okamoto, Kazuhiro Adachi, Seiji Suzuki
  • Patent number: 8895422
    Abstract: Production of an integrated circuit including an electrical contact on SiC is disclosed. One embodiment provides for production of an electrical contact on an SiC substrate, in which a conductive contact is produced on a boundary surface of the SiC substrate by irradiation and absorption of a laser pulse on an SiC substrate.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: November 25, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Roland Rupp, Thomas Gutt, Michael Treu
  • Patent number: 8890169
    Abstract: On a front surface of a region where a junction termination extension structure of a semiconductor device using silicon carbide is formed, a structure having an n-type semiconductor region with a concentration relatively higher than a concentration of an n?-type drift layer is formed. An edge of the junction termination extension structure located on a side away from an active region is surrounded from its bottom surface to its front surface by an n-type semiconductor region. By this means, it is possible to provide a device with a low resistance while ensuring a withstand voltage, or by decreasing the resistance of the device, it is possible to provide a device with low power loss.
    Type: Grant
    Filed: November 8, 2010
    Date of Patent: November 18, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Norifumi Kameshiro, Haruka Shimizu
  • Patent number: 8889533
    Abstract: A method of manufacturing a semiconductor device by using a substrate processing apparatus comprises a reaction chamber configured to process a plurality of substrates stacked at predetermined intervals, wherein a first gas flow from a first gas supply inlet and a second gas flow from a second gas supply inlet are crossed with each other before these gas flows reach the substrates. The method of manufacturing a semiconductor device comprises: loading the plurality of substrates into the reaction chamber; supplying a silicon-containing gas and a chlorine-containing gas from the first gas supply inlet into the reaction chamber, supplying a carbon-containing gas and a reducing gas from the second gas supply inlet into the reaction chamber and supplying a dopant-containing gas into the reaction chamber from the first gas supply inlet or the second gas supply inlet; and unloading the substrates from the reaction chamber.
    Type: Grant
    Filed: February 22, 2011
    Date of Patent: November 18, 2014
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Takafumi Sasaki, Yoshinori Imai, Koei Kuribayashi, Sadao Nakashima
  • Patent number: 8872193
    Abstract: The present invention provides a technique capable of realizing a silicon carbide semiconductor device having high performance and high reliability. By constituting a channel region by an n?-type, intrinsic, or p?-type channel region and a p+-type channel region, a high channel mobility and a high threshold voltage are realized. Further, by constituting a source region by an n+-type source region and an n++-type source region, and forming the n+-type source region between the p+-type channel region and the n++-type source region, an electric field in the p+-type channel region is relaxed to suppress deterioration of a gate insulating film, and also by electrically connecting a source wiring electrode to the n++-type source region, a contact resistance is decreased.
    Type: Grant
    Filed: May 9, 2013
    Date of Patent: October 28, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Naoki Tega, Digh Hisamoto, Takashi Takahama
  • Patent number: 8866155
    Abstract: A collector layer is made of silicon carbide having a first conductivity type. A switching element is provided on the collector layer. The switching element includes a junction gate for controlling a channel having a second conductivity type different from the first conductivity type.
    Type: Grant
    Filed: May 15, 2013
    Date of Patent: October 21, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Hideki Hayashi
  • Patent number: 8866156
    Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate and a contact electrode. The silicon carbide substrate includes an n type region and a p type region that makes contact with the n type region. The contact electrode makes contact with the n type region and the p type region. The contact electrode contains Ni atoms and Si atoms. The number of the Ni atoms is not less than 87% and not more than 92% of the total number of the Ni atoms and the Si atoms. Accordingly, there can be provided a silicon carbide semiconductor device, which can achieve ohmic contact with an n type impurity region and can achieve a low contact resistance for a p type impurity region, as well as a method for manufacturing such a silicon carbide semiconductor device.
    Type: Grant
    Filed: May 16, 2013
    Date of Patent: October 21, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shunsuke Yamada, Hideto Tamaso
  • Patent number: 8853792
    Abstract: Embodiments of transistors comprise a gate stack overlying a semiconductor material. The gate stack comprises a deposited oxide layer overlying the semiconductor material, an oxygen-diffusion barrier layer overlying the deposited oxide layer, a high-k dielectric layer overlying the oxygen-diffusion barrier layer, and a conductive material (e.g., an oxygen-gettering conductive material) overlying the high-k dielectric layer. When the conductive material is an oxygen-gettering conductive material, the oxygen-diffusion barrier layer prevents diffusion of oxygen from the deposited oxide layer to the oxygen-gettering conductive material.
    Type: Grant
    Filed: January 5, 2012
    Date of Patent: October 7, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Murshed M. Chowdhury, James K. Schaeffer
  • Patent number: 8829532
    Abstract: Semiconductor layer structure and a method for producing a structure are provided, including a substrate made of semiconductor material, on which a layer made of a second semiconductor material is situated, furthermore a region (3) enriched with impurity atoms, which region is situated either in layer (2) or at a specific depth below the interface between layer (2) and substrate (1), additionally a layer (4) within the region (3) enriched with impurity atoms, which layer comprises cavities produced by ion implantation, furthermore at least one epitaxial layer (6) applied to layer (2) and also a defect region (5) comprising dislocations and stacking faults within the layer (4) comprising cavities, the at least one epitaxial layer (6) being largely crack-free, and a residual strain of the at least one epitaxial layer (6) being less than or equal to 1 GPa.
    Type: Grant
    Filed: February 2, 2007
    Date of Patent: September 9, 2014
    Assignee: Siltronic AG
    Inventors: Brian Murphy, Maik Häberlen, Jörg Lindner, Bernd Stritzker
  • Patent number: 8822315
    Abstract: A method is disclosed for treating a silicon carbide substrate for improved epitaxial deposition thereon and for use as a precursor in the manufacture of devices such as light emitting diodes. The method includes the steps of implanting dopant atoms of a first conductivity type into the first surface of a conductive silicon carbide wafer having the same conductivity type as the implanting ions at one or more predetermined dopant concentrations and implant energies to form a dopant profile, annealing the implanted wafer, and growing an epitaxial layer on the implanted first surface of the wafer.
    Type: Grant
    Filed: December 22, 2004
    Date of Patent: September 2, 2014
    Assignee: Cree, Inc.
    Inventors: Davis Andrew McClure, Alexander Suvorov, John Adam Edmond, David Beardsley Slater, Jr.
  • Patent number: 8786027
    Abstract: In sophisticated semiconductor devices, replacement gate approaches may be applied in combination with a process strategy for implementing a strain-inducing semiconductor material, wherein superior proximity of the strain-inducing semiconductor material and/or superior robustness of the replacement gate approach may be achieved by forming the initial gate electrode structures with superior uniformity and providing at least one cavity for implementing the strained channel regions in a very advanced manufacturing stage, i.e., after completing the basic transistor configuration.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: July 22, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Uwe Griebenow, Jan Hoentschel, Thilo Scheiper, Sven Beyer
  • Patent number: 8772891
    Abstract: A lateral overflow drain and a channel stop are fabricated using a double mask process. Each lateral overflow drain is formed within a respective channel stop. Due to the use of two mask layers, one edge of each lateral overflow drain is aligned, or substantially aligned, with an edge of a respective channel stop.
    Type: Grant
    Filed: October 30, 2009
    Date of Patent: July 8, 2014
    Assignee: Truesense Imaging, Inc.
    Inventors: Edmund K. Banghart, Eric G. Stevens, Hung Q. Doan
  • Patent number: 8742426
    Abstract: A semiconductor device includes an AlGaN layer that is provided on a SiC substrate and has an acceptor concentration equal to or higher than a donor concentration, a GaN layer provided on the AlGaN layer, and an electron supply layer that is provided on the GaN layer and has a band gap greater than that of GaN.
    Type: Grant
    Filed: July 27, 2011
    Date of Patent: June 3, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Ken Nakata, Isao Makabe, Keiichi Yui
  • Patent number: 8728923
    Abstract: A manufacturing method of a semiconductor device having an ohmic electrode is disclosed. The manufacturing method includes: forming a metal thin film on a rear surface of a semiconductor substrate; forming an ohmic electrode by laser annealing by irradiating the metal thin film with laser beam; and dicing the semiconductor substrate into chips by cutting at a dicing region of the semiconductor substrate. In forming the ohmic electrode, laser irradiation of the metal thin film is performed on a chip-by-chip basis while the dicing region is not being irradiated with the laser beam.
    Type: Grant
    Filed: September 25, 2012
    Date of Patent: May 20, 2014
    Assignee: DENSO CORPORATION
    Inventors: Jun Kawai, Tetsuji Kondou, Kazuhiko Sugiura, Nobuyuki Kato
  • Patent number: 8723259
    Abstract: A SiC semiconductor device capable of increasing a switching speed without destroying a gate insulating film. In addition, in a SiC-MOSFET including an n-type semiconductor substrate formed of SiC, a p-type semiconductor layer is entirely or partially provided on an upper surface of a p-type well layer that has a largest area of the transverse plane among a plurality of p-type well layers provided in an n-type drift layer and is arranged on an outermost periphery immediately below a gate electrode pad. It is preferable that a concentration of an impurity contained in the p-type semiconductor layer be larger than that of the p-type well layer.
    Type: Grant
    Filed: February 23, 2010
    Date of Patent: May 13, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yukiyasu Nakao, Masayuki Imaizumi, Shuhei Nakata, Naruhisa Miura
  • Patent number: 8710510
    Abstract: An insulated gate bipolar transistor (IGBT) includes a substrate having a first conductivity type, a drift layer having a second conductivity type opposite the first conductivity type, and a well region in the drift layer and having the first conductivity type. An epitaxial channel adjustment layer is on the drift layer and has the second conductivity type. An emitter region extends from a surface of the epitaxial channel adjustment layer through the epitaxial channel adjustment layer and into the well region. The emitter region has the second conductivity type and at least partially defines a channel region in the well region adjacent to the emitter region. A gate oxide layer is on the channel region, and a gate is on the gate oxide layer. Related methods are also disclosed.
    Type: Grant
    Filed: June 18, 2007
    Date of Patent: April 29, 2014
    Assignee: Cree, Inc.
    Inventors: Qingchun Zhang, Sei-Hyung Ryu, Charlotte Jonas, Anant K. Agarwal
  • Patent number: 8703566
    Abstract: A memory device includes an array of memory cells and peripheral devices. At least some of the individual memory cells include carbonated portions that contain SiC. At least some of the peripheral devices do not include any carbonated portions. A transistor includes a first source/drain, a second source/drain, a channel including a carbonated portion of a semiconductive substrate that contains SiC between the first and second sources/drains and a gate operationally associated with opposing sides of the channel.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: April 22, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Chandra Mouli
  • Patent number: 8697551
    Abstract: Embodiments of the invention provide a crystalline aluminum carbide thin film, a semiconductor substrate having the crystalline aluminum carbide thin film formed thereon, and a method of fabricating the same. Further, the method of fabricating the AlC thin film includes supplying a carbon containing gas and an aluminum containing gas to a furnace, to growing AlC crystals on a substrate.
    Type: Grant
    Filed: April 26, 2013
    Date of Patent: April 15, 2014
    Assignee: Seoul Opto Device Co., Ltd.
    Inventor: Shiro Sakai
  • Patent number: 8697555
    Abstract: The invention offers a method of producing a semiconductor device that can suppress the worsening of the property due to surface roughening of a wafer by sufficiently suppressing the surface roughening of the wafer in the heat treatment step and a semiconductor device in which the worsening of the property caused by the surface roughening is suppressed. The method of producing a MOSFET as a semiconductor device is provided with a step of preparing a wafer 3 made of silicon carbide and an activation annealing step that performs activation annealing by heating the wafer 3. In the activation annealing step, the wafer 3 is heated in an atmosphere containing a vapor of silicon carbide generated from the SiC piece 61, which is a generating source other than the wafer 3.
    Type: Grant
    Filed: August 21, 2008
    Date of Patent: April 15, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Kazuhiro Fujikawa, Shin Harada, Yasuo Namikawa, Takeyoshi Masuda
  • Patent number: 8610131
    Abstract: An IGBT includes a groove provided in a silicon carbide semiconductor layer, a body region of a first conductivity type provided in the silicon carbide semiconductor layer, and an insulating film covering at least a sidewall surface of the groove, the sidewall surface of the groove being a surface having an off angle of 50° or more and 65° or less with respect to a {0001} plane, the sidewall surface of the groove including a surface of the body region, the insulating film being in contact with at least the surface of the body region at the sidewall surface of the groove, and a first conductivity type impurity concentration in the body region being 5×1016 cm?3 or more.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: December 17, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Wada, Takeyoshi Masuda, Misako Honaga, Toru Hiyoshi
  • Patent number: 8586996
    Abstract: A semiconductor device includes a SiC substrate, a semiconductor layer formed on the SiC substrate, a via hole penetrating through the SiC substrate and the semiconductor layer, a Cu pad that is formed on the semiconductor layer and is in contact with the via hole, and a barrier layer covering an upper face and side faces of the Cu pad, and restrains Cu diffusion.
    Type: Grant
    Filed: July 25, 2011
    Date of Patent: November 19, 2013
    Assignee: Sumitomo Electric Device Innovations, Inc.
    Inventor: Masahiro Nishi
  • Patent number: 8563988
    Abstract: As viewed along a normal to the principal surface of a substrate 101, this semiconductor element 100 has a unit cell region 100ul and a terminal region 100f located between the unit cell region and an edge of the semiconductor element. The terminal region 100f includes a ring region 103f of a second conductivity type which is arranged in a first silicon carbide semiconductor layer 102 so as to contact with a drift region 102d. The ring region includes a high concentration ring region 103af which contacts with the surface of the first silicon carbide semiconductor layer and a low concentration ring region 103bf which contains an impurity of the second conductivity type at a lower concentration than in the high concentration ring region and of which the bottom contacts with the first silicon carbide semiconductor layer. A side surface of the high concentration ring region 103af contacts with the drift region 102d.
    Type: Grant
    Filed: October 27, 2011
    Date of Patent: October 22, 2013
    Assignee: Panasonic Corporation
    Inventors: Masao Uchida, Koutarou Tanaka
  • Patent number: 8546923
    Abstract: Method for manufacturing a rigid power module with a layer that is electrically insulating and conducts well thermally and has been deposited as a coating, the structure having sprayed-on particles that are fused to each other, of at least one material that is electrically insulating and conducts well thermally, having the following steps: manufacturing a one-piece lead frame; populating the lead frame with semiconductor devices, possible passive components, and bonding corresponding connections, inserting the thus populated lead frame into a compression mold so that accessibility of part areas of the lead frame is ensured, pressing a thermosetting compression molding compound into the mold while enclosing the populated lead frame, coating the underside of the thus populated lead frame by thermal spraying in at least the electrically conducting areas and overlapping also the predominant areas of the spaces, filled with mold compound.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: October 1, 2013
    Assignee: Danfoss Silicon Power GmbH
    Inventors: Ronald Eisele, Mathias Kock, Teoman Senyildiz
  • Patent number: 8519486
    Abstract: A semiconductor device includes a MOS transistor, a source electrode and a drain electrode on the MOS transistor each include a first carbon doped silicon layer including carbon at a first carbon concentration and phosphorus at a first phosphorus concentration and a second carbon doped silicon layer over the first silicon carbide layer, which includes phosphorus at a second phosphorus concentration higher than the first phosphorus concentration, and which includes carbon at a second carbon concentration less than or equal to the first carbon concentration.
    Type: Grant
    Filed: May 19, 2010
    Date of Patent: August 27, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Naoyoshi Tamura
  • Patent number: 8507922
    Abstract: Disclosed is a silicon carbide substrate which has less high frequency loss and excellent heat dissipating characteristics. The silicon carbide substrate (S) is provided with a first silicon carbide layer (1), which is composed of a polycrystalline silicon carbide, and a second silicon carbide layer (2), which is composed of polycrystalline silicon carbide formed on the surface of the first silicon carbide layer. The second silicon carbide layer (2) has a high-frequency loss smaller than that of the first silicon carbide layer (1), the first silicon carbide layer (1) has a thermal conductivity higher than that of the second silicon carbide layer (2), and on the surface side of the second silicon carbide layer (2), the high-frequency loss at a frequency of 20 GHz is 2 dB/mm or less, and the thermal conductivity is 200 W/mK or more.
    Type: Grant
    Filed: July 5, 2011
    Date of Patent: August 13, 2013
    Assignees: Mitsui Engineering & Shipbuilding Co., Ltd., Admap Inc.
    Inventors: Satoshi Kawamoto, Masaki Nakamura
  • Patent number: 8501571
    Abstract: A semiconductor device includes a MOS transistor, a source electrode and a drain electrode on the MOS transistor each include a first carbon doped silicon layer including carbon at a first carbon concentration and phosphorus at a first phosphorus concentration and a second carbon doped silicon layer over the first silicon carbide layer, which includes phosphorus at a second phosphorus concentration higher than the first phosphorus concentration, and which includes carbon at a second carbon concentration less than or equal to the first carbon concentration.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: August 6, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Naoyoshi Tamura
  • Patent number: 8497208
    Abstract: A method for producing a semiconductor device including a first conductor disposed on a semiconductor substrate; an oxygen-containing insulation film disposed on the semiconductor substrate and on the first conductor, the insulation film having a contact hole which extends to the first conductor and a trench which is connected to an upper portion of the contact hole; a zirconium oxide film disposed on a side surface of the contact hole and a side surface and a bottom surface of the trench; a zirconium film disposed on the zirconium oxide film inside the contact hole and inside the trench; and a second conductor composed of Cu embedded into the contact hole and into the trench.
    Type: Grant
    Filed: September 16, 2010
    Date of Patent: July 30, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Michie Sunayama, Yoshiyuki Nakao, Noriyoshi Shimizu
  • Patent number: 8492827
    Abstract: Silicon carbide metal-oxide semiconductor field effect transistors (MOSFETs) may include an n-type silicon carbide drift layer, a first p-type silicon carbide region adjacent the drift layer and having a first n-type silicon carbide region therein, an oxide layer on the drift layer, and an n-type silicon carbide limiting region disposed between the drift layer and a portion of the first p-type region. The limiting region may have a carrier concentration that is greater than the carrier concentration of the drift layer.
    Type: Grant
    Filed: March 15, 2011
    Date of Patent: July 23, 2013
    Assignee: Cree, Inc.
    Inventor: Sei-Hyung Ryu
  • Patent number: 8486835
    Abstract: Non-production wafers of polycrystalline silicon are placed in non-production slots of a support tower for thermal processing monocrystalline silicon wafers. They may have thicknesses of 0.725 to 2 mm and be roughened on both sides. Nitride may be grown on the non-production wafers to a thickness of over 2 ?m without flaking. The polycrystalline silicon is preferably randomly oriented Czochralski polysilicon grown using a randomly oriented seed, for example, CVD grown silicon. Both sides are ground to introduce sub-surface damage and then oxidized and etch cleaned. An all-silicon hot zone of a thermal furnace, for example, depositing a nitride layer, may include a silicon support tower placed within a silicon liner and supporting the polysilicon non-production wafers with silicon injector tube providing processing gas within the liner.
    Type: Grant
    Filed: September 18, 2009
    Date of Patent: July 16, 2013
    Inventors: James E. Boyle, Reese Reynolds, Raanan Y. Zehavi, Tom L. Cadwell, Doris Mytton
  • Patent number: 8476646
    Abstract: Provided is a light emitting device, which includes a second conductive type semiconductor layer, an active layer, a first conductive type semiconductor layer, and a intermediate refraction layer. The active layer is disposed on the second conductive type semiconductor layer. The first conductive type semiconductor layer is disposed on the active layer. The intermediate refraction layer is disposed on the first conductive type semiconductor layer. The intermediate refraction layer has a refractivity that is smaller than that of the first conductive type semiconductor layer and is greater than that of air.
    Type: Grant
    Filed: November 12, 2010
    Date of Patent: July 2, 2013
    Assignee: LG Innotek Co., Ltd.
    Inventor: Hyo Kun Son
  • Patent number: 8466474
    Abstract: There is provided a silicon carbide semiconductor device equipped with an ohmic electrode that exhibits both low contact resistance and favorable surface conditions, the silicon carbide semiconductor device including a p-type silicon carbide single crystal, and an ohmic electrode for the p-type silicon carbide single crystal, wherein the ohmic electrode includes an alloy layer containing at least titanium, aluminum and silicon, and ratios of titanium, aluminum, and silicon in the alloy layer are Al: 40 to 70% by mass, Ti: 20 to 50% by mass, and Si: 1 to 15% by mass.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: June 18, 2013
    Assignee: Showa Denko K.K.
    Inventor: Kotaro Yano
  • Patent number: 8455314
    Abstract: In sophisticated semiconductor devices, replacement gate approaches may be applied in combination with a process strategy for implementing a strain-inducing semiconductor material, wherein superior proximity of the strain-inducing semiconductor material and/or superior robustness of the replacement gate approach may be achieved by forming the initial gate electrode structures with superior uniformity and providing at least one cavity for implementing the strained channel regions in a very advanced manufacturing stage, i.e., after completing the basic transistor configuration.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: June 4, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Uwe Griebenow, Jan Hoentschel, Thilo Scheiper, Sven Beyer