Abstract: A silicon carbide substrate according to the present disclosure is a silicon carbide substrate that includes a first main surface and a second main surface opposite to the first main surface, and is made of silicon carbide having a polytype of 4H. The first main surface has a maximum diameter of more than or equal to 140 mm. The first main surface is a {0001} plane or a plane inclined at an off angle of more than 0° and less than or equal to 8° relative to the {0001} plane. Half-widths of a peak corresponding to a folded mode of a longitudinal optical branch of a Raman spectrum of the silicon carbide substrate within a plane of the first main surface have an average value of less than 2.5 cm?1, and a standard deviation of less than or equal to 0.06 cm?1.

Abstract: A semiconductor substrate includes a drift layer of a first layer formed of a single crystal SiC semiconductor and a buffer layer and a substrate layer of a second layer that is formed of a SiC semiconductor which includes a polycrystalline structure and is formed on the surface of the first layer, in which the second layer (12) is formed on the surface of the drift layer of the first layer by means of CVD growth, the drift layer of the first layer is formed by means of epitaxial growth, and accordingly, defects occurring at a junction interface of the semiconductor substrate including the single crystal SiC layer and the polycrystal SiC layer are suppressed, and manufacturing costs are also reduced.

Abstract: An optical device includes a vanadium compensated, high resistivity, SiC single crystal of 6H or 4H polytype, for transmitting light having a wavelength in a range of from 420 nm to 4.5 ?m. The device may include a window, lens, prism, or waveguide. A system includes a source for generating light having a wavelength in a range of from 420 nm to 4.5 ?m, and a device for receiving and transmitting the light, where the device includes a vanadium compensated, high resistivity, SiC single crystal of 6H or 4H polytype. The disclosure also relates to crystals and methods for optical applications, including an aluminum doped SiC crystal having residual nitrogen and boron impurities, where the aluminum concentration is greater than the combined concentrations of nitrogen and boron, and where an optical absorption coefficient is less than about 0.4 cm?1 at a wavelength between about 400 nm to about 800 nm.

Abstract: Silicon carbide (SiC) wafers and related methods are disclosed that include large diameter SiC wafers with wafer shape characteristics suitable for semiconductor manufacturing. Large diameter SiC wafers are disclosed that have reduced deformation related to stress and strain effects associated with forming such SiC wafers. As described herein, wafer shape and flatness characteristics may be improved by reducing crystallographic stress profiles during growth of SiC crystal boules or ingots. Wafer shape and flatness characteristics may also be improved after individual SiC wafers have been separated from corresponding SiC crystal boules. In this regard, SiC wafers and related methods are disclosed that include large diameter SiC wafers with suitable crystal quality and wafer shape characteristics including low values for wafer bow, warp, and thickness variation.

Abstract: A semiconductor substrate includes a drift layer of a first layer formed of a single crystal SiC semiconductor and a buffer layer and a substrate layer of a second layer that is formed of a SiC semiconductor which includes a polycrystalline structure and is formed on the surface of the first layer, in which the second layer (12) is formed on the surface of the drift layer of the first layer by means of CVD growth, the drift layer of the first layer is formed by means of epitaxial growth, and accordingly, defects occurring at a junction interface of the semiconductor substrate including the single crystal SiC layer and the polycrystal SiC layer are suppressed, and manufacturing costs are also reduced.

Abstract: A method for forming a silicon carbide material with a plurality of negatively charged silicon mono-vacancy defects includes irradiating a silicon carbide sample, annealing the irradiated silicon carbide sample in an annealing operation, and quenching the annealed silicon carbide sample. Quenching may include heating the annealed silicon carbide sample to a maximum temperature and quenching the annealed silicon carbide sample to form the silicon carbide sample with the plurality of negatively charged silicon mono-vacancy defects.

Abstract: An embodiment relates to a n-type planar gate DMOSFET comprising a Silicon Carbide (SiC) substrate. The SiC substrate includes a N+ substrate, a N? drift layer, a P-well region and a first N+ source region within each P-well region. A second N+ source region is formed between the P-well region and a source metal via a silicide layer. During third quadrant operation of the DMOSFET, the second N+ source region starts depleting when a source terminal is positively biased with respect to a drain terminal. The second N+ source region impacts turn-on voltage of body diode regions of the DMOSFET by establishing short-circuitry between the P-well region and the source metal when the second N+ source region is completely depleted.

Abstract: According to an embodiment, provided is a semiconductor device including: a first electrode; a second electrode; and a silicon carbide layer disposed between the first electrode and the second electrode, the silicon carbide layer including: a first silicon carbide region of an n-type; and a second silicon carbide region disposed between the first silicon carbide region and the first electrode, the second silicon carbide being in contact with the first electrode, and the second silicon carbide containing one oxygen atom bonding with four silicon atoms.

Abstract: In a general aspect, a silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) can include a substrate of a first conductivity type, a drift region of the first conductivity type disposed on the substrate, a spreading layer of the first conductivity type disposed in the drift region, a body region of a second conductivity type disposed in the spreading layer, and a source region of the first conductivity type disposed in the body region. The SiC MOSFET can also include a gate structure that includes a gate oxide layer, an aluminum nitride layer disposed on the gate oxide layer, and a gallium nitride layer of the second conductivity disposed on the aluminum nitride layer.

Abstract: The present application relates to semiconductor photodetectors, in particular to a silicon carbide-based UV-visible-NIR full-spectrum-responsive photodetector and a method for fabricating the same. The photodetector includes a silicon carbide substrate, and metal counter electrodes and a surface plasmon polariton nanostructure arranged thereon. The silicon carbide substrate and the metal counter electrodes constitute a metal-semiconductor-metal photodetector with coplanar electrodes. When the ultraviolet light is input, free carriers directly generated in silicon carbide are collected by an external circuit to generate electrical signals. When the visible light is input, hot carriers generated in the surface plasmon polariton nanostructure tunnel into the silicon carbide semiconductor to become free carriers to generate electrical signals.

Abstract: The present disclosure provides high-purity semi-insulating single-crystal silicon carbide wafer and crystal which include one polytype single crystal. The semi-insulating single-crystal silicon carbide wafer has silicon vacancy inside, wherein the silicon-vacancy concentration is greater than 5E11 cm{circumflex over (?)}-3.

Abstract: A substrate processing method is described for etching silicon carbide films for resist underlayer applications. The method includes providing a substrate containing a silicon carbide film thereon, and a photoresist layer defining a pattern over the silicon carbide film, plasma-exciting an etching gas containing a fluorocarbon-containing gas and an oxygen-containing gas, and exposing the substrate to the plasma-excited etching gas to transfer the pattern to the silicon carbide film, where at least a portion of a thickness of the photoresist layer survives the exposing. For example, the photoresist layer includes an EUV resist layer and the etching gas includes C4F8 gas, O2 gas, and Ar gas. In another example, the exposing includes exposing the substrate to a) a plasma-excited etching gas containing C4F8 gas, O2 gas, and Ar gas, and b) exposing the substrate to a plasma-excited Ar gas, where steps a) and b) are sequentially performed at least once.

Abstract: Embodiments may relate to a microelectronic package that includes a die and a backside metallization (BSM) layer positioned on the face of the die. The BSM layer may include a feature that indicates that the BSM layer was formed on the face of the die by a masked deposition technique. Other embodiments may be described or claimed.

Abstract: According to an embodiment, provided is a semiconductor device including: a first electrode; a second electrode; and a silicon carbide layer disposed between the first electrode and the second electrode, the silicon carbide layer including: a first silicon carbide region of an n-type; and a second silicon carbide region disposed between the first silicon carbide region and the first electrode, the second silicon carbide being in contact with the first electrode, and the second silicon carbide containing one oxygen atom bonding with four silicon atoms.

Abstract: A die stack assembly includes first and second power semiconductor device dice. The first die has a P type peripheral edge separation structure that extends from the top planar semiconductor surface of the first die all the way to the bottom planar semiconductor surface of the die, and that is doped at least in part with aluminum. The backside of the first die is mounted to the backside of the second die. A metal feature that is not covered with passivation, and that can serve as a bonding pad, is disposed on part of the peripheral edge separation structure. A metal member (for example, a bond wire or metal clip) contacts the metal feature such that an electrical connection is established from the metal member, through the metal feature, through the peripheral edge separation structure of the first die, and to an electrode of the second die.

Abstract: A silicon carbide semiconductor device, including a silicon carbide semiconductor structure, an insulated gate structure, an interlayer insulating film formed on the insulated gate structure, a poly-silicon film formed on the interlayer insulating film, and a main electrode formed on the poly-silicon film and in electrical connection with the silicon carbide semiconductor structure. The insulated gate structure includes a gate insulating film, which is a silicon dioxide film contacting the silicon carbide semiconductor structure, and a gate electrode formed on the gate insulating film.

Abstract: A device, apparatus and method for trapping metal ions and detecting metal ion contamination in a solution provide a semiconductor device formed on a semiconductor substrate and including an N-well formed over a P-type substrate and at least a contact portion of the N-well in electrical contact with the solution. When the semiconductor device is optically illuminated, a P/N junction is formed as a result of photovoltaic phenomena. Metal ions from the solution migrate to the contact area due to the voltage created at the P/N junction. The semiconductor device includes a conductive structure with conductive features separated by a gap and therefore in an initially electrically open state. When the ions migrate to the contact area, they precipitate, at least partially bridging the gap and creating conductance through the conductive structure. The conductance may be measured to determine the amount of metal ion contamination.

Abstract: The method includes the steps of: preparing a single crystal SiC including an upper surface 10a and a lower surface 10b and provided with a micropipe 11 penetrating from the upper surface 10a to the lower surface 10b; forming a first seed layer 21 made of a metal material on the upper surface 10a of the single crystal SiC; and forming a first plated layer 31 on the first seed layer 21 so as to close an upper end of the micropipe 11, using an electroplating method.

Abstract: A thermally conductive and electrically insulating layer is provided over a semiconductor structure.

Abstract: III-nitride materials are generally described herein, including material structures comprising III-nitride material regions and silicon-containing substrates. Certain embodiments are related to gallium nitride materials and material structures comprising gallium nitride material regions and silicon-containing substrates.

Abstract: A semiconductor device may include a substrate having a lower via-hole, an epitaxial layer having an opening exposing a top surface of the substrate, a semiconductor chip disposed on the top surface of the substrate and including first, second, and third electrodes, an upper metal layer connected to the first electrode, a supporting substrate disposed on the upper metal layer and having an upper via-hole, an upper pad disposed on the substrate and extending into the upper via-hole, a lower pad connected to the second electrode in the opening, and a lower metal layer covering a bottom surface of the substrate and connected to the lower pad through the lower via-hole.

Abstract: An SiC semiconductor device having a p-type 4H—SiC region formed on a part of a surface portion of an SiC substrate, a defect reduction layer formed in a surface portion of the 4H—SiC region, the defect reduction layer having C defect density <1015 cm?3 by introduction of carbon, a thickness of the defect reduction layer being equal to or less than 5 nm from a surface of the SiC substrate, a gate insulating film formed on the defect reduction layer, and a gate electrode formed on the gate insulating film.

Abstract: A method of laser ablation for electrical contact to a buried electrically conducting layer in diamond comprising polishing a single crystal diamond substrate having a first carbon surface, implanting the diamond with a beam of 180 KeV followed by 150 KeV C+ ions at fluencies of 4×1015 ions/cm2 and 5×1015 ions/cm2 respectively, forming an electrically conducting carbon layer beneath the first carbon surface, and ablating the single crystal diamond which lies between the electrically conducting layer and the first carbon surface.

Abstract: A semiconductor device includes a drift layer having a first conductivity type, a well region in the drift layer having a second conductivity type opposite the first conductivity type, and a source region in the well region. The source region has the first conductivity type and defines a channel region in the well region. The source region includes a lateral source region adjacent the channel region and a plurality of source contact regions extending away from the lateral source region opposite the channel region. A body contact region having the second conductivity type is between at least two of the plurality of source contact regions and is in contact with the well region. A source ohmic contact overlaps at least one of the source contact regions and the body contact region. A minimum dimension of a source contact area of the semiconductor device is defined by an area of overlap between the source ohmic contact and the at least one source contact region.

Abstract: An optoelectronic semiconductor chip has a first semiconductor layer sequence which comprises a multiplicity of microdiodes, and a second semiconductor layer sequence which comprises an active region The first semiconductor layer sequence and the second semiconductor layer sequence are based on a nitride compound semiconductor material, the first semiconductor layer sequence is before the first semiconductor layer sequence in the direction of growth, and the microdiodes form an ESD protection for the active region.

Abstract: A substrate is provided with a main surface having an off angle of 5° or smaller relative to a reference plane. The reference plane is a {000-1} plane in the case of hexagonal system and is a {111} plane in the case of cubic system. A silicon carbide layer is epitaxially formed on the main surface of the substrate. The silicon carbide layer is provided with a trench having first and second side walls opposite to each other. Each of the first and second side walls includes a channel region. Further, each of the first and second side walls substantially includes one of a {0-33-8} plane and a {01-1-4} plane in the case of the hexagonal system and substantially includes a {100} plane in the case of the cubic system.

Abstract: A semiconductor device of an embodiment includes: an n-type first SiC epitaxial layer; a p-type second SiC epitaxial layer on the first SiC epitaxial layer containing a p-type impurity and an n-type impurity, the p-type impurity being an element A, the n-type impurity being an element D, the element A and the element D forming a combination of Al, Ga, or In and N, and/or a combination of B and P, the ratio of the concentration of the element D to the element A being higher than 0.33 but lower than 1.0; a surface region at the surface of the second SiC epitaxial layer containing the element A at a lower concentration than in the second SiC epitaxial layer, the ratio being higher than in the second SiC epitaxial layer; n-type first and second SiC regions; a gate insulating film; a gate electrode; a first electrode; and a second electrode.

Abstract: A MOSFET having a high mobility may be obtained by introducing nitrogen to the channel region or the interface between the gate dielectric film and the SiC substrate of the SiC MOSFET, but there is a problem that a normally-on MOSFET is obtained. For realizing both a high mobility and normally-off, and for providing a SiC MOSFET having further high reliability, nitrogen is introduced to the channel region of the SiC substrate or the interface between the gate dielectric film and the SiC substrate, and furthermore a metal oxide film having a thickness of 10%, or less of the total thickness of the gate dielectric film is inserted in the gate dielectric film.

Abstract: An apparatus includes a wafer with a number of openings therein. For each opening, an LED device is coupled to a conductive carrier and the wafer in a manner so that each of the coupled LED device and a portion of the conductive carrier at least partially fill the opening. A method of fabricating an LED device includes forming a number of openings in a wafer. The method also includes coupling light-emitting diode (LED) devices to conductive carriers. The LED devices with conductive carriers at least partially fill each of the openings.

Abstract: Provided is a light emitting device, which includes a second conductive type semiconductor layer, an active layer, a first conductive type semiconductor layer, and a intermediate refraction layer. The active layer is disposed on the second conductive type semiconductor layer. The first conductive type semiconductor layer is disposed on the active layer. The intermediate refraction layer is disposed on the first conductive type semiconductor layer. The intermediate refraction layer has a refractivity that is smaller than that of the first conductive type semiconductor layer and is greater than that of air.

Abstract: There are provided a high-quality semiconductor device having stable characteristics and a method for manufacturing such a semiconductor device. The semiconductor device includes a substrate having a main surface, and a silicon carbide layer. The silicon carbide layer is formed on the main surface of the substrate. The silicon carbide layer includes a side surface as an end surface inclined relative to the main surface. The side surface substantially includes one of a {03-3-8} plane and a {01-1-4} plane in a case where the silicon carbide layer is of hexagonal crystal type, and substantially includes a {100} plane in a case where the silicon carbide layer is of cubic crystal type.

Abstract: A method of sealing a first wafer and a second wafer each made of semiconducting materials, including: implanting a metallic species in at least the first wafer, assembling the first wafer and the second wafer by molecular bonding, and after the molecular bonding, forming a metallic ohmic contact including alloys formed between the implanted metallic species and the semiconducting materials of the first wafer and the second wafer, the metallic ohmic contact being formed at an assembly interface between the first wafer and the second wafer, wherein the forming includes causing the implanted metallic species to diffuse towards the interface between the first wafer with the second wafer and beyond the interface.

Abstract: Embodiments of the invention provide a crystalline aluminum carbide layer, a laminate substrate having the crystalline aluminum carbide layer formed thereon, and a method of fabricating the same. The laminate substrate has a GaN layer including a GaN crystal and an AlC layer including an AlC crystal. Further, the method of fabricating the laminate substrate, which has the AlN layer including the AlN crystal and the AlC layer including the AlC crystal, includes supplying a carbon containing gas and an aluminum containing gas to grow the AlC layer.

Abstract: A silicon carbide vertical MOSFET having low ON-resistance and high blocking voltage. A first deposition film of low concentration silicon carbide of a first conductivity type is formed on the surface of a high concentration silicon carbide substrate of a first conductivity type. Formed on the first deposition film is a second deposition film that includes a high concentration gate region of a second conductivity type, with a first region removed selectively. A third deposition film is formed on the second deposition film, which includes a second region that is wider than the selectively removed first region, a high concentration source region of a first conductivity type, and a low concentration gate region of a second conductivity type. A low concentration base region of a first conductivity type is formed in contact with the first deposition film in the first and second regions.

Abstract: Production of an integrated circuit including an electrical contact on SiC is disclosed. One embodiment provides for production of an electrical contact on an SiC substrate, in which a conductive contact is produced on a boundary surface of the SiC substrate by irradiation and absorption of a laser pulse on an SiC substrate.

Abstract: On a front surface of a region where a junction termination extension structure of a semiconductor device using silicon carbide is formed, a structure having an n-type semiconductor region with a concentration relatively higher than a concentration of an n?-type drift layer is formed. An edge of the junction termination extension structure located on a side away from an active region is surrounded from its bottom surface to its front surface by an n-type semiconductor region. By this means, it is possible to provide a device with a low resistance while ensuring a withstand voltage, or by decreasing the resistance of the device, it is possible to provide a device with low power loss.

Abstract: A method of manufacturing a semiconductor device by using a substrate processing apparatus comprises a reaction chamber configured to process a plurality of substrates stacked at predetermined intervals, wherein a first gas flow from a first gas supply inlet and a second gas flow from a second gas supply inlet are crossed with each other before these gas flows reach the substrates. The method of manufacturing a semiconductor device comprises: loading the plurality of substrates into the reaction chamber; supplying a silicon-containing gas and a chlorine-containing gas from the first gas supply inlet into the reaction chamber, supplying a carbon-containing gas and a reducing gas from the second gas supply inlet into the reaction chamber and supplying a dopant-containing gas into the reaction chamber from the first gas supply inlet or the second gas supply inlet; and unloading the substrates from the reaction chamber.

Abstract: The present invention provides a technique capable of realizing a silicon carbide semiconductor device having high performance and high reliability. By constituting a channel region by an n?-type, intrinsic, or p?-type channel region and a p+-type channel region, a high channel mobility and a high threshold voltage are realized. Further, by constituting a source region by an n+-type source region and an n++-type source region, and forming the n+-type source region between the p+-type channel region and the n++-type source region, an electric field in the p+-type channel region is relaxed to suppress deterioration of a gate insulating film, and also by electrically connecting a source wiring electrode to the n++-type source region, a contact resistance is decreased.

Abstract: A collector layer is made of silicon carbide having a first conductivity type. A switching element is provided on the collector layer. The switching element includes a junction gate for controlling a channel having a second conductivity type different from the first conductivity type.

Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate and a contact electrode. The silicon carbide substrate includes an n type region and a p type region that makes contact with the n type region. The contact electrode makes contact with the n type region and the p type region. The contact electrode contains Ni atoms and Si atoms. The number of the Ni atoms is not less than 87% and not more than 92% of the total number of the Ni atoms and the Si atoms. Accordingly, there can be provided a silicon carbide semiconductor device, which can achieve ohmic contact with an n type impurity region and can achieve a low contact resistance for a p type impurity region, as well as a method for manufacturing such a silicon carbide semiconductor device.

Abstract: Embodiments of transistors comprise a gate stack overlying a semiconductor material. The gate stack comprises a deposited oxide layer overlying the semiconductor material, an oxygen-diffusion barrier layer overlying the deposited oxide layer, a high-k dielectric layer overlying the oxygen-diffusion barrier layer, and a conductive material (e.g., an oxygen-gettering conductive material) overlying the high-k dielectric layer. When the conductive material is an oxygen-gettering conductive material, the oxygen-diffusion barrier layer prevents diffusion of oxygen from the deposited oxide layer to the oxygen-gettering conductive material.

Abstract: Semiconductor layer structure and a method for producing a structure are provided, including a substrate made of semiconductor material, on which a layer made of a second semiconductor material is situated, furthermore a region (3) enriched with impurity atoms, which region is situated either in layer (2) or at a specific depth below the interface between layer (2) and substrate (1), additionally a layer (4) within the region (3) enriched with impurity atoms, which layer comprises cavities produced by ion implantation, furthermore at least one epitaxial layer (6) applied to layer (2) and also a defect region (5) comprising dislocations and stacking faults within the layer (4) comprising cavities, the at least one epitaxial layer (6) being largely crack-free, and a residual strain of the at least one epitaxial layer (6) being less than or equal to 1 GPa.

Abstract: A method is disclosed for treating a silicon carbide substrate for improved epitaxial deposition thereon and for use as a precursor in the manufacture of devices such as light emitting diodes. The method includes the steps of implanting dopant atoms of a first conductivity type into the first surface of a conductive silicon carbide wafer having the same conductivity type as the implanting ions at one or more predetermined dopant concentrations and implant energies to form a dopant profile, annealing the implanted wafer, and growing an epitaxial layer on the implanted first surface of the wafer.

Abstract: In sophisticated semiconductor devices, replacement gate approaches may be applied in combination with a process strategy for implementing a strain-inducing semiconductor material, wherein superior proximity of the strain-inducing semiconductor material and/or superior robustness of the replacement gate approach may be achieved by forming the initial gate electrode structures with superior uniformity and providing at least one cavity for implementing the strained channel regions in a very advanced manufacturing stage, i.e., after completing the basic transistor configuration.

Abstract: A lateral overflow drain and a channel stop are fabricated using a double mask process. Each lateral overflow drain is formed within a respective channel stop. Due to the use of two mask layers, one edge of each lateral overflow drain is aligned, or substantially aligned, with an edge of a respective channel stop.

Abstract: A semiconductor device includes an AlGaN layer that is provided on a SiC substrate and has an acceptor concentration equal to or higher than a donor concentration, a GaN layer provided on the AlGaN layer, and an electron supply layer that is provided on the GaN layer and has a band gap greater than that of GaN.

Abstract: A manufacturing method of a semiconductor device having an ohmic electrode is disclosed. The manufacturing method includes: forming a metal thin film on a rear surface of a semiconductor substrate; forming an ohmic electrode by laser annealing by irradiating the metal thin film with laser beam; and dicing the semiconductor substrate into chips by cutting at a dicing region of the semiconductor substrate. In forming the ohmic electrode, laser irradiation of the metal thin film is performed on a chip-by-chip basis while the dicing region is not being irradiated with the laser beam.

Abstract: A SiC semiconductor device capable of increasing a switching speed without destroying a gate insulating film. In addition, in a SiC-MOSFET including an n-type semiconductor substrate formed of SiC, a p-type semiconductor layer is entirely or partially provided on an upper surface of a p-type well layer that has a largest area of the transverse plane among a plurality of p-type well layers provided in an n-type drift layer and is arranged on an outermost periphery immediately below a gate electrode pad. It is preferable that a concentration of an impurity contained in the p-type semiconductor layer be larger than that of the p-type well layer.

Abstract: An insulated gate bipolar transistor (IGBT) includes a substrate having a first conductivity type, a drift layer having a second conductivity type opposite the first conductivity type, and a well region in the drift layer and having the first conductivity type. An epitaxial channel adjustment layer is on the drift layer and has the second conductivity type. An emitter region extends from a surface of the epitaxial channel adjustment layer through the epitaxial channel adjustment layer and into the well region. The emitter region has the second conductivity type and at least partially defines a channel region in the well region adjacent to the emitter region. A gate oxide layer is on the channel region, and a gate is on the gate oxide layer. Related methods are also disclosed.

Abstract: A memory device includes an array of memory cells and peripheral devices. At least some of the individual memory cells include carbonated portions that contain SiC. At least some of the peripheral devices do not include any carbonated portions. A transistor includes a first source/drain, a second source/drain, a channel including a carbonated portion of a semiconductive substrate that contains SiC between the first and second sources/drains and a gate operationally associated with opposing sides of the channel.