Preliminary Treatment Of Foundation Plate (epo) Patents (Class 257/E21.08)
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Patent number: 9640720Abstract: Provided is a surface light-emitting device comprising a substrate composed of an oriented polycrystalline zinc oxide sintered body in a plate shape, a light emitting functional layer provided on the substrate, and an electrode provided on the light emitting functional layer. According to the present invention, a surface light-emitting device having high luminous efficiency can be inexpensively provided.Type: GrantFiled: June 12, 2015Date of Patent: May 2, 2017Assignee: NGK Insulators, Ltd.Inventors: Morimichi Watanabe, Katsuhiro Imai, Jun Yoshikawa, Tsutomu Nanataki, Takashi Yoshino, Yukihisa Takeuchi
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Patent number: 8779548Abstract: Disclosed is an integrated circuit (IC) comprising a substrate (10) including a plurality of circuit elements and a metallization stack (20) covering said substrate for providing interconnections between the circuit elements, wherein the top metallization layer of said stack carries a plurality of metal portions (30) embedded in an exposed porous material (40) for retaining a liquid, said porous material laterally separating said plurality of metal portions. An electronic device comprising such an IC and a method of manufacturing such an IC are also disclosed.Type: GrantFiled: July 26, 2010Date of Patent: July 15, 2014Assignee: NXP, B.V.Inventors: Youri Victorovitch Ponomarev, Aurelie Humbert, Roel Daamen
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Patent number: 8293600Abstract: Memory devices and methods for manufacturing are described herein. A memory device as described herein includes a first electrode layer, a second electrode layer, and a thermal isolation structure including a layer of thermal isolation material between the first and second electrode layers. The first and second electrode layers and the thermal isolation structure define a multi-layer stack having a sidewall. A sidewall conductor layer including a sidewall conductor material is on the sidewall of the multi-layer stack. The sidewall conductor material has an electrical conductivity greater than that of the thermal isolation material. A memory element including memory material is on and in contact with the second electrode layer.Type: GrantFiled: December 6, 2011Date of Patent: October 23, 2012Assignee: Macronix International Co., Ltd.Inventor: Shih-Hung Chen
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Patent number: 7824955Abstract: A hybrid beam deposition (HBD) system and methods according to the present invention utilizes a unique combination of pulsed laser deposition (PLD) technique and equipment with equipment and techniques that provide a radical oxygen rf-plasma stream to effectively increase the flux density of available reactive oxygen at a deposition substrate for the effective synthesis of metal oxide thin films. The HBD system and methods of the present invention further integrate molecular beam epitaxy (MBE) and/or chemical vapor deposition (CVD) techniques and equipment in combination with the PLD equipment and technique and the radical oxygen rf-plasma stream to provide elemental source materials for the synthesis of undoped and/or doped metal oxide thin films as well as the synthesis of undoped and/or doped metal-based oxide alloy thin films.Type: GrantFiled: August 27, 2003Date of Patent: November 2, 2010Assignee: Moxtronics, Inc.Inventors: Henry W. White, Yungryel Ryu, Tae-seok Lee
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Patent number: 7371617Abstract: A semiconductor package with a heat sink and a method for fabricating the same are proposed. The heat sink is provided with a rigid and thermally resistant detach member on a top surface thereof, and is attached via its bottom surface to a chip mounted on a chip carrier. The detach member is sized larger than the heat sink and can be easily removed from the top surface of the heat sink. Subsequently, a molding process is performed to form an encapsulant for completely encapsulating the chip, the heat sink and the detach member. Then, a singulation process is performed to cut along predetermined cutting lines located between sides of the heat sink and corresponding sides of the detach member. Finally, the detach member and a portion of the encapsulant formed on the detach member are removed from the heat sink. The above fabrication method reduces the packaging cost.Type: GrantFiled: October 12, 2006Date of Patent: May 13, 2008Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Ho-Yi Tsai, Chien-Ping Huang
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Patent number: 7190016Abstract: Structures including a capacitor dielectric material disposed on the surface of an electrode suitable for use in forming capacitors are disclosed. Methods of forming such structures are also disclosed.Type: GrantFiled: October 5, 2005Date of Patent: March 13, 2007Assignee: Rohm and Haas Electronic Materials LLCInventors: John P. Cahalen, Maria Anna Rzeznik, John E. Schemenaur, Rajan Hariharan
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Patent number: 7164210Abstract: A semiconductor package with a heat sink and a method for fabricating the same are proposed. The heat sink is provided with a rigid and thermally resistant detach member on a top surface thereof, and is attached via its bottom surface to a chip mounted on a chip carrier. The detach member is sized larger than the heat sink and can be easily removed from the top surface of the heat sink. Subsequently, a molding process is performed to form an encapsulant for completely encapsulating the chip, the heat sink and the detach member. Then, a singulation process is performed to cut along predetermined cutting lines located between sides of the heat sink and corresponding sides of the detach member. Finally, the detach member and a portion of the encapsulant formed on the detach member are removed from the heat sink. The above fabrication method reduces the packaging cost.Type: GrantFiled: December 29, 2004Date of Patent: January 16, 2007Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Ho-Yi Tsai, Chien-Ping Huang