Preparation Of Substrate, Preliminary Treatment Oxidation Of Substrate, Reduction Treatment (epo) Patents (Class 257/E21.079)
  • Patent number: 11014127
    Abstract: A first material is filled during a semiconductor fabrication process in a space bound on at least one side by a fence formation created as a result of an etching operation. A solvent-removable material is deposited such that the solvent-removable material encapsulates at least that portion of the fence formation which is protruding from the structure such that a height of the fence formation exceeds a height of the structure. The portion of the fence formation which is protruding from the structure and a first portion of the solvent-removable material are removed by planarization. A second portion of the solvent-removable material is removed by dissolving in a solvent, the second portion remaining after removal by the planarization of the first portion of the solvent-removable material.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: May 25, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hariklia Deligianni, Bruce B. Doris, Eugene J. O'Sullivan, Naigang Wang
  • Patent number: 10639679
    Abstract: A first material is filled during a semiconductor fabrication process in a space bound on at least one side by a fence formation created as a result of an etching operation. A solvent-removable material is deposited such that the solvent-removable material encapsulates at least that portion of the fence formation which is protruding from the structure such that a height of the fence formation exceeds a height of the structure. The portion of the fence formation which is protruding from the structure and a first portion of the solvent-removable material are removed by planarization. A second portion of the solvent-removable material is removed by dissolving in a solvent, the second portion remaining after removal by the planarization of the first portion of the solvent-removable material.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: May 5, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hariklia Deligianni, Bruce B. Doris, Eugene J. O'Sullivan, Naigang Wang
  • Patent number: 8878275
    Abstract: In one general aspect, an apparatus can include a channel region disposed in a semiconductor substrate, a gate dielectric disposed on the channel region and a drift region disposed in the semiconductor substrate adjacent to the channel region. The apparatus can further include a field plate having an end portion disposed between a top surface of the semiconductor substrate and the gate dielectric The end portion can include a surface in contact with the gate dielectric, the surface having a first portion aligned along a first plane non-parallel to a second plane along which a second portion of the surface is aligned, the first plane being non-parallel to the top surface of the semiconductor substrate and the second plane being non-parallel to the top surface of the semiconductor substrate.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: November 4, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Sunglyong Kim, Mark Schmidt, Christopher Nassar, Steven Leibiger
  • Patent number: 8716149
    Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having a gate structure. An atomic layer deposition (ALD) process is performed to deposit a spacer around the gate structure. The ALD process includes alternating flowing ionized radicals of a first precursor across the semiconductor substrate and flowing a chlorosilane precursor across the semiconductor substrate to deposit the spacer.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: May 6, 2014
    Assignee: GlobalFoundries, Inc.
    Inventors: Fabian Koehler, Sergej Mutas, Dina Triyoso, Itasham Hussain
  • Patent number: 8643155
    Abstract: A chip on film (COF) is disclosed in the present disclosure, which comprises an adhesive base layer, a driving integrated circuit (IC), an adhesive layer and a copper layer. The driving IC is embedded on a surface of the adhesive base layer; the adhesive layer is located under the adhesive base layer; the copper layer is located under the adhesive layer. The adhesive base layer is formed with a heat and pressure spreading structure. A heat and pressure spreading structure is disposed on the adhesive base layer of the COF so that deformation or unevenness of the glass substrate in the bonded area can be avoided when the COF is thermally pressed to the glass substrate of the LCD. These guarantees the consistency between the bonded area and the unbounded area, the bonded area and the unbounded area of the glass substrate will have the same transmissivity and luminance.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: February 4, 2014
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd.
    Inventors: Liang-Chan Liao, Po-Shen Lin, Yu Wu
  • Patent number: 8501636
    Abstract: A method for fabricating silicon dioxide layer is disclosed. The method includes the following steps. Firstly, a semiconductor substrate is provided. Next, the semiconductor substrate is cleaned with a solution containing hydrogen peroxide to form a chemical oxide layer on the semiconductor substrate. Then, the chemical oxide layer is heated in no oxygen atmosphere, such that the chemical oxide layer forms a compact layer. Then, the semiconductor substrate is heated in oxygen atmosphere to form a silicon dioxide layer between the semiconductor substrate and the compact layer.
    Type: Grant
    Filed: July 24, 2012
    Date of Patent: August 6, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Shao-Wei Wang, Yu-Ren Wang, Chien-Liang Lin, Ying-Wei Yen, Kun-Yuan Lo, Chih-Wei Yang
  • Patent number: 8378471
    Abstract: Various semiconductor chip packages and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a solder bump to a side of a semiconductor chip and bringing the solder bump into contact with a conductor pad coupled to a substrate and positioned in an opening of a solder mask on the substrate. The conductor pad has a first lateral dimension and the opening has a second lateral dimension that is larger than the first lateral dimension. A metallurgical bond is established between the solder bump and the conductor pad.
    Type: Grant
    Filed: January 22, 2010
    Date of Patent: February 19, 2013
    Assignee: ATI Technologies ULC
    Inventors: Roden R. Topacio, Vincent Chan, Fan Yeung
  • Patent number: 8163626
    Abstract: Embodiments described herein generally relate to flash memory devices and methods for manufacturing flash memory devices. In one embodiment, a method for selective removal of nitrogen from the nitrided areas of a substrate is provided. The method comprises positioning a substrate comprising a material layer disposed adjacent to an oxide containing layer in a processing chamber, exposing the substrate to a nitridation process to incorporate nitrogen onto the material layer and the exposed areas of the oxide containing layer, and exposing the nitrided material layer and the nitrided areas of the oxide containing layer to a gas mixture comprising a quantity of a hydrogen containing gas and a quantity of an oxygen containing gas to selectively remove nitrogen from the nitrided areas of the oxide containing layer relative to the nitrided material layer using a radical oxidation process.
    Type: Grant
    Filed: June 15, 2010
    Date of Patent: April 24, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Johanes Swenburg, David Chu, Theresa Kramer Guarini, Yonah Cho, Udayan Ganguly, Lucien Date
  • Patent number: 8158487
    Abstract: The invention relates to a process for annealing a structure that includes at least one wafer, with the annealing process including conducting a first annealing of the structure in an oxidizing atmosphere while holding the structure in contact with a holder in a first position in order to oxidize at least portion of the exposed surface of the structure, shifting the structure on the holder into a second position in which non-oxidized regions of the structure are exposed, and conducting a second annealing of the structure in an oxidizing atmosphere while holding the structure in the second position. The process provides an oxide layer on the structure.
    Type: Grant
    Filed: January 21, 2011
    Date of Patent: April 17, 2012
    Assignee: Soitec
    Inventors: Nicolas Sousbie, Bernard Aspar, Thierry Barge, Chrystelle Lagahe Blanchard
  • Patent number: 8119444
    Abstract: An image sensor and a method of manufacturing an image sensor. An image sensor may include a semiconductor substrate which may include a readout circuitry. An image sensor may include an interlayer dielectric over a semiconductor substrate, and/or a first metal pattern over an interlayer dielectric. An interconnection may penetrate an interlayer dielectric and/or may be connected to a readout circuitry. A first metal pattern may be formed over an interlayer dielectric, and/or may be connected to an interconnection. A second metal pattern may be formed over a first metal pattern. A photodiode pattern may be formed over a second metal pattern.
    Type: Grant
    Filed: December 8, 2009
    Date of Patent: February 21, 2012
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Min-Hyung Lee
  • Patent number: 8110503
    Abstract: Various processes and related systems are provided for making structures on substrate surfaces. Disclosed are methods of making a structure supported by a substrate by providing a substrate having a receiving surface and exposing at least a portion of the receiving surface to output from a remote plasma of an inert gas. The remote plasma has an energy low enough to substantially avoid etching or sputtering of the receiving surface but sufficient to generate a treated receiving surface. The treated surface is contacted with a deposition gas, thereby making the structure supported by the substrate.
    Type: Grant
    Filed: April 26, 2011
    Date of Patent: February 7, 2012
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: Navneet Kumar, Angel Yanguas-Gil, Gregory S. Girolami, John R. Abelson
  • Patent number: 8043981
    Abstract: Methods and apparatus for forming an oxide layer on a semiconductor substrate are disclosed. A two frequency plasma source is used to form a plasma in a plasma reactor. In various embodiments, different quantities of power are supplied to a power source operating at the first frequency and a power source operating at the second frequency over time.
    Type: Grant
    Filed: April 19, 2010
    Date of Patent: October 25, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Kai Ma, Yoshitaka Yokota, Christopher S. Olsen
  • Patent number: 8011319
    Abstract: A holding device is presented in which a layer which is to be oxidized is processed, in a single-substrate process. The process temperature during the processing is recorded directly at the substrate or at a holding device for the substrate. The process includes introducing a substrate, which bears a layer to be oxidized uncovered in an edge region in a layer stack, into a heating device, passing an oxidation gas onto the substrate, heating the substrate to a process temperature, which is recorded during the processing via a temperature of the holding device which holds the substrate, and controlling the substrate temperature to a desired temperature or temperature curve during the processing.
    Type: Grant
    Filed: October 5, 2009
    Date of Patent: September 6, 2011
    Assignee: Infineon Technologies AG
    Inventors: Hin-Yiu Chung, Thomas Gutt
  • Patent number: 8004027
    Abstract: Provided is an image sensor. The image sensor comprises an interlayer dielectric, lines, and a crystalline semiconductor layer including photodiodes and a device isolation region. The interlayer dielectric can be formed on a first substrate comprising a readout circuitry. The lines pass through the interlayer dielectric to connect with the readout circuitry, and each line is formed according to unit pixel. The crystalline semiconductor layer can be bonded on the interlayer dielectric including the lines. The photodiodes, formed inside the crystalline semiconductor layer, are electrically connected with the lines. The device isolation region comprises conductive impurities and is formed inside the crystalline semiconductor layer so that the photodiodes can be separated according to unit pixels.
    Type: Grant
    Filed: September 5, 2008
    Date of Patent: August 23, 2011
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Joon Hwang
  • Patent number: 7972933
    Abstract: Methods of forming semiconductor devices are provided herein. In some embodiments, a method of forming a semiconductor device may include providing a substrate having an oxide surface and a silicon surface; forming a nitrogen-containing layer on exposed portions of both the oxide and silicon surfaces; and oxidizing the nitrogen-containing layer to selectively remove the nitrogen-containing layer from atop the oxide surface. In some embodiments, an oxide layer is formed atop a remaining portion of the nitrogen-containing layer formed on the silicon feature. In some embodiments, the oxide surface is an exposed surface of a shallow trench isolate region (STI) disposed adjacent to one or more floating gates of a semiconductor device. In some embodiments, the silicon surface is an exposed surface of a silicon or polysilicon floating gate of a semiconductor device.
    Type: Grant
    Filed: March 29, 2010
    Date of Patent: July 5, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Christopher S. Olsen, Johanes Swenberg, Udayan Ganguly, Theresa Kramer Guarini, Yonah Cho
  • Patent number: 7927914
    Abstract: The invention provides a manufacturing method for a semiconductor photoelectrochemical cell, comprising the steps of burning a base made of titanium or a titanium alloy in an atmosphere of 700° C. to 1000° C. at a rate of temperature increase of no lower than 5° C./second so that a titanium oxide layer is formed on the surface, and thus, mixing titanium metal into said titanium oxide layer.
    Type: Grant
    Filed: August 9, 2006
    Date of Patent: April 19, 2011
    Assignee: Shiken Co., Ltd.
    Inventors: Yoshinori Nakagawa, Kiyohisa Wada
  • Patent number: 7910495
    Abstract: A plasma oxidizing method includes a step of placing an object to be processed and having a surface containing silicon on a susceptor disposed in a processing vessel of a plasma processing apparatus, a step of producing a plasma from a processing gas containing oxygen in the processing vessel, a step of supplying high-frequency electric power to the susceptor and applying a high-frequency bias to the object to be processed when the plasma is produced, and a step of forming a silicon oxide film by oxidizing silicon in the surface of the object to be processed by the plasma.
    Type: Grant
    Filed: September 27, 2007
    Date of Patent: March 22, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Toshihiko Shiozawa, Yoshiro Kabe, Takashi Kobayashi, Hikaru Adachi, Junichi Kitagawa, Nobuhiko Yamamoto
  • Patent number: 7838400
    Abstract: A method of manufacturing a solar cell is provided. One surface of a semiconductor substrate is doped with a n-type dopant. The substrate is then subjected to a thermal oxidation process to form an oxide layer on one or both surfaces of the substrate. The thermal process also diffuses the dopant into the substrate, smoothing the concentration profile. The smoothed concentration gradient enables the oxide layer to act as a passivating layer. Anti-reflective coatings may be applied over the oxide layers, and a reflective layer may be applied on the surface opposite the doped surface to complete the solar cell.
    Type: Grant
    Filed: July 17, 2008
    Date of Patent: November 23, 2010
    Assignee: Applied Materials, Inc.
    Inventor: Peter Borden
  • Patent number: 7838443
    Abstract: The invention concerns a method for minimizing “corner” effects in shallow silicon oxide trenches, by densifying the silicon oxide layer after it has been deposited in the trenches. Said densification is preferably carried out by irradiating the layer under luminous radiation with weak wavelength.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: November 23, 2010
    Inventors: Patrick Schiavone, Frédéric Gaillard
  • Patent number: 7696091
    Abstract: A method of manufacturing a silicon layer includes pretreating a surface of a silicon nitride layer formed on a substrate through a plasma enhanced chemical vapor deposition method using a first reaction gas including at least one of silicone tetrafluoride (SiF4) gas, a nitrogen trifluoride (NF3) gas, SiF4—H2 gas and a mixture thereof. Then, a silicon layer is formed on the pretreated silicon nitride layer through the plasma enhanced chemical vapor deposition method using a second reaction gas including a mixture of gas including silicon tetrafluoride (SiF4), hydrogen (H2) and argon (Ar).
    Type: Grant
    Filed: February 16, 2007
    Date of Patent: April 13, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kunal Girotra, Byoung-June Kim, Sung-Hoon Yang
  • Patent number: 7670939
    Abstract: Various semiconductor chip packages and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a solder bump to a side of a semiconductor chip and bringing the solder bump into contact with a conductor pad coupled to a substrate and positioned in an opening of a solder mask on the substrate. The conductor pad has a first lateral dimension and the opening has a second lateral dimension that is larger than the first lateral dimension. A metallurgical bond is established between the solder bump and the conductor pad.
    Type: Grant
    Filed: May 12, 2008
    Date of Patent: March 2, 2010
    Assignee: ATI Technologies ULC
    Inventors: Roden R. Topacio, Vincent Chan, Fan Yeung
  • Patent number: 7615499
    Abstract: A method is presented in which a layer which is to be oxidized is processed, in a single-substrate process. The process temperature during the processing is recorded directly at the substrate or at a holding device for the substrate. The method includes introducing a substrate, which bears a layer to be oxidized uncovered in an edge region in a layer stack, into a heating device, passing an oxidation gas onto the substrate, heating the substrate to a process temperature, which is recorded during the processing via a temperature of a holding device which holds the substrate, and controlling the substrate temperature to a desired temperature or temperature curve during the processing.
    Type: Grant
    Filed: July 26, 2003
    Date of Patent: November 10, 2009
    Assignee: Infineon Technologies AG
    Inventors: Hin-Yiu Chung, Thomas Gutt
  • Patent number: 7482262
    Abstract: Disclosed are embodiments relating to a method of manufacturing a semiconductor device that may improve the yield rate of the semiconductor device. In embodiments, the method may include preparing a substrate including a plurality of conductive patterns, forming first and second insulating layers on the substrate, forming a plurality of via holes by selectively etching the first and second insulating layers, forming a plurality of trenches by selectively etching the second insulating layer in such a manner that the trenches are communicated with the trenches, and forming metal interconnections in the via holes and the trenches. The width ratio of the trench to the insulating layer positioned between adjacent trenches may be in a range of 0.45 to 0.55.
    Type: Grant
    Filed: November 14, 2006
    Date of Patent: January 27, 2009
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Ji Ho Hong
  • Publication number: 20080197350
    Abstract: A thin film transistor (TFT) may include a channel layer, a source electrode, a drain electrode, a protective layer, a gate electrode, and/or a gate insulating layer. The channel layer may include an oxide semiconductor material. The source electrode and the drain electrode may face each other on the channel layer. The protective layer may be under the source electrode and the drain electrode and/or may cover the channel layer. The gate electrode may be configured to apply an electric field to the channel layer. The gate insulating layer may be interposed between the gate electrode and the channel layer.
    Type: Application
    Filed: December 27, 2007
    Publication date: August 21, 2008
    Inventors: Jae-chul Park, Young-soo Park, Sun-Il Kim
  • Patent number: 7381631
    Abstract: This invention relates to a method of fabricating nano-dimensional structures, comprising: depositing at least one deformable material upon a substrate such that the material includes at least one portion; and creating an oxidizable layer located substantially adjacent to the deposited deformable material such that at least a portion of the oxidized portion of the oxidizable layer interacts with the at least one portion of the deformable material to apply a localized pressure upon the at least one portion of the deformable material.
    Type: Grant
    Filed: July 5, 2005
    Date of Patent: June 3, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Peter Mardilovich, Pavel Kornilovich, Randy Hoffman
  • Patent number: 7259112
    Abstract: The invention concerns a method for minimizing “corner” effects in shallow silicon oxide trenches, by densifying the silicon oxide layer after it has been deposited in the trenches. Said densification is preferably carried out by irradiating the layer under luminous radiation with weak wavelength.
    Type: Grant
    Filed: July 8, 1998
    Date of Patent: August 21, 2007
    Assignee: Fahrenheit Thermoscope, LLC
    Inventors: Patrick Schiavone, Frédéric Gaillard
  • Patent number: 7141513
    Abstract: After ion implantation, thermal ashing is performed using ozone at a pressure of between about 0.01 to about 1000 Torr at below 1000° C. to remove the resist. Since the process includes a substantial amount of ozone, the resist can be completely oxidized, thus leaving no residue or other contaminates to remain on the substrate. Using ozone allows fast resist removal with minimal residue at low temperatures.
    Type: Grant
    Filed: October 21, 2004
    Date of Patent: November 28, 2006
    Assignee: WaferMasters, Inc.
    Inventor: Woo Sik Yoo
  • Patent number: 7129185
    Abstract: A substrate processing method includes the steps of removing carbon from a surface of a silicon substrate by irradiating an ultraviolet light on the surface in an essentially ultraviolet nonreactive gas atmosphere and forming an oxide film or an oxynitride film on the surface of the silicon substrate by irradiating an ultraviolet light thereon in an essentially ultraviolet reactive gas atmosphere. Further, a computer readable storage medium stores therein a program for controlling the substrate processing method.
    Type: Grant
    Filed: October 19, 2004
    Date of Patent: October 31, 2006
    Assignee: Tokyo Electron Limited
    Inventors: Shintaro Aoyama, Masanobu Igeta, Hiroshi Shinriki
  • Patent number: 7122488
    Abstract: Methods are provided for forming silicon dioxide (SiO2) on a silicon carbide (SiC) substrate. The method comprises: providing a SiC substrate; supplying an atmosphere including oxygen; performing a high-density (HD) plasma-based process; and, forming a SiO2 layer overlying the SiC substrate. Typically, performing the HD plasma-based process includes connecting a top electrode to an inductively coupled HD plasma source. In one aspect, SiO2 is grown on the SiC substrate. Then, an HD plasma oxidation process is performed that creates a reactive oxygen species and breaks the Si—C bonds in the SiC substrate, to form free Si and C atoms in the SiC substrate. The free Si atoms in the SiC substrate are bonded to the HD plasma-generated reactive oxygen species, and the SiO2 layer is grown.
    Type: Grant
    Filed: March 29, 2004
    Date of Patent: October 17, 2006
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Pooran Chandra Joshi, Apostolos T. Voutsas, John W. Hartzell