Multistep Processes For Manufacture Of Device Using Quantum Interference Effect, E.g., Electrostatic Aharonov-bohm Effect (epo) Patents (Class 257/E21.089)
  • Patent number: 8674339
    Abstract: Light-emitting devices (LED) and methods of manufacturing the same.
    Type: Grant
    Filed: November 17, 2010
    Date of Patent: March 18, 2014
    Assignee: Samsung Electronics Co., Ltd
    Inventor: Taek Kim
  • Patent number: 8551868
    Abstract: A method of fabricating quantum confinements is provided. The method includes depositing, using a deposition apparatus, a material layer on a substrate, where the depositing includes irradiating the layer, before a cycle, during a cycle, and/or after a cycle of the deposition to alter nucleation of quantum confinements in the material layer to control a size and/or a shape of the quantum confinements. The quantum confinements can include quantum wells, nanowires, or quantum dots. The irradiation can be in-situ or ex-situ with respect to the deposition apparatus. The irradiation can include irradiation by photons, electrons, or ions. The deposition is can include atomic layer deposition, chemical vapor deposition, MOCVD, molecular beam epitaxy, evaporation, sputtering, or pulsed-laser deposition.
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: October 8, 2013
    Assignees: The Board of Trustees of the Leland Stanford Junior Universit, Honda Patents & Technologies North America, LLC
    Inventors: Timothy P. Holme, Andrei Iancu, Hee Joon Jung, Michael C Langston, Munekazu Motoyama, Friedrich B. Prinz, Takane Usui, Hitoshi Iwadate, Neil Dasgupta, Cheng-Chieh Chao
  • Patent number: 8455279
    Abstract: Methods for manufacturing a polarization pinned vertical cavity surface emitting laser (VCSEL). Steps include growing a lower mirror on a substrate; growing an active region on the lower mirror; growing an upper mirror on the active region; depositing a grating layer on the upper mirror; and etching a grating into the grating layer.
    Type: Grant
    Filed: August 15, 2011
    Date of Patent: June 4, 2013
    Assignee: Finisar Corporation
    Inventors: Ralph H. Johnson, James K. Guenter
  • Patent number: 8426897
    Abstract: An improved semiconductor apparatus that comprises an elongated structure that extends into the substrate. The apparatus comprises a collection contact, a resistive path, a bias connection that creates along the length of the elongated structure, an electric field component that drives signal charge carriers in a direction perpendicular to the elongated structure, and a second bias that generates a current flow that creates within the substrate a constant electric field component to drive signal charge carriers towards the collection contact on the first surface.
    Type: Grant
    Filed: December 1, 2006
    Date of Patent: April 23, 2013
    Inventor: Artto Aurola
  • Patent number: 8399876
    Abstract: A semiconductor die includes at least one first region and at least one second region. The at least one first region is configured to emit light having at least a first wavelength. The at least one second region is configured to emit light having at least a second wavelength, which is different from the first wavelength.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: March 19, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Taek Kim
  • Publication number: 20130056705
    Abstract: A method of manufacturing a quantum dot layer, and a quantum dot optoelectronic device including the quantum dot layer. The method includes sequentially stacking a self-assembled monolayer, a sacrificial layer, and a quantum dot layer on a source substrate; disposing a stamp on the quantum dot layer; picking up the sacrificial layer, the quantum dot layer and the stamp; and removing the sacrificial layer from the quantum dot layer using a solution that dissolves the sacrificial layer.
    Type: Application
    Filed: May 29, 2012
    Publication date: March 7, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tae-ho KIM, Kyung-sang CHO, Dae-young CHUNG, Byoung-lyong CHOI
  • Publication number: 20120322184
    Abstract: Methods for improving the temperature performance of alInGaP based light emitters. Nitrogen is added to the quantum wells in small quantities. Nitrogen is added in a range of about 0.5 percent to 2 percent. The addition of nitrogen increases the conduction band offset and increases the separation of the indirect conduction band. To keep the emission wavelength in a particular range, the concentration of In in the quantum wells may be decreased or the concentration of Al in the quantum wells may be increased. Because the depth of the quantum wells in the valence band is more than is required although the addition of nitrogen reduces the depth of the quantum wells in the valence band. The net result is an increase in the conduction band offset and an increase in the separation of the indirect conduction band.
    Type: Application
    Filed: August 27, 2012
    Publication date: December 20, 2012
    Applicant: FINISAR CORPORATION
    Inventor: Ralph Herbert Johnson
  • Patent number: 8324120
    Abstract: An apparatus includes a substrate with a planar surface, a multilayer of semiconductor layers located on the planar surface, a plurality of electrodes located over the multilayer, and a dielectric layer located between the electrodes and the multilayer. The multilayer includes a 2D quantum well. A first set of the electrodes is located to substantially surround a lateral area of the 2D quantum well. A second set of the electrodes is controllable to vary a lateral width of a non-depleted channel between the substantially surrounded lateral area of the 2D quantum well and another area of the 2D quantum well. A third set of the electrodes is controllable to vary an area of a non-depleted portion of the lateral area.
    Type: Grant
    Filed: May 6, 2011
    Date of Patent: December 4, 2012
    Assignee: Alcatel Lucent
    Inventors: Kirk William Baldwin, Loren N. Pfeiffer, Kenneth William West, Robert L Willett
  • Publication number: 20120292590
    Abstract: An optical component comprising an emitter and a solid reflector, said reflector having a convex outer surface, said emitter being located within the solid reflector, the emitter being configured to emit radiation via an electric dipole transition, the dipole having a dipole axis being orientated at an angle of 45 degrees or less to the surface normal at the apex of the reflector.
    Type: Application
    Filed: May 18, 2012
    Publication date: November 22, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Anthony John BENNETT, Andrew James SHIELDS, Joanna Krystyna SKIBA-SZYMANSKA
  • Patent number: 8278186
    Abstract: The present invention relates to a wafer cleaning and a wafer bonding method using the same that can improve a yield of cleaning process and bonding property in bonding the cleaned wafer by cleaning the wafer using atmospheric pressure plasma and cleaning solution. The wafer cleaning method includes the steps of providing a process chamber with a wafer whose bonding surface faces upward, cleaning and surface-treating the bonding surface of the wafer by supplying atmospheric pressure plasma and a cleaning solution to the bonding surface of the wafer, and withdrawing out the wafer from the process chamber.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: October 2, 2012
    Assignee: Ltrin Co., Ltd.
    Inventors: Yong Won Cha, Dong Chul Kim
  • Publication number: 20120241723
    Abstract: An optoelectronic device includes a first electrode, a quantum dot layer disposed on the first electrode including a plurality of quantum dots, a fullerene layer disposed directly on the quantum dot layer wherein the quantum dot layer and the fullerene layer form an electronic heterojunction, and a second electrode disposed on the fullerene layer. The device may include an electron blocking layer. The quantum dot layer may be modified by a chemical treatment to exhibit in creased charge carrier mobility.
    Type: Application
    Filed: September 29, 2010
    Publication date: September 27, 2012
    Applicant: RESEARCH TRIANGLE INSTITUTE, INTERNATIONAL
    Inventors: Ethan Klem, John Lewis
  • Publication number: 20110291069
    Abstract: Light-emitting devices (LED) and methods of manufacturing the same.
    Type: Application
    Filed: November 17, 2010
    Publication date: December 1, 2011
    Applicant: Samsung Electronics Co., Ltd.
    Inventor: Taek Kim
  • Publication number: 20110269298
    Abstract: A method of fabricating quantum confinements is provided. The method includes depositing, using a deposition apparatus, a material layer on a substrate, where the depositing includes irradiating the layer, before a cycle, during a cycle, and/or after a cycle of the deposition to alter nucleation of quantum confinements in the material layer to control a size and/or a shape of the quantum confinements. The quantum confinements can include quantum wells, nanowires, or quantum dots. The irradiation can be in-situ or ex-situ with respect to the deposition apparatus. The irradiation can include irradiation by photons, electrons, or ions. The deposition is can include atomic layer deposition, chemical vapor deposition, MOCVD, molecular beam epitaxy, evaporation, sputtering, or pulsed-laser deposition.
    Type: Application
    Filed: March 24, 2011
    Publication date: November 3, 2011
    Inventors: Timothy P. Holme, Andrei Iancu, Hee Joon Jung, Michael C Langston, Munekazu Motoyama, Friedrich B. Prinz, Takane Usui, Hitoshi Iwadate, Neil Dasgupta, Cheng-Chieh Chao
  • Publication number: 20110215289
    Abstract: A reconfigurable device and a method of creating, erasing, or reconfiguring the device are provided. At an interface between a first insulating layer and a second insulating layer, an electrically conductive, quasi one- or zero-dimensional electron gas is present such that the interface presents an electrically conductive region that is non-volatile. The second insulating layer is of a thickness to allow metal-insulator transitions upon the application of a first external electric field. The electrically conductive region is subject to erasing upon application of a second external electric field.
    Type: Application
    Filed: May 13, 2011
    Publication date: September 8, 2011
    Inventor: Jeremy Levy
  • Publication number: 20110140084
    Abstract: An optical semiconductor device includes a substrate; and an active layer disposed on the substrate, wherein the active layer includes a first barrier layer containing GaAs, a quantum dot layer, which is disposed on the first barrier layer, which includes a quantum dot containing InAs, which includes a side barrier layer which covers at least a part of the quantum dot and a side surface of the quantum dot, and having an elongation strain inherent therein, and a second barrier layer disposed on the quantum dot layer.
    Type: Application
    Filed: December 10, 2010
    Publication date: June 16, 2011
    Applicant: FUJITSU LIMITED
    Inventor: Nobuaki HATORI
  • Publication number: 20110142088
    Abstract: The invention relates to a method for the production of a photon pair source, which generates entangled photon pairs, having at least one quantum dot, wherein in the method the operational behaviour of the photon pair source is determined by adjusting the fine structure splitting of the excitonic energy level of the at least one quantum dot. It is provided according to the invention for the fine structure splitting of the excitonic energy level to be adjusted by depositing the at least one quantum dot on a {111} crystal surface of a semiconductor substrate.
    Type: Application
    Filed: July 20, 2009
    Publication date: June 16, 2011
    Inventors: MOMME Winkelnkemper, Andrei Schliwa, Dieter Bimberg
  • Publication number: 20100295020
    Abstract: A nanowire product and process for fabricating it has a wafer with a buried oxide (BOX) upper layer in which a well is formed and the ends of a nanowire are on the BOX layer forming a beam that spans the well. A mask coating is formed on the upper surface of the BOX layer leaving an uncoated window over a center part of the beam and also forming a mask coating around the beam intermediate ends between each end of the beam center part and a side wall of the well. Applying oxygen through the window thins the beam center part while leaving the wire intermediate ends over the well thicker and having a generally arched shape. A thermal oxide coating can be placed on the wire and also the mask on the BOX layer before oxidation.
    Type: Application
    Filed: May 20, 2009
    Publication date: November 25, 2010
    Inventors: Tymon Barwicz, Lidija Sekaric, Jeffrey W. Sleight
  • Patent number: 7781754
    Abstract: The Bell-state analyzer includes a semiconductor device having quantum dots formed therein and adapted to support Fermions in a spin-up and/or spin-down states. Different Zeeman splittings in one or more of the quantum dots allows resonant quantum tunneling only for antiparallel spin states. This converts spin parity into charge information via a projective measurement. The measurement of spin parity allows for the determination of part of the states of the Fermions, which provides the states of the qubits, while keeping the undetermined part of the state coherent. The ability to know the parity of qubit states allows for logic operations to be performed on the qubits, i.e., allows for the formation of (two-qubit) quantum gates, which like classical logic gates, are the building blocks of a quantum computer. Quantum computers that perform a parity gate and a CNOT gate using the Bell-state analyzer of the invention are disclosed.
    Type: Grant
    Filed: July 9, 2007
    Date of Patent: August 24, 2010
    Assignee: MagiQ Technologies, Inc.
    Inventors: Daniel Loss, Hans-Andreas Engel
  • Patent number: 7585705
    Abstract: A method and device structure are disclosed for preventing gate oxide damage of a trench MOSFET during wafer processing while adding an ESD protection module atop the trench MOSFET. The ESD protection module has a low temperature oxide (LTO) bottom layer whose patterning process is found to cause the gate oxide damage. The method includes: a) Fabricate numerous trench MOSFETs on a wafer. b) Add a Si3N4 isolation layer, capable of preventing the LTO patterning process from damaging the gate oxide, atop the wafer. c) Add numerous ESD protection modules atop the Si3N4 isolation layer. d) Remove those portions of the Si3N4 isolation layer that are not beneath the ESD protection modules. In one embodiment, hydrofluoric acid is used as a first etchant for patterning the LTO while hot phosphoric acid is used as a second etchant for removing portions of the Si3N4 isolation layer.
    Type: Grant
    Filed: November 29, 2007
    Date of Patent: September 8, 2009
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Mengyu Pan, Zengyi He, Kaiyu Chen
  • Publication number: 20090159869
    Abstract: A semiconductor structure (10, 10?, 70, 80) includes a light emitter (12, 72) carried by a support structure (11). The light emitter (12, 72) includes a base region (24, 76) with a sloped sidewall (12a, 12b) and a light emitting region (25, 77) positioned thereon. The light emitting (25, 77) region includes a nitride semiconductor alloy having a composition that is different in a first region (26, 95) near the support structure (11) compared to a second region (27, 96) away from the support structure (11).
    Type: Application
    Filed: March 10, 2006
    Publication date: June 25, 2009
    Inventors: Fernando A. Ponce, Sridhar Srinivasan, Hiromasa Omiya
  • Publication number: 20090053845
    Abstract: A system and method for providing improved surface quality following removal of a substrate and template layers from a semiconductor structure provides an improved surface quality for a layer (such as a quantum well heterostructure active region) prior to bonding a heat sink/conductive substrate to the structure. Following the physical removal of a sapphire substrate, a sacrificial coating such as a spin-coat polymer photoresist is applied to an exposed GaN surface. This sacrificial coating provides a planar surface, generally parallel to the planes of the interfaces of the underlying layers. The sacrificial coating and etching conditions are selected such that the etch rate of the sacrificial coating approximately matches the etch rate of GaN and the underlying layers, so that the physical surface profile during etching approximates the physical surface profile of the sacrificial coating prior to etching.
    Type: Application
    Filed: November 5, 2008
    Publication date: February 26, 2009
    Applicant: PALO ALTO RESEARCH CENTER INCORPORATED
    Inventors: William S. Wong, Michael A. Kneissl, Mark Teepe
  • Patent number: 7482619
    Abstract: Provided are a charge trap memory device including a substrate and a gate structure including a charge trapping layer formed of a composite of nanoparticles, and a method of manufacturing the charge trap memory device.
    Type: Grant
    Filed: September 7, 2006
    Date of Patent: January 27, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwang-soo Seol, Shin-ae Jun, Eun-joo Jang, Jung-eun Lim, Kyung-sang Cho, Byung-ki Kim, Jae-ho Lee, Jae-young Choi
  • Publication number: 20080283892
    Abstract: A one cylinder storage device and a method for fabricating a capacitor are disclosed, realizing simplified fabrication by overexposure with a mask having a plurality of holes, in which the method includes forming a contact hole in an insulating layer on a semiconductor substrate; forming a conductive layer on the insulating layer to fill the contact hole; forming a photoresist layer on the conductive layer; forming a photoresist layer pattern by overexposure and generating a side lobe phenomenon; forming a cylindrical lower electrode by patterning the conductive layer using the photoresist layer pattern as a mask; and forming a dielectric layer and an upper electrode covering the lower electrode.
    Type: Application
    Filed: July 7, 2008
    Publication date: November 20, 2008
    Inventor: Jae Hyun KANG
  • Patent number: 7402486
    Abstract: A one cylinder storage device and a method for fabricating a capacitor are disclosed, realizing simplified fabrication by overexposure with a mask having a plurality of holes, in which the method includes forming a contact hole in an insulating layer on a semiconductor substrate; forming a conductive layer on the insulating layer to fill the contact hole; forming a photoresist layer on the conductive layer; forming a photoresist layer pattern by overexposure and generating a side lobe phenomenon; forming a cylindrical lower electrode by patterning the conductive layer using the photoresist layer pattern as a mask; and forming a dielectric layer and an upper electrode covering the lower electrode.
    Type: Grant
    Filed: December 29, 2005
    Date of Patent: July 22, 2008
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Jae Hyun Kang
  • Patent number: 7192841
    Abstract: A method of bonding two components by depositing an amorphous and non-hydrogenated intermediate layer (2) on one of the components (1,4) and arranging the components (1,4) in spaced relationship with the intermediate layer (2) therebetween. The method further comprises heating one or both of the components (1,4) before bringing the components (1,4) into contact. Finally, a voltage is applied to the components (1,4) to create a permanent bond between the two components.
    Type: Grant
    Filed: April 30, 2002
    Date of Patent: March 20, 2007
    Assignee: Agency for Science, Technology and Research
    Inventors: Jun Wei, Zhiping Wang, Hong Xie
  • Patent number: 7173272
    Abstract: A nondeterministic quantum CNOT gate (10) for photon qubits, with success probability 1/9, uses beamsplitters (B1–B5) with selected reflectivities to mix control and target input modes. It may be combined with an atomic quantum memory to construct a deterministic CNOT gate, with applications in quantum computing and as a Bell-state analyser.
    Type: Grant
    Filed: August 20, 2002
    Date of Patent: February 6, 2007
    Assignee: The University of Queensland
    Inventor: Timothy Cameron Ralph
  • Patent number: 7138285
    Abstract: A method of performing quantum well intermixing in a semiconductor device structure uses a sacrificial part of a cap layer, that is removed after QWI processing, to restore the cap surface to a condition in which high performance contacts are still possible.
    Type: Grant
    Filed: May 21, 2003
    Date of Patent: November 21, 2006
    Assignee: Intense Limited
    Inventors: Stephen Najda, Stewart Duncan McDougall, Xuefeng Liu