Device Having Semiconductor Body Comprising Group Iv Elements Or Group Iii-v Compounds With Or Without Impurities, E.g., Doping Materials (epo) Patents (Class 257/E21.085)

  • Patent number: 9780228
    Abstract: Provided are an oxide semiconductor device and a method for manufacturing same, wherein the oxide semiconductor device according to an embodiment of the inventive concept includes a substrate, and an oxide semiconductor layer on the substrate having different concentration of oxygen vacancy in the thickness direction.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: October 3, 2017
    Assignee: Industry-Academic Cooperation Foundation, Yonsei University
    Inventors: Hyun Jae Kim, Yeong-gyu Kim, Ji Hoon Park, Seokhyun Yoon, Seonghwan Hong
  • Patent number: 9343525
    Abstract: A substrate includes aluminum nitride, wherein the aluminum nitride substrate has on at least a surface thereof an aluminum nitride single-crystal layer having as a principal plane a plane that is inclined 0.05° to 0.40° in the m-axis direction from the (0001) plane of a wurzite structure.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: May 17, 2016
    Assignee: Tokuyama Corporation
    Inventors: Keiichiro Hironaka, Toru Kinoshita
  • Patent number: 9018050
    Abstract: A rolled-up transmission line structure for a radiofrequency integrated circuit (RFIC) comprises a multilayer sheet in a rolled configuration comprising multiple turns about a longitudinal axis, where the multilayer sheet comprises a conductive pattern layer on a strain-relieved layer. The conductive pattern layer comprises a first conductive film and a second conductive film separated from the first conductive film in a rolling direction. In the rolled configuration, the first conductive film surrounds the longitudinal axis, and the second conductive film surrounds the first conductive film. The first conductive film serves as a signal line and the second conductive film serves as a conductive shield for the rolled-up transmission line structure.
    Type: Grant
    Filed: October 10, 2013
    Date of Patent: April 28, 2015
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: Xiuling Li, Wen Huang
  • Patent number: 8993447
    Abstract: An apparatus includes a wafer with a number of openings therein. For each opening, an LED device is coupled to a conductive carrier and the wafer in a manner so that each of the coupled LED device and a portion of the conductive carrier at least partially fill the opening. A method of fabricating an LED device includes forming a number of openings in a wafer. The method also includes coupling light-emitting diode (LED) devices to conductive carriers. The LED devices with conductive carriers at least partially fill each of the openings.
    Type: Grant
    Filed: April 8, 2013
    Date of Patent: March 31, 2015
    Assignee: TSMC Solid State Lighting Ltd.
    Inventors: Hsing-Kuo Hsia, Chih-Kuang Yu, Hung-Yi Kuo, Chyi Shyuan Chern
  • Patent number: 8980689
    Abstract: Provided is a method of fabricating a multi-chip stack package. The method includes preparing single-bodied lower chips having a single-bodied lower chip substrate having a first surface and a second surface disposed opposite the first surface, bonding unit package substrates onto the first surface of the single-bodied lower chip substrate to form a single-bodied substrate-chip bonding structure, separating the single-bodied substrate-chip bonding structure into a plurality of unit substrate-chip bonding structures, preparing single-bodied upper chips having a single-bodied upper chip substrate, bonding the plurality of unit substrate-chip bonding structures onto a first surface of the single-bodied upper chip substrate to form a single-bodied semiconductor chip stack structure, and separating the single-bodied semiconductor chip stack structure into a plurality of unit semiconductor chip stack structures.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: March 17, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byoung-Soo Kwak, Cha-Jea Jo, Tae-Je Cho, Sang-Uk Han
  • Patent number: 8956890
    Abstract: The present invention provides a method for producing a Group III nitride semiconductor light-emitting device wherein a p-cladding layer has a uniform Mg concentration. A p-cladding layer having a superlattice structure in which AlGaN and InGaN are alternately and repeatedly deposited is formed in two stages of the former process and the latter process where the supply amount of the Mg dopant gas is different. The supply amount of the Mg dopant gas in the latter process is half or less than that in the former process. The thickness of a first p-cladding layer formed in the former process is 60% or less than that of the p-cladding layer, and 160 ? or less.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: February 17, 2015
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Atsushi Miyazaki, Koji Okuno
  • Patent number: 8946894
    Abstract: Methods and apparatuses for forming a package for high-power semiconductor devices are disclosed herein. A package may include a plurality of distinct thermal spreader layers disposed between a die and a metal carrier. Other embodiments are described and claimed.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: February 3, 2015
    Assignee: TriQuint Semiconductor, Inc.
    Inventors: Tarak A. Railkar, Deep C. Dumka
  • Patent number: 8940647
    Abstract: Embodiments of the present invention provide a method for surface treatment on a metal oxide and a method for preparing a thin film transistor. The method for surface treatment on a metal oxide comprises: utilizing plasma to perform a surface treatment on a device to be processed; the plasma comprises a mixture gas of an F-based gas and O2, and the device to be processed is a metal oxide or a manufactured article coated with a metal oxide. The embodiments provided by the present invention can reduce the contact resistance between a metal oxide and other electrodes, and improve the effect of ohmic contact of the metal oxide.
    Type: Grant
    Filed: August 22, 2012
    Date of Patent: January 27, 2015
    Assignee: Boe Technology Group Co., Ltd.
    Inventors: Xiaodi Liu, Jun Cheng
  • Patent number: 8937020
    Abstract: One object is to provide a deposition technique for forming an oxide semiconductor film. By forming an oxide semiconductor film using a sputtering target including a sintered body of a metal oxide whose concentration of hydrogen contained is low, for example, lower than 1×1016 atoms/cm3, the oxide semiconductor film contains a small amount of impurities such as a compound containing hydrogen typified by H2O or a hydrogen atom. In addition, this oxide semiconductor film is used as an active layer of a transistor.
    Type: Grant
    Filed: June 20, 2013
    Date of Patent: January 20, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toru Takayama, Keiji Sato
  • Patent number: 8921174
    Abstract: Disclosed herein is a method for fabricating a complementary tunneling field effect transistor based on a standard CMOS IC process, which belongs to the field of logic devices and circuits of field effect transistors in ultra large scaled integrated (ULSI) circuits. In the method, an intrinsic channel and body region of a TFET are formed by means of complementary P-well and N-well masks in the standard CMOS IC process to form a well doping, a channel doping and a threshold adjustment by implantation. Further, a bipolar effect in the TFET can be inhibited via a distance between a gate and a drain on a layout so that a complementary TFET is formed. In the method according to the invention, the complementary tunneling field effect transistor (TFET) can be fabricated by virtue of existing processes in the standard CMOS IC process without any additional masks and process steps.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: December 30, 2014
    Assignee: Peking University
    Inventors: Ru Huang, Qianqian Huang, Zhan Zhan, Yingxin Qiu, Yangyuan Wang
  • Patent number: 8921213
    Abstract: An object of the present invention is to amplify the current which varies by a factor of several orders of magnitude with a constant gain without using a complicated circuit. In order to solve the problem, with a semiconductor device includes a first semiconductor region of a first conductivity, a second semiconductor region which is an opposite conductivity opposite to the first conductivity and is in contact with the first semiconductor region and a third semiconductor region which is the first conductivity and is in contact with the second semiconductor region at the second surface, a fourth semiconductor region in contact with the second semiconductor region is provided so as to be separated from the third semiconductor region and enclose the third semiconductor region and an impurity concentration of the fourth semiconductor region is larger than that of the second semiconductor region.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: December 30, 2014
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Yutaka Hayashi, Yasushi Nagamune, Toshitaka Ota
  • Patent number: 8907390
    Abstract: Disclosed herein is a thermally-assisted magnetic tunnel junction structure including a thermal barrier. The thermal barrier is composed of a cermet material in a disordered form such that the thermal barrier has a low thermal conductivity and a high electric conductivity. Compared to conventional magnetic tunnel junction structures, the disclosed structure can be switched faster and has improved compatibility with standard semiconductor fabrication processes.
    Type: Grant
    Filed: November 11, 2010
    Date of Patent: December 9, 2014
    Assignee: Crocus Technology Inc.
    Inventor: Jason Reid
  • Patent number: 8877573
    Abstract: A thin film transistor substrate and a method for manufacturing the same are discussed, in which the thin film transistor comprises a gate line and a data line arranged on a substrate to cross each other; a gate electrode connected with the gate line below the gate line; an active layer formed on the gate electrode; an etch stopper formed on the active layer; an ohmic contact layer formed on the etch stopper; source and drain electrodes formed on the ohmic contact layer; and a pixel electrode connected with the drain electrode. It is possible to prevent a crack from occurring in the gate insulating film during irradiation of the laser and prevent resistance of the gate electrode from being increased.
    Type: Grant
    Filed: October 7, 2013
    Date of Patent: November 4, 2014
    Assignee: LG Display Co., Ltd.
    Inventor: KiTae Kim
  • Patent number: 8866199
    Abstract: An object of the present invention is to provide a group III-V compound semiconductor photo detector comprising an absorption layer having a group III-V compound semiconductor layer containing Sb as a group V constituent element, and an n-type InP window layer, resulting in reduced dark current. The InP layer 23 grown on the absorption layer 23 contains antimony as impurity, due to the memory effect with antimony which is supplied during the growth of a GaAsSb layer of the absorption layer 21. In the group III-V compound semiconductor photo detector 11, the InP layer 23 contains antimony as impurity and is doped with silicon as n-type dopant. Although antimony impurities in the InP layer 23 generate holes, the silicon contained in the InP layer 23 compensates for the generated carriers. As a result, the second portion 23d of the InP layer 23 has sufficient n-type conductivity.
    Type: Grant
    Filed: July 21, 2010
    Date of Patent: October 21, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Katsushi Akita, Takashi Ishizuka, Kei Fujii, Youichi Nagai
  • Patent number: 8847367
    Abstract: Provided are a hole-injecting material for an organic electroluminescent device (organic EL device) exhibiting high luminous efficiency at a low voltage and having greatly improved driving stability, and an organic EL device using the material. The hole-injecting material for an organic EL device is selected from benzenehexacarboxylic acid anhydrides, benzenehexacarboxylic acid imides, or N-substituted benzenehexacarboxylic acid imides. Further, the organic EL device has at least one light-emitting layer and at least one hole-injecting layer between an anode and a cathode arranged opposite to each other, and includes the above-mentioned hole-injecting material for an organic EL device in the hole-injecting layer. The organic EL device may contain a hole-transporting material having an ionization potential (IP) of 6.0 eV or less in the hole-injecting layer or a layer adjacent to the hole-injecting layer.
    Type: Grant
    Filed: February 27, 2009
    Date of Patent: September 30, 2014
    Assignee: Nippon Steel & Sumikin Chemical Co., Ltd.
    Inventors: Takayuki Fukumatsu, Ikumi Ichihashi, Hiroshi Miyazaki, Atsushi Oda
  • Patent number: 8809132
    Abstract: A capping layer may be deposited over the active channel of a thin film transistor (TFT) in order to protect the active channel from contamination. The capping layer may affect the performance of the TFT. If the capping layer contains too much hydrogen, nitrogen, or oxygen, the threshold voltage, sub threshold slope, and mobility of the TFT may be negatively impacted. By controlling the ratio of the flow rates of the nitrogen, oxygen, and hydrogen containing gases, the performance of the TFT may be optimized. Additionally, the power density, capping layer deposition pressure, and the temperature may also be controlled to optimize the TFT performance.
    Type: Grant
    Filed: August 22, 2011
    Date of Patent: August 19, 2014
    Assignee: Applied Materials, Inc.
    Inventor: Yan Ye
  • Patent number: 8779435
    Abstract: A semiconductor wafer has a plurality of optical semiconductor devices (namely, semiconductor lasers) which are formed from epitaxially grown layers and arranged across the surface of the semiconductor wafer. The InGaAs epitaxial layer of the semiconductor wafer has an opening (or groove) which continuously extends along and between the plurality of optical semiconductor devices, and which exposes the layer underlying the InGaAs epitaxial layer to at least the layer overlying the InGaAs epitaxial layer. The semiconductor wafer may be scribed along this opening to form a vertically extending crack therein.
    Type: Grant
    Filed: October 12, 2011
    Date of Patent: July 15, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventor: Masato Negishi
  • Patent number: 8765501
    Abstract: Methods of epitaxy of gallium nitride, and other such related films, and light emitting diodes on patterned sapphire substrates, and other such related substrates, are described.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: July 1, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Jie Su, Tuoh-Bin Ng, Olga Kryliouk, Sang Won Kang, Jie Cui
  • Patent number: 8759199
    Abstract: A method of selectively growing a plurality of semiconductor carbon nanotubes using light irradiation. The method includes disposing a plurality of nanodots, which include a catalyst material, on a substrate; growing a plurality of carbon nanotubes from the plurality of nanodots, and irradiating light onto the nanodot to selectively grow the plurality of semiconductor carbon nanotubes.
    Type: Grant
    Filed: September 10, 2010
    Date of Patent: June 24, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-mook Choi, Jae-young Choi, Jin Zhang, Guo Hong
  • Patent number: 8753946
    Abstract: The present invention provides a method of manufacturing an electronic apparatus, such as a lighting device having light emitting diodes (LEDs) or a power generating device having photovoltaic diodes. The exemplary method includes depositing a first conductive medium within a plurality of channels of a base to form a plurality of first conductors; depositing within the plurality of channels a plurality of semiconductor substrate particles suspended in a carrier medium; forming an ohmic contact between each semiconductor substrate particle and a first conductor; converting the semiconductor substrate particles into a plurality of semiconductor diodes; depositing a second conductive medium to form a plurality of second conductors coupled to the plurality of semiconductor diodes; and depositing or attaching a plurality of lenses suspended in a first polymer over the plurality of diodes. In various embodiments, the depositing, forming, coupling and converting steps are performed by or through a printing process.
    Type: Grant
    Filed: February 4, 2012
    Date of Patent: June 17, 2014
    Assignees: NthDegree Technologies Worldwide Inc, NASA, an agency of the United States
    Inventors: William Johnstone Ray, Mark David Lowenthal, Neil O. Shotton, Richard A. Blanchard, Mark Allan Lewandowski, Kirk A. Fuller, Donald Odell Frazier
  • Patent number: 8753947
    Abstract: The present invention provides a method of manufacturing an electronic apparatus, such as a lighting device having light emitting diodes (LEDs) or a power generating device having photovoltaic diodes. The exemplary method includes depositing a first conductive medium within a plurality of channels of a base to form a plurality of first conductors; depositing within the plurality of channels a plurality of semiconductor substrate particles suspended in a carrier medium; forming an ohmic contact between each semiconductor substrate particle and a first conductor; converting the semiconductor substrate particles into a plurality of semiconductor diodes; depositing a second conductive medium to form a plurality of second conductors coupled to the plurality of semiconductor diodes; and depositing or attaching a plurality of lenses suspended in a first polymer over the plurality of diodes. In various embodiments, the depositing, forming, coupling and converting steps are performed by or through a printing process.
    Type: Grant
    Filed: February 4, 2012
    Date of Patent: June 17, 2014
    Assignees: NthDegree Technologies Worldwide Inc, NASA
    Inventors: William Johnstone Ray, Mark David Lowenthal, Neil O. Shotton, Richard A. Blanchard, Mark Allan Lewandowski, Kirk A. Fuller, Donald Odell Frazier
  • Patent number: 8748934
    Abstract: The present disclosure discloses a vertical selection transistor, a memory cell having the vertical selection transistor, a three-dimensional memory array structure and a method for fabricating the three-dimensional memory array structure. The vertical selection transistor comprises: an upper electrode; a lower electrode; a first semiconductor layer, a second semiconductor layer, a third semiconductor layer and a fourth semiconductor layer vertically stacked between the lower electrode and the upper electrode; and a gate stack formed on a side of the second semiconductor layer, in which the first semiconductor layer and the third semiconductor layer are first type doped layers, the second semiconductor layer and the fourth semiconductor layer are second type doped layers, and a doping concentration of the second semiconductor layer is lower than that of the first semiconductor layer or that of the third semiconductor layer respectively.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: June 10, 2014
    Assignee: Tsinghua University
    Inventors: Liyang Pan, Fang Yuan
  • Patent number: 8698255
    Abstract: A simple and cost-effective form of implementing a semiconductor component having a micromechanical microphone structure, including an acoustically active diaphragm as a deflectable electrode of a microphone capacitor, a stationary, acoustically permeable counterelement as a counter electrode of the microphone capacitor, and means for applying a charging voltage between the deflectable electrode and the counter electrode of the microphone capacitor. In order to not impair the functionality of this semiconductor component, even during overload situations in which contact occurs between the diaphragm and the counter electrode, the deflectable electrode and the counter electrode of the microphone capacitor are counter-doped, at least in places, so that they form a diode in the event of contact. In addition, the polarity of the charging voltage between the deflectable electrode and the counter electrode is such that the diode is switched in the blocking direction.
    Type: Grant
    Filed: April 6, 2010
    Date of Patent: April 15, 2014
    Assignee: Robert Bosch GmbH
    Inventors: Frank Reichenbach, Arnim Hoechst, Thomas Buck
  • Patent number: 8679861
    Abstract: In one aspect, a method of enhancing semiconductor chip process variability and lifetime reliability through a three-dimensional (3D) integration applied to electronic packaging is disclosed. Also provided is an arrangement for implementing the inventive method. In another aspect, a method and on-chip controller are disclosed for enhancing semiconductor chip process variability and lifetime reliability through a three-dimensional (3D) integration applied to electronic packaging. Also provided is an on-chip reliability/variability controller arrangement for implementing the inventive method. In yet another aspect, base semiconductor chips, each comprising a plurality of chiplets, are manufactured and tested. For a base semiconductor chip having at least one non-functional chiplet, at least one repair semiconductor chiplet chiplet is vertically stacked. A functional multi-chip assembly is formed, which provides the same functionality as a base semiconductor chip in which all chiplets are functional.
    Type: Grant
    Filed: July 16, 2008
    Date of Patent: March 25, 2014
  • Patent number: 8674399
    Abstract: A light-emitting element includes a ?-Ga2O3 substrate, a GaN-based semiconductor layer formed on the ?-Ga2O3 substrate, and a double-hetero light-emitting layer formed on the GaN-based semiconductor layer.
    Type: Grant
    Filed: June 22, 2011
    Date of Patent: March 18, 2014
    Assignee: Koha Co., Ltd.
    Inventors: Noboru Ichinose, Kiyoshi Shimamura, Kazuo Aoki, Encarnacion Antonia Garcia Villora
  • Publication number: 20140069185
    Abstract: A vacuum-cavity-insulated flow sensor and related fabrication method are described. The sensor comprises a porous silicon wall with numerous vacuum-pores which is created in a silicon substrate, a porous silicon membrane with numerous vacuum-pores which is surrounded and supported by the porous silicon wall, and a cavity with a vacuum-space which is disposed beneath the porous silicon membrane and surrounded by the porous silicon wall. The fabrication method includes porous silicon formation and silicon polishing in HF solution.
    Type: Application
    Filed: September 7, 2012
    Publication date: March 13, 2014
    Inventor: Xiang Zheng Tu
  • Patent number: 8647901
    Abstract: There is provided a method of forming a nitride semiconductor layer, including the steps of firstly providing a substrate on which a patterned epitaxy layer with a pier structure is formed. A protective layer is then formed on the patterned epitaxy layer, exposing a top surface of the pier structure. Next, a nitride semiconductor layer is formed over the patterned epitaxy layer connected to the nitride semiconductor layer through the pier structure, wherein the nitride semiconductor layer, the pier structure, and the patterned epitaxy layer together form a space exposing a bottom surface of the nitride semiconductor layer. Thereafter, a weakening process is performed to remove a portion of the bottom surface of the nitride semiconductor layer and to weaken a connection point between the top surface of the pier structure and the nitride semiconductor layer. Finally, the substrate is separated from the nitride semiconductor layer through the connection point.
    Type: Grant
    Filed: June 11, 2008
    Date of Patent: February 11, 2014
    Assignee: Industrial Technology Research Institute
    Inventors: Yih-Der Guo, Chih-Ming Lai, Jenq-Dar Tsay, Po-Chun Liu
  • Patent number: 8597962
    Abstract: An improved method of fabricating a vertical semiconductor LED is disclosed. Ions are implanted into the LED to create non-conductive regions, which facilitates current spreading in the device. In some embodiments, the non-conductive regions are located in the p-type layer. In other embodiments, the non-conductive layer may be in the multi-quantum well or n-type layer.
    Type: Grant
    Filed: March 29, 2011
    Date of Patent: December 3, 2013
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: San Yu, Chi-Chun Chen
  • Patent number: 8592298
    Abstract: A method for fabricating edge termination structures in gallium nitride (GaN) materials includes providing a n-type GaN substrate having a first surface and a second surface, forming an n-type GaN epitaxial layer coupled to the first surface of the n-type GaN substrate, and forming a growth mask coupled to the n-type GaN epitaxial layer. The method further includes patterning the growth mask to expose at least a portion of the n-type GaN epitaxial layer, and forming at least one p-type GaN epitaxial structure coupled to the at least a portion of the n-type GaN epitaxial layer. The at least one p-type GaN epitaxial structure comprises at least one portion of an edge termination structure. The method additionally includes forming a first metal structure electrically coupled to the second surface of the n-type GaN substrate.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: November 26, 2013
    Assignee: Avogy, Inc.
    Inventors: Linda Romano, David P. Bour, Andrew Edwards, Hui Nie, Isik C. Kizilyalli, Richard J. Brown, Thomas R. Prunty
  • Patent number: 8586433
    Abstract: A compound semiconductor device is provided with a first nitride semiconductor layer of a first conductivity type, a second nitride semiconductor layer of the first conductivity type which is formed over the first nitride semiconctor layer and being in contact with the first nitride semiconductor layer, a third nitride semiconductor layer of a second conductivity type being in contact with the second nitride semiconductor layer, a fourth nitride semiconductor layer of the first conductivity type being in contact with the third nitride semiconductor layer, and an insulating film insulating the first nitride semiconductor layer and the fourth nitride, semiconductor layer from each other. A source electrode is positioned inside an Outer edge of the insulating film in planar view.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: November 19, 2013
    Assignee: Fujitsu Limited
    Inventors: Yuichi Minoura, Toshihide Kikkawa
  • Patent number: 8580626
    Abstract: A semiconductor device and method of manufacturing the device is disclosed. In one aspect, the device includes a semiconductor substrate and a GaN-type layer stack on top of the semiconductor substrate. The GaN-type layer stack has at least one buffer layer, a first active layer and a second active layer. Active device regions are definable at an interface of the first and second active layer. The semiconductor substrate is present on an insulating layer and is patterned to define trenches according to a predefined pattern, which includes at least one trench underlying the active device region. The trenches extend from the insulating layer into at least one buffer layer of the GaN-type layer stack and are overgrown within the at least one buffer layer, so as to obtain that the first and the second active layer are continuous at least within the active device regions.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: November 12, 2013
    Assignee: IMEC
    Inventors: Kai Cheng, Stefan DeGroote
  • Patent number: 8574942
    Abstract: A method of preparing a silicon nanowire and a method of fabricating a lithium secondary battery including the silicon nanowire are provided. The method of preparing a silicon nanowire may include forming a catalyst layer including metal particles separated from one another on a silicon layer, selectively etching the silicon layer contacting the metal particles, and removing the metal particles.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: November 5, 2013
    Assignee: Unist Academy-Industry Research Corporation
    Inventors: Soojin Park, Byoungman Bang, Jung-Pil Lee, Hyun-Kon Song, Jaephil Cho
  • Patent number: 8563343
    Abstract: A method of manufacturing a laser diode device includes: forming, in a semiconductor laser bar, separation trenches extending across all of a transverse dimension of the semiconductor laser bar and defining a mesa stripe, each of the separation trenches having wide portions located at longitudinal edge portions of the semiconductor laser bar and a narrow portion located in a longitudinal central portion of the semiconductor laser bar; scribing, in the semiconductor laser bar, grooves extending parallel to the separation trenches and terminating before reaching longitudinal edge portions of the semiconductor laser bar; and splitting the semiconductor laser bar along the grooves to form cleaved surfaces extending from a bottom surface of the semiconductor laser bar to bottom surfaces of the separation trenches.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: October 22, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventor: Takashi Motoda
  • Patent number: 8558212
    Abstract: A non-volatile memory device structure. The device structure includes a first electrode, a second electrode, a resistive switching material comprising an amorphous silicon material overlying the first electrode, and a thickness of dielectric material having a thickness ranging from 5 nm to 10 nm disposed between the second electrode and the resistive switching layer. The thickness of dielectric material is configured to electrically breakdown in a region upon application of an electroforming voltage to the second electrode. The electrical breakdown allows for a metal region having a dimension of less than about 10 nm by 10 nm to form in a portion of the resistive switching material.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: October 15, 2013
    Assignee: Crossbar, Inc.
    Inventor: Sung Hyun Jo
  • Patent number: 8530290
    Abstract: A thin film transistor includes: a substrate; a semiconductor layer disposed on the substrate, and including a channel region, source and drain regions, and edge regions having a first impurity formed at edges of the source and drain regions, and optionally, in the channel region; a gate insulating layer insulating the semiconductor layer; a gate electrode insulated from the semiconductor layer by the gate insulating layer; and source and drain electrodes electrically connected to the semiconductor layer.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: September 10, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Byoung-Keon Park, Tae-hoon Yang, Jin-Wook Seo, Sei-Hwan Jung, Ki-Yong Lee
  • Patent number: 8530932
    Abstract: A semiconductor fabrication method includes depositing a dummy gate layer onto a substrate, patterning the dummy gate layer, depositing a hardmask layer over the dummy gate layer, patterning the hardmask layer, etching a recess into the substrate, adjacent the dummy gate layer, depositing a semiconductor material into the recess, removing the hardmask layer, depositing replacement spacers onto the dummy gate layer, performing an oxide deposition over the dummy gate layer and replacement spacers, removing the dummy gate and replacement spacers, thereby forming a gate recess in the oxide and depositing a gate stack into the recess.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: September 10, 2013
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Michael A. Guillorn, Isaac Lauer, Amlan Majumdar
  • Patent number: 8524581
    Abstract: Methods and apparatus for depositing thin films incorporating the use of a surfactant are described. Methods and apparatuses include a deposition process and system comprising multiple isolated processing regions which enables rapid repetition of sub-monolayer deposition of thin films. The use of surfactants allows the deposition of high quality epitaxial films at lower temperatures having low values of surface roughness. The deposition of Group III-V thin films such as GaN is used as an example.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: September 3, 2013
    Assignee: Intermolecular, Inc.
    Inventors: Philip A. Kraus, Boris Borisov, Thai Cheng Chua, Sandeep Nijhawan, Yoga Saripalli
  • Patent number: 8524562
    Abstract: A method to reduce (avoid) Fermi Level Pinning (FLP) in high mobility semiconductor compound channel such as Ge and III-V compounds (e.g. GaAs or InGaAs) in a Metal Oxide Semiconductor (MOS) device. The method is using atomic hydrogen which passivates the interface of the high mobility semiconductor compound with the gate dielectric and further repairs defects. The methods further improve the MOS device characteristics such that a MOS device with a quantum well is created.
    Type: Grant
    Filed: September 15, 2009
    Date of Patent: September 3, 2013
    Assignee: IMEC
    Inventors: Wei-E Wang, Han Chung Lin, Marc Meuris
  • Patent number: 8505481
    Abstract: In certain desirable embodiments, the present invention relates to the use of 15N isotopes into GaAsN, InAsN or GaSbN films for ion beam analysis. A semiconductor-nitride assembly for growing and analyzing crystal growth in a group III-V semiconductor sample that includes: a substrate; a buffer layer deposited on the substrate, a nitrogen gas injector to incorporate enriched nitrogen gas and the nitrogen gas injector includes a concentration of enriched nitrogen gas, a thin film consisting of at least one group III element containing compound where at least one group III element is covalently bonded with the nitrogen in the presence of the same or different group V element of the buffer layer, and a proton beam to analyze the incorporation of the nitrogen gas in the thin film layer is described.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: August 13, 2013
    Assignee: The United States of America as represented by the Secretary of the Army
    Inventors: Stefan P Svensson, John D Demaree
  • Patent number: 8492862
    Abstract: One object is to provide a deposition technique for forming an oxide semiconductor film. By forming an oxide semiconductor film using a sputtering target including a sintered body of a metal oxide whose concentration of hydrogen contained is low, for example, lower than 1×1016 atoms/cm3, the oxide semiconductor film contains a small amount of impurities such as a compound containing hydrogen typified by H2O or a hydrogen atom. In addition, this oxide semiconductor film is used as an active layer of a transistor.
    Type: Grant
    Filed: November 12, 2010
    Date of Patent: July 23, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toru Takayama, Keiji Sato
  • Publication number: 20130171832
    Abstract: An apparatus and method for delivering fluids to a semiconductor chamber for combinatorial processing is provided. In some embodiments the apparatus is comprised of a showerhead assembly having a plurality of processing sectors separated by a purge member. The processing sectors are configured to receive one or more processing fluids for combinatorial processing on a substrate. The processing sectors are isolated by a purge fluid conveyed through the purge member. The purge member is configured to selectively control the profile of the purge fluid to enhance isolation of the processing fluids within each sector. The profile of the purge fluid is manipulated by selectively controlling the shape and/or density of the purge curtain, independently between each processing sector.
    Type: Application
    Filed: December 28, 2011
    Publication date: July 4, 2013
    Applicant: Intermolecular Inc.
    Inventor: Wayne French
  • Patent number: 8450813
    Abstract: There is provided a fin transistor structure and a method of fabricating the same. The fin transistor structure comprises a fin formed on a semiconductor substrate, wherein a bulk semiconductor material is formed between a portion of the fin serving as the channel region of the transistor structure and the substrate, and an insulation material is formed between remaining portions of the fin and the substrate. Thereby, it is possible to reduce the current leakage while maintaining the advantages of body-tied structures.
    Type: Grant
    Filed: June 25, 2010
    Date of Patent: May 28, 2013
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Zhijiong Luo, Haizhou Yin, Huilong Zhu
  • Patent number: 8445973
    Abstract: There is provided a fin transistor structure and a method of fabricating the same. The fin transistor structure comprises a fin formed on a semiconductor substrate, wherein an insulation material is formed between a portion of the fin serving as the channel region of the transistor structure and the substrate, and a bulk semiconductor material is formed between remaining portions of the fin and the substrate. Thereby, it is possible to reduce the current leakage while maintaining the advantages such as low cost and high heat transfer.
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: May 21, 2013
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Zhijiong Luo, Huilong Zhu, Haizhou Yin
  • Patent number: 8435892
    Abstract: It is an object of an invention disclosed in the present specification to provide a transistor having low contact resistance. In the transistor, a semiconductor film including an impurity element imparting P-type or N-type conductivity, an insulating film formed thereover, and an electrode or a wiring that is electrically connected to the semiconductor film through a contact hole formed at least in the insulating film are included; the semiconductor film has a first range of a concentration of the impurity element (1×1020/cm3 or less) that is included in a deeper region than predetermined depth, and a second range of a concentration of the impurity element (more than 1×1020/cm3) that is included in a shallower region than the predetermined depth; and a deeper region than a portion in contact with the electrode or the wiring in the semiconductor film is in the first range of the concentration of the impurity element.
    Type: Grant
    Filed: October 20, 2010
    Date of Patent: May 7, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Atsuo Isobe, Keiko Saito, Tomohiko Sato
  • Patent number: 8420439
    Abstract: A method of producing a radiation-emitting thin film component includes providing a substrate, growing nanorods on the substrate, growing a semiconductor layer sequence with at least one active layer epitaxially on the nanorods, applying a carrier to the semiconductor layer sequence, and detaching the semiconductor layer sequence and the carrier from the substrate by at least partial destruction of the nanorods.
    Type: Grant
    Filed: October 19, 2009
    Date of Patent: April 16, 2013
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Hans-Jürgen Lugauer, Klaus Streubel, Martin Strassburg, Reiner Windisch, Karl Engl
  • Patent number: 8420419
    Abstract: A method of fabricating a III-nitride semiconductor laser device includes: preparing a substrate product, where the substrate product has a laser structure, the laser structure includes a semiconductor region and a substrate of a hexagonal III-nitride semiconductor, the substrate has a semipolar primary surface, and the semiconductor region is formed on the semipolar primary surface; scribing a first surface of the substrate product to form a scribed mark, the scribed mark extending in a direction of an a-axis of the hexagonal III-nitride semiconductor; and after forming the scribed mark, carrying out breakup of the substrate product by press against a second region of the substrate product while supporting a first region of the substrate product but not supporting the second region thereof, to form another substrate product and a laser bar.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: April 16, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shimpei Takagi, Yusuke Yoshizumi, Koji Katayama, Masaki Ueno, Takatoshi Ikegami
  • Patent number: 8415684
    Abstract: An apparatus includes a wafer with a number of openings therein. For each opening, an LED device is coupled to a conductive carrier and the wafer in a manner so that each of the coupled LED device and a portion of the conductive carrier at least partially fill the opening. A method of fabricating an LED device includes forming a number of openings in a wafer. The method also includes coupling light-emitting diode (LED) devices to conductive carriers. The LED devices with conductive carriers at least partially fill each of the openings.
    Type: Grant
    Filed: November 12, 2010
    Date of Patent: April 9, 2013
    Assignee: TSMC Solid State Lighting Ltd.
    Inventors: Hsing-Kuo Hsia, Chih-Kuang Yu, Gordon Kuo, Chyi Shyuan Chern
  • Publication number: 20130049178
    Abstract: A bonded wafer structure having a handle wafer, a device wafer, and an interface region with an abrupt transition between the conductivity profile of the device wafer and the handle wafer is used for making semiconductor devices. The improved doping profile of the bonded wafer structure is well suited for use in the manufacture of integrated circuits. The bonded wafer structure is especially suited for making radiation-hardened integrated circuits.
    Type: Application
    Filed: August 25, 2011
    Publication date: February 28, 2013
    Applicant: Aeroflex Colorado Springs Inc.
    Inventors: David B. Kerwin, Joseph Benedetto
  • Publication number: 20130049177
    Abstract: A bonded wafer structure having a handle wafer, a device wafer, and an interface region with an abrupt transition between the conductivity profile of the device wafer and the handle wafer is used for making semiconductor devices. The improved doping profile of the bonded wafer structure is well suited for use in the manufacture of integrated circuits. The bonded wafer structure is especially suited for making radiation-hardened integrated circuits.
    Type: Application
    Filed: August 25, 2011
    Publication date: February 28, 2013
    Applicant: Aeroflex Colorado Springs Inc.
    Inventors: David B. Kerwin, Joseph M. Benedetto
  • Patent number: RE45084
    Abstract: The present invention is a method of fabricating an optical device using multiple sacrificial spacer layers. The first step in this process is to fabricate the underlying base structure and deposit an optical structure thereon. A facet is then created at the ends of the optical structure and alternating sacrificial and intermediate layers are fabricated on the device. A mask layer is deposited on the structure, with openings created in the layers to allow use of an etchant. User-defined portions of the spacer layers are subsequently removed with the etchant to create air gaps between the intermediate layers.
    Type: Grant
    Filed: April 19, 2012
    Date of Patent: August 19, 2014
    Assignee: National Security Agency
    Inventors: John L. Fitz, Daniel S. Hinkel, Scott C. Horst