Alloying Of Doping Material With Group Iii-v Compound (epo) Patents (Class 257/E21.155)
  • Patent number: 10658184
    Abstract: A method for semiconductor manufacturing includes providing a substrate and a patterning layer over the substrate; forming a hole in the patterning layer; applying a first directional etching along a first direction to inner sidewalls of the hole; and applying a second directional etching along a second direction to the inner sidewalls of the hole, wherein the second direction is different from the first direction.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: May 19, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Tien Shen, Chi-Cheng Hung, Chin-Hsiang Lin, Chien-Wei Wang, Ching-Yu Chang, Chih-Yuan Ting, Kuei-Shun Chen, Ru-Gun Liu, Wei-Liang Lin, Ya Hui Chang, Yuan-Hsiang Lung, Yen-Ming Chen, Yung-Sung Yen
  • Patent number: 8623683
    Abstract: According to one embodiment, in a nitride semiconductor light emitting device, a first clad layer includes an n-type nitride semiconductor. An active layer is formed on the first clad layer, and includes an In-containing nitride semiconductor. A GaN layer is formed on the active layer. A first AlGaN layer is formed on the GaN layer, and has a first Al composition ratio. A p-type second AlGaN layer is formed on the first AlGaN layer, has a second Al composition ratio higher than the first Al composition ratio, and contains a larger amount of Mg than the GaN layer and the first AlGaN layer. A second clad layer is formed on the second AlGaN layer, and includes a p-type nitride semiconductor.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: January 7, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hajime Nago, Koichi Tachibana, Toshiyuki Oka, Shigeya Kimura, Shinya Nunoue
  • Patent number: 8455370
    Abstract: This invention provides methods that permit wafers to be loaded and unloaded in a gas-phase epitaxial growth chamber at high temperatures. Specifically, this invention provides a method for moving wafers or substrates that can bathe a substrate being moved in active gases that are optionally temperature controlled. The active gases can act to limit or prevent sublimation or decomposition of the wafer surface, and can be temperature controlled to limit or prevent thermal damage. Thereby, previously-necessary temperature ramping of growth chambers can be reduced or eliminated leading to improvement in wafer throughput and system efficiency.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: June 4, 2013
    Assignee: Soitec
    Inventors: Michael Albert Tischler, Ronald Thomas Bertram, Jr.
  • Patent number: 8415180
    Abstract: Provided is a method for fabricating a wafer product including an active layer grown on a gallium oxide substrate and allowing an improvement in emission intensity. In step S105, a buffer layer 13 comprised of a Group III nitride such as GaN, AlGaN, or AlN is grown at 600 Celsius degrees on a primary surface 11a of a gallium oxide substrate 11. After the growth of the buffer layer 13, while supplying a gas G2, which contains hydrogen and nitrogen, into a growth reactor 10, the gallium oxide substrate 11 and the buffer layer 13 are exposed to an atmosphere in the growth reactor 11 at 1050 Celsius degrees. A Group III nitride semiconductor layer 15 is grown on the modified buffer layer. The modified buffer layer includes, for example, voids. The Group III nitride semiconductor layer 15 can be comprised of GaN and AlGaN. When the Group III nitride semiconductor layer 15 is formed of these materials, excellent crystal quality is obtained on the modified buffer layer 14.
    Type: Grant
    Filed: March 1, 2010
    Date of Patent: April 9, 2013
    Assignees: Sumitomo Electric Industries, Ltd., Koha Co., Ltd.
    Inventors: Shin Hashimoto, Katsushi Akita, Kensaku Motoki, Shinsuke Fujiwara, Hideaki Nakahata
  • Patent number: 8153536
    Abstract: This invention provides apparatus, protocols, and methods that permit wafers to be loaded and unloaded in a gas-phase epitaxial growth chamber at high temperatures. Specifically, this invention provides a device for moving wafers or substrates that can bath a substrate being moved in active gases that are optionally temperature controlled. The active gases can act to limit or prevent sublimation or decomposition of the wafer surface, and can be temperature controlled to limit or prevent thermal damage. Thereby, previously-necessary temperature ramping of growth chambers can be reduced or eliminated leading to improvement in wafer throughput and system efficiency.
    Type: Grant
    Filed: November 12, 2008
    Date of Patent: April 10, 2012
    Assignee: Soitec
    Inventors: Michael Albert Tischler, Ronald Thomas Bertram, Jr.
  • Publication number: 20110233711
    Abstract: A method for local contacting and local doping of a semiconductor layer including the following process steps: A) Generation of a layer structure on the semiconductor layer through i) application of at least one intermediate layer on one side of the semiconductor layer, and ii) application of at least one metal layer onto the intermediate layer last applied in step i), wherein the metal layer at least partly covers the last applied intermediate layer, B) Local heating of the layer structure in such a manner that in a local region a short-time melt-mixture of at least partial regions of at least the layers: metal layer, intermediate layer and semiconductor layer, forms. After solidification of the melt-mixture, a contacting is created between metal layer and semiconductor layer. It is essential that in step A) i) at least one intermediate layer designed as dopant layer is applied, which contains a dopant wherein the dopant has a greater solubility in the semiconductor layer than the metal of the metal layer.
    Type: Application
    Filed: August 20, 2009
    Publication date: September 29, 2011
    Applicant: Fraunhofer-Gesellschaft Zur Forderung Der Angewandten Forschung E.V.
    Inventors: Ralf Preu, Andreas Grohe, Daniel Biro, Jochen Rentsch, Marc Hofmann, Jan-Frederik Nekarda, Andreas Wolf
  • Patent number: 7968893
    Abstract: Disclosed are a semiconductor light emitting device, which can improve characteristics of the semiconductor light emitting device such as a forward voltage characteristic and a turn-on voltage characteristic, increase light emission efficiency by lowering an input voltage, and increase reliability of the semiconductor light emitting device by a low-voltage operation, and a method of manufacturing the same. The semiconductor light emitting device includes: an n-type GaN semiconductor layer; an active layer formed on a gallium face of the n-type GaN semiconductor layer; a p-type semiconductor layer formed on the active layer; and an n-type electrode formed on a nitrogen face of the n-type GaN semiconductor layer and including a lanthanum (La)-nickel (Ni) alloy.
    Type: Grant
    Filed: September 15, 2008
    Date of Patent: June 28, 2011
    Assignee: Samsung LED Co., Ltd.
    Inventors: Sang Yeob Song, Jin Hyun Lee, Yu Seung Kim, Kwang Ki Choi, Pun Jae Choi, Hyun Soo Kim, Sang Bum Lee
  • Patent number: 7842595
    Abstract: A method for manufacturing an electronic-photonic device. Epitaxially depositing an n-doped III-V composite semiconductor alloy buffer layer on a crystalline surface of a substrate at a first temperature. Forming an active layer on the n-doped III-V epitaxial composite semiconductor alloy buffer layer at a second temperature, the active layer including a plurality of spheroid-shaped quantum dots. Depositing a p-doped III-V composite semiconductor alloy capping layer on the active layer at a third temperature. The second temperature is less than the first temperature and the third temperature. The active layer has a photoluminescence intensity emission peak in the telecommunication C-band.
    Type: Grant
    Filed: March 4, 2009
    Date of Patent: November 30, 2010
    Assignee: Alcatel-Lucent USA Inc.
    Inventors: Nick Sauer, Nils Weimann, Liming Zhang
  • Publication number: 20090206361
    Abstract: A group III nitride semiconductor light emitting device with a double sided electrode structure which has a low driving voltage as well as excellent light emission efficiency is provided, and the group III nitride semiconductor light emitting device includes at least an impurity layer 30 composed of a high concentration layer 3b made of a group III nitride semiconductor containing high concentration of impurity atoms, and a low concentration layer 3a made of a group III nitride semiconductor containing impurity atoms whose concentration is lower than that of the high concentration layer 3b; and a group III nitride semiconductor layer 2, and the lower concentration layer 3a and the high concentration layer 3b are continuously formed on the group III nitride semiconductor layer 2 in this order to form the group III nitride semiconductor light emitting device.
    Type: Application
    Filed: March 23, 2007
    Publication date: August 20, 2009
    Applicant: SHOWA DENKO K.K.,
    Inventors: Hisayuki Miki, Hiromitsu Sakai
  • Patent number: 7557007
    Abstract: The method for manufacturing a semiconductor device according to the invention includes forming a thick silicon oxide film uniformly in a trench. Argon ions or the like implanted obliquely into the trench to form an ion implanted damaged region selectively in the portion of the silicon oxide film on the trench sidewall utilizing the shadowing effects of the oblique ion implantation. The silicon oxide film is wet etched to selectively remove the silicon oxide film in the ion implanted damaged region utilizing the etching rate difference, wherein the etching rate is faster in the damaged region than in the undamaged region. As a result, a thick residual oxide film is formed on the bottom and the lower sidewall portion of the trenchwithout causing any bird's beak.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: July 7, 2009
    Assignee: Fuji Electric Device Technology Co., Ltd.
    Inventors: Kazuo Shimoyama, Mutsumi Kitamura, Hongfei Lu
  • Patent number: 7550368
    Abstract: A group-III nitride semiconductor stack comprises a single-crystal substrate, a first group-III nitride layer formed on a principal surface of the single-crystal substrate, a graded low-temperature deposited layer formed on the group-III nitride layer and made of nitride in which group-III element composition is continuously changed, and a second group-III nitride layer formed on the graded low-temperature deposited layer.
    Type: Grant
    Filed: May 24, 2006
    Date of Patent: June 23, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideto Sugawara, Tsunenori Hiratsuka
  • Patent number: 7235486
    Abstract: In one embodiment, a method for forming a tungsten material on a substrate surface is provide which includes positioning a substrate within a deposition chamber, heating the substrate to a deposition temperature, and exposing the substrate sequentially to a first reducing gas and a tungsten precursor gas to form a tungsten nucleation layer on the substrate during an atomic layer deposition (ALD) process. The method may further provide exposing the substrate to a deposition gas comprising a second reducing gas and the tungsten precursor gas to form a tungsten bulk layer on the tungsten nucleation layer during a chemical vapor deposition (CVD) process. Examples include that the ALD and CVD processes are conducted in the same deposition chamber or in different deposition chambers.
    Type: Grant
    Filed: August 29, 2006
    Date of Patent: June 26, 2007
    Assignee: Applied Materials, Inc.
    Inventors: Moris Kori, Alfred W. Mak, Jeong Soo Byun, Lawrence Chung-Lai Lei, Hua Chung, Ashok Sinha, Ming Xi
  • Patent number: 7115494
    Abstract: A method and system to reduce the resistance of refractory metal layers by controlling the presence of fluorine contained therein. The present invention is based upon the discovery that when employing ALD techniques to form refractory metal layers on a substrate, the carrier gas employed impacts the presence of fluorine in the resulting layer. As a result, the method features chemisorbing, onto the substrate, alternating monolayers of a first compound and a second compound, with the second compound having fluorine atoms associated therewith, with each of the first and second compounds being introduced into the processing chamber along with a carrier gas to control a quantity of the fluorine atoms associated with the monolayer of the second compound.
    Type: Grant
    Filed: January 24, 2006
    Date of Patent: October 3, 2006
    Assignee: Applied Materials, Inc.
    Inventors: Ashok Sinha, Ming Xi, Moris Kori, Alfred W. Mak, Jeong Soo Byun, Lawrence Chung-Lai Lei, Hua Chung