Abstract: A package for a micro-electromechanical device (MEMS package) includes an inner enclosure having an inner cavity defined therein, and a fill port channel communicating with the inner cavity and of sufficient length to allow a quantity of adhesive to enter the fill port channel while preventing the adhesive from entering the inner cavity.

Abstract: A repairing method, repairing device and repairing structure for repairing a signal line of an array substrate having the disconnected defect, including: setting a repairing route according to a position of the disconnected defect and determining a position at which a filling portion is required to be formed according to the repairing route; forming the filling portion at the position at which the filling portion is required to be formed; and forming a repairing line along the repairing route. By detecting the repairing route before repairing the disconnected defect by forming the filling portion according to the repairing route, the present disclosure can avoid the disconnection of the repairing line caused by great height differences of the surface under the repairing line and improve the repairing success rate of the disconnected defect.

Abstract: A device includes a capping substrate bonded with a substrate structure. The substrate structure includes an integrated circuit structure. The integrated circuit structure includes a top metallic layer disposed on an outgasing prevention structure. At least one micro-electro mechanical system (MEMS) device is disposed over the top metallic layer and the outgasing prevention structure.

Abstract: A method of protecting an electronics package is discussed along with devices formed by the method. The method involves providing at least one electronic component that requires protecting from tampering and/or reverse engineering. Further, the method includes mixing into a liquid glass material at least one of high durability micro-particles or high-durability nano-particles, to form a coating material. Further still, the method includes depositing the coating material onto the electronic component and curing the coating material deposited.

Abstract: An integrated circuit includes a substrate and at least one chip. Each chip is disposed over the substrate or the other chip. Solder bumps are disposed between the substrate and the at least one chip. An insulating film is disposed around the solder bumps and provides electrical insulation for the solder bumps except areas for interconnections. A thermally conductive underfill is disposed between the substrate, the at least one chip, and the solder bumps.

Abstract: Disclosed herein are a semiconductor package and a method of manufacturing the same, the semiconductor package including: a molding member having a cavity formed therein; a device mounted in the cavity; an insulating member formed inside the cavity and on and/or beneath the molding member and the device; a circuit layer formed on the insulating member, and including vias and connection pads electrically connected with the device; a solder resist layer formed on the circuit layer, and having openings exposing upper portions of the connection pads; and solder balls formed in the openings.

Abstract: A device for resin coating is used for producing an LED package including an LED element covered with resin containing phosphor. In a state in which a trial coating material 43 is located by a clamp unit 63, a trial coating of resin applied to the trial coating material 43 is irradiated with excitation light and light emitted from the phosphor contained in the resin is measured by an emission characteristic measuring unit 39. A deviation of the measurement result of the emission characteristic measuring unit from a prescribed emission characteristic is determined, and then a proper amount of resin to be applied to the LED element is derived for actual production based on the deviation.

Abstract: A transition layer 38 is provided on a die pad 22 of an IC chip 20 and integrated into a multilayer printed circuit board 10. Due to this, it is possible to electrically connect the IC chip 20 to the multilayer printed circuit board 10 without using lead members and a sealing resin. Also, by providing the transition layer 38 made of copper on an aluminum pad 24, it is possible to prevent a resin residue on the pad 24 and to improve connection characteristics between the die pad 24 and a via hole 60 and reliability.

Abstract: A device includes a capping substrate bonded with a substrate structure. The substrate structure includes an integrated circuit structure. The integrated circuit structure includes a top metallic layer disposed on an outgasing prevention structure. At least one micro-electro mechanical system (MEMS) device is disposed over the top metallic layer and the outgasing prevention structure.

Abstract: An exemplary structure for a field effect transistor according to at least one embodiment comprises a substrate comprising a surface; a gate structure comprising sidewalls and a top surface over the substrate; a spacer adjacent to the sidewalls of the gate structure; a first contact etch stop layer over the spacer and extending along the surface of the substrate; an interlayer dielectric layer adjacent to the first contact etch stop layer, wherein a top surface of the interlayer dielectric layer is coplanar with the top surface of the gate structure; and a second contact etch stop layer over the top surface of the gate structure.

Abstract: An encapsulation structure comprising at least one hermetically sealed cavity in which at least the following are encapsulated: a device, an electronic component produced on a first substrate, and a getter material layer covering the electronic component in order to block the gases capable of being degassed by the electronic component, and in which the device is not covered by the getter material layer.

Abstract: A semiconductor sensor die is packaged with a footed lid that has side walls and a top portion with a central hole. Gel material is dispensed into a cavity formed by the side walls such that it covers the die prior to attaching the lid top portion.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base substrate having a component side; mounting a device over the component side; forming a shield connector on the component side adjacent the device; forming a package interconnect on the component side outside a region having the shield connector and the device; applying an encapsulant around the package interconnect, the shield connector, and the device; and mounting a shield structure on the encapsulant, the shield connector, and the device, with the package interconnect partially exposed.

Abstract: An electronic device according to the invention includes: a substrate; an MEMS structure formed above the substrate; and a covering structure defining a cavity in which the MEMS structure is arranged, wherein the covering structure has a first covering layer covering from above the cavity and having a through-hole in communication with the cavity and a second covering layer formed above the first covering layer and closing the through-hole, the first covering layer has a first region located above at least the MEMS structure and a second region located around the first region, the first covering layer is thinner in the first region than in the second region, and a distance between the substrate and the first covering layer in the first region is longer than a distance between the substrate and the first covering layer in the second region.

Abstract: A method of manufacturing is provided that includes providing a semiconductor chip device that has a circuit board and a first semiconductor chip coupled thereto. A lid is placed on the circuit board. The lid includes an opening and an internal cavity. A liquid thermal interface material is placed in the internal cavity for thermal contact with the first semiconductor chip and the circuit board.

Abstract: A MEMS device is packaged in a process which hydrogen (H) deuterium (D) for reduced stiction. H is exchanged with D by exposing the MEMS device with a deuterium source, such as deuterium gas or heavy water vapor, optionally with the assistance of a direct or downstream plasma.

Abstract: A housing for an optoelectronic component is disclosed, having a plastic base body that has a front side with an assembly region for at least one radiation emitting or radiation detecting body, wherein the plastic base body is formed from at least one first plastic component and at least one second plastic component. The second plastic component is disposed on the front side of the plastic base body, and is formed from a material that differs from the first plastic component in at least one optical property, and forms an optically functional region of the plastic base body. Further, a method for producing a housing for an optoelectronic component and a light emitting diode component is disclosed.

Abstract: To provide a semiconductor equipment having high heat-transfer effect and breakdown voltage, and a method of manufacturing the same. The semiconductor equipment includes: a sealed container; a stem connected to the sealed container via a stem peripheral portion; and a semiconductor chip mounted on a top surface of the stem, inside the sealed container. The semiconductor chip is electrically connected to a lead provided to the stem, the stem peripheral portion, which is of a material that is different from the material of stem and the same as the material of the sealed container, is bonded along a periphery of the stem, and the sealed container is filled with a working fluid including at least one of ethanol, a perfluorocarbon, and a fluoroether.

Abstract: A semiconductor device and a fabrication method of the semiconductor device, the semiconductor device including: a gate electrode, a source electrode, and a drain electrode which are placed on a first surface of a substrate, and have a plurality of fingers; a gate terminal electrode, a source terminal electrode, and the drain terminal electrode which governed and formed a plurality of fingers for every the gate electrode, the source electrode, and the drain electrode; an active area placed on an underneath part of the gate electrode, the source electrode, and the drain electrode, on the substrate between the gate electrode and source electrode, and on the substrate between the gate electrode and the drain electrode; a sealing layer which is placed on the active area, the gate electrode, the source electrode, and the drain electrode through a cavity part, and performs a hermetic seal of the active area, the gate electrode, the source electrode, and the drain electrode.

Abstract: A method for manufacturing a semiconductor module, includes the steps of preparing a board; mounting a semiconductor device on the second metal foil; placing a resin case onto the board for surrounding a first metal foil, an insulating sheet, the second metal foil, and the semiconductor device; pouring a resin in a paste form into the case to fill a space relative to the first metal foil, insulating sheet, the second metal foil and the semiconductor device; and heat-curing the resin. A bottom end of a peripheral wall of the case is located above a bottom surface of the first metal. The bottom surface of the first metal foil and the resin form a flat bottom surface to contact an external mounting member.

Abstract: A light emitting device having a structure in which oxygen and moisture are prevented from reaching light emitting elements, and a method of manufacturing the same, are provided. Further, the light emitting elements are sealed by using a small number of process steps, without enclosing a drying agent. The present invention has a top surface emission structure. A substrate on which the light emitting elements are formed is bonded to a transparent sealing substrate. The structure is one in which a transparent second sealing material covers the entire surface of a pixel region when bonding the two substrates, and a first sealing material (having a higher viscosity than the second sealing material), which contains a gap material (filler, fine particles, or the like) for protecting a gap between the two substrates, surrounds the pixel region. The two substrates are sealed by the first sealing material and the second sealing material.

Abstract: This application relates to a method of manufacturing a semiconductor device comprising: providing a metal carrier; placing the metal carrier into a mold for forming a molded structure holding the metal carrier; segmenting the metal carrier into at least two disconnected metal carrier segments; and attaching a semiconductor chip to the molded structure.

Abstract: The present invention discloses a semiconductor device package structure with redistribution layer (RDL) and through silicon via (TSV) techniques. The package structure comprises an electronic element which includes a dielectric layer on a backside surface of the electronic element, a plurality of first conductive through vias across through the electronic element and the dielectric layer, and a plurality of conductive pads accompanying the first conductive through vias on an active surface of the electronic element; a filler material disposed adjacent to the electronic element; a first redistribution layer disposed over the dielectric layer and the filler material, and connected to the first conductive through vias; a first protective layer disposed over the active surface of the electronic element, the conductive pads, and the filler material; and a second protective layer disposed over the redistribution layer, the dielectric layer, and the filler material.

Abstract: A method of manufacturing a stacked die module includes applying a plurality of stacked die structures to a carrier. Each stacked die structure includes a first semiconductor die applied to the carrier and a second semiconductor die stacked over the first semiconductor die. The second semiconductor die has a larger lateral surface area than the first semiconductor die. A dam is applied around each of the stacked die structures, thereby forming an enclosed cavity for each of the stacked die structures. The enclosed cavity for each stacked die structure surrounds the first semiconductor die of the stacked die structure.

Abstract: The invention relates to a hermetically sealed semiconductor module and more particularly to repacking a non-hermetically sealed semiconductor module thereby forming a hermetically sealed semiconductor module.

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a chip and a substrate. The method also includes bonding the chip to the substrate. The method also includes, after the bonding the chip, dispensing a sealing material between the chip and the substrate. In accordance with the method, the chip and the substrate are maintained within a temperature range from the bonding the chip to the dispensing the sealing material, and wherein a lower limit of the temperature range is approximately twice a room temperature.

Abstract: A method for manufacturing a laser device includes fixing a laser chip to a holder via a metal having a low melting point by melting the metal at a temperature higher than the melting point, heating the holder to which the laser chip is fixed at a heat treatment temperature that is lower than the melting point and, thereafter, sealing the laser chip by covering the holder to which the laser chip is fixed with a cap. The heating step may be performed in an atmosphere in which ozone is generated or an atmosphere in which oxygen plasma is generated. Furthermore, the holder to which the laser chip is fixed is covered with a cap to make a hermetically sealed package in dry air or an inert gas, and then an ultraviolet ray is irradiated into the package while it is heated.

Abstract: Devices, systems, and methods for semiconductor die temperature management are described and discussed herein. An IC device is described that includes at least one intra-die cooling structure. In an embodiment, the IC device includes a semiconductor die formed of integral device layers and further includes at least one coolant reservoir and at least one coolant channel. In an embodiment, the at least one coolant reservoir and at least one coolant channel are disposed wholly within the semiconductor die. In various embodiments, at least one coolant reservoir and at least one coolant channel are constructed and arranged to circulate coolant fluid in proximity to at least one IC device structure in order to decrease and or normalize an operating temperature of the IC device. In other embodiments, systems and methods for designing and/or fabricating IC die that include at least one intra-die cooling structure are provided herein.

Abstract: This invention is a method for manufacturing a high-frequency module device. A high-frequency circuit unit (2) in which first to third unit wiring layers (5) to (7), each having a capacitor (12) or the like at a part, are stacked and formed on flattened one surface of a dummy board (30) so that a third pattern wiring is exposed from a connection surface (2a) of an uppermost layer is mounted on a mounting surface (3a) of a base board (3) where an input/output terminal part (18) is exposed, in such a manner that the third pattern wiring and the input/output terminal part are connected with each other, and after that, the dummy board is removed. A high-frequency module device is thus manufactured.

Abstract: A power semiconductor module comprising a substrate, a circuit formed thereon and having a plurality of conductor tracks that are electrically insulated from one another and power semiconductor components arranged on the conductor tracks. The latter are connected in a circuit-conforming manner by a connection device, which has an alternating layer sequence of at least two electrically conductive layers with at least one electrically insulating layer between them. In this case, the substrate has a first sealing area, which uninterruptedly encloses the circuit. Furthermore, this sealing area is connected to an assigned second sealing area on a layer of the connection device by a connection layer. According to the invention, this power semiconductor module is produced by applying pressure to the substrate, to the power semiconductor components and to the connection device.

Abstract: A first semiconductor element is mounted on a wiring board. A second semiconductor element having a portion projecting to an outer side of an outer periphery of the first semiconductor element is disposed on the first semiconductor element via an adhesive. The adhesive has a viscosity (?0.5 rpm) at a low-rotation speed in a range from 10 Pa·s to 150 Pa·s and a thixotropic ratio of 2 or higher expressed by a ratio (?0.5 rpm/?5 rpm) of the viscosity (?0.5 rpm) at the low-rotation speed to a viscosity (?5 rpm) at a high-rotation speed. The second semiconductor element is bonded onto the first semiconductor element while the adhesive is filled in a hollow portion between the projecting portion of the second semiconductor element and the wiring board.

Abstract: The present application relates to a multiple component which is to be subsequently individualized by forming components containing active structures, in addition to a corresponding component which can be used in microsystem technology systems. The multiple component and/or component comprises a flat substrate and also a flat cap structure which are bound to each other such that they surround at least one first and one second cavity per component, which are sealed against each other and towards the outside. The first of the two cavities is provided with getter material and due to the getter material has a different internal pressure and/or a different gas composition than the second cavity. The present application also relates to a method for producing the type of component and/or components for which gas mixtures of various types of gas have a different absorption ratio in relation to the getter material.

Abstract: An integrated circuit package is disclosed. The integrated circuit package comprises an integrated circuit die having a plurality of solder bumps; and a substrate comprising a first plurality of contact pads on a first surface and a second plurality of contact pads on a second surface. The plurality of solder bumps on the integrated circuit die is coupled to the first plurality of contact pads on the first surface of the substrate, wherein at least one edge of the substrate is formed after the integrated circuit die is attached to the substrate. According to one embodiment of the invention, the at least one edge of the substrate is formed after excess substrate material is detached at designated areas. According to another aspect of the invention, an assembly fixture is disclosed. An apparatus and method for assembling an integrated circuit package are also disclosed.

Abstract: A sealable microelectronic device providing mechanical stress endurance which includes a semiconductor substrate. A substantially continuous sealing element is positioned adjacent an outer periphery and between a microelectronic component and the semiconductor substrate, or another microelectronic component. The sealing element seals the microelectronic component to the substrate or another microelectronic component, and provides structural support to the microelectronic device.

Abstract: According to an exemplary embodiment, a wafer level package includes a device wafer including at least one device wafer contact pad and a device, and where the at least one device wafer contact pad is electrically connected to the device. The wafer level package includes a first polymer layer situated over the device wafer. The wafer level package includes at least one passive component situated over the first polymer layer and having a first terminal and a second terminal. The first terminal of the at least one passive component is electrically connected to the at least one device wafer contact pad. The wafer level package includes a second polymer layer situated over the at least one passive component. The wafer level package includes at least one polymer layer contact pad situated over the second polymer layer and electrically connected to the second terminal of the at least one passive component.

Abstract: In the present invention, an etching hole 21 is formed in a polysilicon film 14 as a cavity-wall member. Through the etching hole 21, hydrofluoric acid is injected, so as to dissolve a silicon oxide film 13, thereby forming a cavity 22. In the cavity 22, a detecting unit 12 of a sensor is in an exposed condition. Next, by sputtering, an Al film 16 is deposited in the etching hole 21 and on an upper face of a substrate. Thereafter, a portion of the Al film 16 positioned on the polysilicon film 14 is removed by etching back, thereby leaving only a metal closure 16a of Al which closes the etching hole. The sputtering step is performed under a pressure of 5 Pa or less, so that the pressure in the cavity can be held to be low.

Abstract: An LGA structure is provided having at least one semiconductor device over a substrate and a mechanical load apparatus over the semiconductor device. The structure includes a load-distributing material between the mechanical load apparatus and the substrate. Specifically, the load-distributing material is proximate a first side of the semiconductor device and a second side of the semiconductor device opposite the first side of the semiconductor device. Furthermore, the load-distributing material completely surrounds the semiconductor device and contacts the mechanical load apparatus, the substrate, and the semiconductor device. The load-distributing material can be thermally conductive and comprises an elastomer and/or a liquid. The load-distributing material comprises a LGA interposer adapted to connect the substrate to a PCB below the substrate and/or a second substrate. Moreover, the load-distributing material comprises compressible material layers and rigid material layers.

Abstract: Provided are a wafer level package and a wafer level packaging method, which are capable of performing an attaching process at a low temperature and preventing contamination of internal devices. In the wafer level package, a device substrate includes a device region, where a device is formed, and internal pads on the top surface. The internal pads are electrically connected to the device. A cap substrate includes a getter corresponding to the device on the bottom surface. A plurality of sealing/attaching members are provided between the device substrate and the cap substrate to attach the device substrate and the cap substrate and seal the device region and the getter. The sealing/attaching members are formed of polymer. A plurality of vias penetrate the cap substrate and are connected to the internal pads.

Abstract: A system and method for utilizing lead-free multi-core modules with organic substrates,including a base portion configured to attach a semiconductor chip;and a cap portion further comprising: a bottom portion configured to be sealed to the base portion;and a vacuum port;wherein when a vacuum is drawn at the vacuum port,a re-workable seal between the base portion and the cap portion is provided to enable rework.

Abstract: An electronic component package includes a dielectric substrate having a first surface where an electronic component is sealed. A first signal line connecting to the electronic component and a first ground conductor are formed on the first surface of the dielectric substrate. A second signal line connected to an outside connection electrode and a second ground conductor are formed on a second surface of the dielectric substrate. The first ground conductor and the second ground conductor are connected by a plurality of ground conductor via-holes. A substrate-buried signal line connected to the first signal line and the second signal line is provided inside of the dielectric substrate so as to be put between the first ground conductor and the second ground conductor above and below and between the ground conductor via-holes on the right and left.

Abstract: A micromechanical device assembly includes a micromechanical device enclosed within a processing region and a lubricant channel formed through an interior wall of the processing region and in fluid communication with the processing region. Lubricant is injected into the lubricant channel via capillary forces and held therein via surface tension of the lubricant against the internal surfaces of the lubrication channel. The lubricant channel containing the lubricant provides a ready supply of fresh lubricant to prevent stiction from occurring between interacting components of the micromechanical device disposed within the processing region.

Abstract: A system for cooling a semiconductor device is disclosed. The system includes a lid encasing the semiconductor device, a first plurality of carbon nanotubes disposed within the lid, and a fluid system configured to pass a fluid through the lid. Furthermore, a second system for cooling a semiconductor device is disclosed. The second system includes a lid, a first plurality of carbon nanotubes disposed within the lid, and a fluid system configured to pass a fluid through the lid. The lid is configured to be mounted over and encase the semiconductor device. Additionally, a method for cooling a semiconductor device is disclosed. The method includes disposing a first plurality of carbon nanotubes within a lid, mounting the lid over the semiconductor device, and passing a fluid through the lid.

Abstract: The invention discloses a subminiature electronic device with a hermetic cavity and method of manufacturing the same. It particularly relates to a chip type or chip scale packaged electronic device produced in substrate level. Firstly, a sacrificial layer is coated onto each of the identical microstructures disposed on a large substrate. A protective layer containing glass powders is then applied to encapsulate the sacrificial layer. Afterwards, the sacrificial layer is removed so as to form a cavity between the microstructure and the protective layer. The whole protective layer is then melted at elevated temperature to seal the cavity in an environment of specific gas. Finally, the large substrate is diced into a plurality of individual devices with a hermetic cavity over the microstructure. The applicable fields include micro-electronic circuits, micro-vibration systems, micro electrical-mechanical systems (MEMS), and gas discharge apparatuses.

Abstract: The invention provides methods for packaging for electronic devices that are light or other radiation-sensitive, such as image sensors including CCD or CMOS chips. In one embodiment of the invention, an image sensor package is assembled by surrounding a chip with a barrier of transfer mold compound and covering the chip with a transparent lid. In another embodiment of the invention, the perimeter area of a chip, including interconnections such as wire bonds and bond pads, is encapsulated with a liquid dispensed epoxy, and a transparent lid is attached. In yet another embodiment of the invention, chip encapsulation is accomplished with a unitary shell of entirely transparent material. In yet another embodiment of the invention, a substrate-mounted chip and a transparent lid are loaded into a transfer mold that holds them in optimal alignment. The transfer mold is then filled with molding compound.

Abstract: Provided herein are gettering members that include a monitor substrate and a conditioning layer thereon. Also provided herein are methods of forming gettering layers and methods of performing immersion lithography processes using the same.

Abstract: A semiconductor device with a structure having superior heat sink characteristics. A first heat sink member is located over a wiring board by using an adhesive material. A semiconductor element is stuck over the first heat sink member by using an adhesive material. The semiconductor element and electrodes located over the wiring board are connected by wires. A second heat sink member which covers the semiconductor element and the wires is joined to the first heat sink member by using a conductive adhesive material. The inside and outside of the second heat sink member are sealed by resin except a flat top thereof. By doing so, the semiconductor device is fabricated. Heat which is generated in the semiconductor element and which is transmitted to the first heat sink member is released from an edge portion of the first heat sink member.

Abstract: Methods for manufacturing microelectronic imaging units and microelectronic imaging units that are formed using such methods are disclosed herein. In one embodiment, a method includes providing a plurality of imaging dies on a microfeature workpiece. The individual imaging dies include an image sensor, an integrated circuit operably coupled to the image sensor, and a plurality of external contacts operably coupled to the integrated circuit. The method further includes attaching a plurality of covers to corresponding imaging dies, cutting the microfeature workpiece to singulate the imaging dies, and coupling the singulated dies to a support member. The covers can be attached to the imaging dies before or after the workpiece is cut.

Abstract: Embodiments of the present disclosure provide systems and methods for producing micro electro-mechanical device packages. Briefly described, in architecture, one embodiment of the system, among others, includes a micro electro-mechanical device formed on a substrate layer; and a thermally decomposable sacrificial structure protecting at least a portion of the micro electro-mechanical device, where the sacrificial structure is formed on the substrate layer and surrounds a gas cavity enclosing an active surface of the micro electro-mechanical device. Other systems and methods are also provided.

Abstract: A hermetic sealing cap member capable of suppressing deterioration of characteristics of an electronic component resulting from a sealant such as solder coming into contact with the electronic component in a package is obtained. This hermetic sealing cap, which is a hermetic sealing cap employed for an electronic component storing package for storing an electronic component (5, 34), comprises a hermetic sealing cap member (11, 41), a first plating layer (12, 42) formed at least on a region other than a region of the hermetic sealing cap member formed with a sealant (3, 32) and a second plating layer (13, 43), formed on the region of the hermetic sealing cap member on which the sealant is arranged, containing a material superior in wettability with the sealant to the first plating layer.