Abstract: A circuit module includes: a substrate including a wiring pattern; a first region in which a first electronic component is mounted on one major surface of the substrate; a second region in which a second electronic component, which is taller than the first electronic component, is mainly mounted on the one major surface of the substrate; a first conductor provided in the first region and electrically connected with the wiring pattern; and sealing resin that seals the first electronic component, the second electronic component, and the first conductor. Sealing resin sealing the first region is formed to be shorter than sealing resin sealing the second region, part of the first conductor is exposed on a surface of the sealing resin, wiring is formed on the surface of the sealing resin, and the first conductor the part of which is exposed is electrically connected with the wiring.

Abstract: In order to inhibit defective connection between a bump of a semiconductor chip and an electrode pad of a substrate, a semiconductor device includes a substrate provided on a surface with a plurality of electrode pads 15, a semiconductor chip 20 provided on a surface with a plurality of bumps 21 substantially equal in size, and an anisotropic conductive film 30 interposed between the plurality of bumps 21 and the plurality of electrode pads 15 and electrically connecting each of the bumps 21 and corresponding one of the electrode pads 15. The plurality of electrode pads 15 includes a plurality of first electrode pads 15A positioned closest to an end 25 of the semiconductor chip 20, and a plurality of second electrode pads 15B positioned inside the plurality of first electrode pads 15A on the semiconductor chip 20. Each of the second electrode pads 15B is larger in area than each of the first electrode pads 15A.

Abstract: A semiconductor package may include a first redistribution layer (RDL); a first semiconductor chip on a top surface of the first RDL, the first semiconductor chip including a first circuit surface and a first bottom surface, the first circuit surface having first I/O pads thereon, the first I/O pads configured to electrically connect the first semiconductor chip to the first RDL via first wire bonds; a second semiconductor chip on the first semiconductor chip, the second semiconductor chip including a second circuit surface and a second bottom surface; and a second RDL on the second semiconductor chip, the second RDL facing both the first circuit surface and the second circuit surface.

Abstract: In the present invention, an electrical connector is formed with contacts on one side of a printed circuit board that are electrically coupled through the board in a known manner. A backing plate formed of a dielectric material is applied to the board over the contacts. The backing plate includes openings extending through the backing plate that are in alignment with the contacts in order to allow electrical connections to be made with the contacts, but while also isolating the contacts from the exterior surface of the backing layer. The backing layer is affixed to the board over the contacts by an adhesive resin layer having an aperture cut into the layer. The aperture cut into the layer surrounds the contacts on the board, and due to the low or no flow nature of the resin, does not flow onto the contacts to cover the contacts.

Abstract: A display device made of a TFT substrate and a driver IC is configured to eliminate bad connection between them. On the driver IC connected to the TFT substrate, a first principal surface has first bumps formed along a first side having a first edge and second bumps formed along a second side opposite to the first side and having a second edge. The TFT substrate has first terminals and second terminals connected to the first and the second bumps, respectively. On a cross section taken perpendicularly to the first and the second sides, the first principal surface has a first area between the first and the second bumps and a second area between the second bumps and the second edge. The first and the second areas are bent toward the TFT substrate.

Abstract: A process of constructing a filled via of a printed circuit board comprises drilling a via hole through a body of the printed circuit board, desmearing a barrel of the via hole, metallizing a outer surface of the via barrel, electroplating the via barrel, pushing nano-copper solder into the via hole and heating the circuit board in order to melt the nano-copper solder within the via hole. The nano-copper solder improves the thermal conductivity of the printed circuit board for applications when heat needs to be conducted from one side of the printed circuit board to another.

Abstract: A copper foil composite comprising a copper foil and a resin layer laminated thereon, wherein equation 1: (f3×t3)/(f2×t2)=>1 is satisfied when t2 (mm) is a thickness of the copper foil, f2 (MPa) is a stress of the copper foil under tensile strain of 4%, t3 (mm) is a thickness of the resin layer, f3 (MPa) is a stress of the resin layer under tensile strain of 4%, and equation 2: 1<=33f1/(F×T) is satisfied when f1 (N/mm) is 180° peeling strength between the copper foil and the resin layer, F (MPa) is strength of the copper foil composite under tensile strain of 30%, and T (mm) is a thickness of the copper foil composite.

Abstract: A showcase member of a glass showcase, the showcase member including a first portion having a plurality of apertures, a light emitting diode (LED) module positioned at one or more of the plurality of apertures and mounted to the showcase member, and a wiring harness electrically connected to the LED module, and configured to electrically connect the LED module to an LED driver circuit. The showcase member can include a second portion integral to the first portion and having tapers forming light shields protruding from the showcase member.

Abstract: A multilayer ceramic capacitor may have low equivalent series inductance (ESL), in which via electrodes are opposed to each other diagonally and be off-centered from positions corresponding to center points of external electrodes, so that a distance between the via electrodes is significantly reduced and a current path is reduced.

Abstract: In one embodiment, a chip-on-lead package structures includes an electronic chip having opposing major surfaces. One major surface of the electronic chip is attached to first and second leads. The one major surface is electrically connected to the first lead, and electrically isolated from the second lead. The other major surface where active device are formed may be electrically connected to the second lead.

Abstract: Methods for bonding semiconductor wafers requiring the transfer of electrical and optical signals between the bonded wafers and across the bonding interface. The methods incorporate the formation of both electrical and optical interconnect vias within the wafer bonding interface to transfer electrical and optical signals between the bonded wafers. The electrical vias are formed using multiplicity of metal posts each comprised of multiple layers of metal that are interfused across the bonding surface. The optical vias are formed using multiplicity of optical waveguides each comprised of a dielectric material that interfuses across the bonding interface and having an index of refraction that is higher than the index of refraction of the dielectric intermediary bonding layer between the bonded wafers. The electrical and optical vias are interspersed across the bonding surface between the bonded wafers to enable uniform transfer of both electrical and optical signals between the bonded wafers.

Abstract: The film for back surface of flip-chip semiconductor according to the present invention is a film for back surface of flip-chip semiconductor to be formed on a back surface of a semiconductor element having been flip-chip connected onto an adherend, wherein a tensile storage elastic modulus at 23° C. after thermal curing is 10 GPa or more and not more than 50 GPa. According to the film for back surface of flip-chip semiconductor of the present invention, since it is formed on the back surface of a semiconductor element having been flip-chip connected onto an adherend, it fulfills a function to protect the semiconductor element. In addition, since the film for back surface of flip-chip semiconductor according to the present invention has a tensile storage elastic modulus at 23° C. after thermal curing of 10 GPa or more, a warp of the semiconductor element generated at the time of flip-chip connection of a semiconductor element onto an adherend can be effectively suppressed or prevented.

Abstract: A substrate includes a die-bonding zone and a glue spreading pattern. The die-bonding zone is set to bond a die. The glue spreading pattern is placed in the die-bonding zone and includes a containing space. The die is placed on the glue spreading pattern, an area of a bottom of the die is greater than an area of an opening of the glue spreading pattern, the containing room of the glue spreading pattern is filled with a glue, and the die is bonded to the substrate by means of the glue.

Abstract: An electronic device and fabrication of an electronic device. One embodiment provides applying a paste including electrically conductive particles to a surface of a semiconductor wafer. The semiconductor wafer is singulated with the electrically conductive particles for obtaining a plurality of semiconductor chips. At least one of the plurality of semiconductor chips is placed over a carrier with the electrically conductive particles facing the carrier. The electrically conductive particles are heated until the at least one semiconductor chip adheres to the carrier.

Abstract: A chip packaging apparatus includes a substrate, a load frame attached to the substrate by an adhesive material, the load frame being formed to define an aperture and a semiconductor chip mounted on the substrate within the aperture. A thickness of the adhesive material between the load frame and the substrate is varied and adjusted such that a surface of the load frame opposite the substrate is disposed substantially in parallel to a surface of the chip opposite the substrate.

Abstract: In one embodiment, a chip-on-lead package structures includes an electronic chip having opposing major surfaces. One major surface of the electronic chip is attached to first and second leads. The one major surface is electrically connected to the first lead, and electrically isolated from the second lead. The other major surface where active device are formed may be electrically connected to the second lead.

Abstract: An article of manufacture includes a semiconductor die (110) having an integrated circuit (105) on a first side of the die (110), a diffusion barrier (125) on a second side of the die (110) opposite the first side, a mat of carbon nanotubes (112) rooted to the diffusion barrier (125), a die attach adhesive (115) forming an integral mass with the mat (112) of the carbon nanotubes, and a die pad (120) adhering to the die attach adhesive and (115) and the mat (112) of carbon nanotubes for at least some thermal transfer between the die (110) and the die pad (120) via the carbon nanotubes (112). Other articles, integrated circuit devices, structures, and processes of manufacture, and assembly processes are also disclosed.

Abstract: The present invention relates to a resin paste composition including an organic compound, and a granular aluminum powder having an average particle diameter of from 2 to 10 ?m and a flake-shaped silver powder having an average particle diameter of from 1 to 5 ?m which are uniformly dispersed in the organic compound, and a semiconductor device manufactured by bonding a semiconductor element onto a supporting member through the resin paste composition and then encapsulating the resulting bonded product. According to the present invention, it is possible to provide a resin paste composition used for bonding an element such as semiconductor chips onto a lead frame which is excellent in not only electrical conductivity and bonding property but also working efficiency without using a large amount of rare and expensive silver, and a semiconductor device having a high productivity and a high reliability.

Abstract: Semiconductor dies are mounted on a heat sink array frame structure. The heat sink array frame structure and the semiconductor dies are assembled together with an insulating substrate that has a corresponding array of apertures on an adhesive tape. The semiconductor dies are connected electrically with electrical contacts on the insulating substrate. The semiconductor dies, heat sinks and electrical connections to the contacts are encapsulated with a mold compound and then the encapsulated array is de-taped and singulated.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a circuit substrate having an active side opposite to an inactive portion; attaching a nonconductive cover to the active side; forming a separation-gap partially cutting into the nonconductive cover and the circuit substrate to a kerf depth; attaching a back-grinding tape to the nonconductive cover; removing a portion of the inactive portion; and exposing the nonconductive cover by removing the back-grinding tape.

Abstract: A method of forming, on a surface of a substrate, at least one hydrophilic attachment area for the purpose of self-assembling a component or a chip, in which a hydrophobic area, which delimits the hydrophilic attachment area, is produced.

Abstract: A device includes a semiconductor material having a first surface. A first material is applied to the first surface and a fiber material is embedded in the first material.

Abstract: A method for manufacturing a chip package is provided. The method includes forming a layer over a carrier; forming further carrier material over the layer; selectively removing one or more portions of the further carrier material thereby releasing one or more portions of the layer from the further carrier material; and adhering a chip including one or more contact pads to the carrier via the layer.

Abstract: A semiconductor element mounting board includes: a board having surfaces; a semiconductor element provided at a side of one of the surfaces of the board; a bonding agent layer through which the board and the semiconductor element are bonded together, the bonding agent layer having a storage modulus at 25° C. of 5 to 1,000 MPa; a first layer into which the semiconductor element is embedded, the first layer provided on the one surface of the board; a second layer provided on the other surface of the board, the second layer being constituted from the same material as that of the first layer, the constituent material of the second layer having the same composition ratio as that of the constituent material of the first layer; and surface layers provided on the first and second layers, respectively, each of the surface layers being formed from at least a single layer.

Abstract: A semiconductor package that includes a conductive clip having an interior surface that includes a plurality of spaced raised portions, a semiconductor device having a first major surface that includes a plurality of spaced depressions each receiving one of the raised portions in the interior thereof, and a conductive adhesive disposed between each raised portion and a respective interior surface of a depression.

Abstract: An anisotropically conductive member has an insulating base material, and conductive paths composed of a conductive material which pass in a mutually insulated state through the insulating base material in a thickness direction thereof and which are provided in such a way that a first end of each conductive path is exposed on a first side of the insulating base material and a second end of each conductive path is exposed on a second side of the insulating base material. The conductive paths have a density of at least 2 million paths/mm2 and the insulating base material is a structure composed of an anodized aluminum film having micropores therein.

Abstract: A method and apparatus for forming a backside contact, electrical and/or thermal, for die encapsulated in a semiconductor device package are provided. Die of varying thicknesses can be accommodated within the semiconductor device package. Embodiments of the present invention provide a conductive pedestal coupled to a backside contact of a die, where the coupling is performed prior to encapsulating the die within the package. In addition, conductive pedestals coupled to varying die within a semiconductor device package are of such a thickness that each conductive pedestal can be exposed on the back side of the package without exposing or damaging the backside of any encapsulated die. Embodiments of the present invention provide for the conductive pedestals being made of electrically or thermally conductive material and coupled to the device die contact using an electrically and/or thermally conductive adhesive.

Abstract: The present invention provides a semiconductor device having a structure that can be mounted on a wiring substrate, as for the semiconductor device formed over a thin film-thickness substrate, a film-shaped substrate, or a sheet-like substrate. In addition, the present invention provides a method for manufacturing a semiconductor device that is capable of raising a reliability of mounting on a wiring substrate. One feature of the present invention is to bond a semiconductor element formed on a substrate having isolation to a member that a conductive film is formed via a medium having an anisotropic conductivity.

Abstract: In one embodiment, a chip-on-lead package structures includes an electronic chip having opposing major surfaces. One major surface of the electronic chip is attached to first and second leads. The one major surface is electrically connected to the first lead, and electrically isolated from the second lead. The other major surface where active device are formed may be electrically connected to the second lead.

Abstract: A method of forming a semiconductor device includes an integrated circuit (IC) die which is provided with a substrate with surfaces. At least one through substrate via (TSV) is formed through the substrate to a protruding integral tip that includes sidewalls and a distal end. A metal layer is formed on the bottom surface of the IC die, and the sidewalls and the distal end of the protruding integral tips. Completing fabrication of at least one functional circuit including at least one ground pad on the top surface of the semiconductor, wherein the ground pad is coupled to said TSV.

Abstract: A discrete semiconductor package includes a discrete semiconductor device disposed upon a non-conductive substrate, with via-connected upper and lower conductive ports. By utilizing a plurality of vias to connect the ports within the non-conductive substrate, and by depositing metals directly upon the surface of the substrate, manufacturing of such semiconductor packages is cheaper and more effective.

Abstract: A display device includes a substrate, a display region having pixels on the substrate, a drive circuit element mounted on a peripheral portion of the substrate, a plurality of terminal portions formed on the peripheral portion and arranged on a mounting portion of the drive circuit element, and a plurality of wiring lines prolonged from the terminal portions to the outside of the mounting portion of the substrate. The terminal parts are arranged to two lines of the plurality of wiring lines along one end of the mounting portion, a plurality of bumps connected to each of the terminal portions by an anisotropic conductive film are formed on the plane facing the terminal portion of the drive circuit element, a part of the plurality bumps include a first bump and a second bump which is adjoined close to the first bump.

Abstract: In one embodiment, a method includes attaching a film to cover a first portion of a first semiconductor die. The first semiconductor die is attached, using the tape, to a lead frame using a first bonding method. The first bonding method places the film between the lead frame and the semiconductor die. A second semiconductor die is attached to the lead frame using a second bonding method. The second bonding method bonds the lead frame and the semiconductor die. The first semiconductor device and the second semiconductor device are encapsulated into a semiconductor package.

Abstract: An assembly and method of making same are provided. The assembly can include a first component including a dielectric region having an exposed surface, a conductive pad at the surface defined by a conductive element having at least a portion extending in an oscillating or spiral path along the surface, and a an electrically conductive bonding material joined to the conductive pad and bridging an exposed portion of the dielectric surface between adjacent segments. The conductive pad can permit electrical interconnection of the first component with a second component having a terminal joined to the pad through the electrically conductive bonding material. The path of the conductive element may or may not overlap or cross itself.

Abstract: A silicon chip surface mounted via balls attached to its front surface, wherein the front and rear surfaces of the chip are covered with a thermosetting epoxy resin having the following characteristics: the resin contains a proportion ranging from 45 to 60% by weight of a load formed of carbon fiber particles with a maximum size of 20 ?m and with its largest portion having a diameter ranging between 2 and 8 ?m, on the front surface side, the loaded resin covers from 45 to 60% of the ball height, on the rear surface side, the loaded resin has a thickness ranging between 80 and 150 ?m.

Abstract: An integrated circuit packaging system and method of manufacture thereof includes: a substrate having a bond pad; a B-stage polymer, having a dispersion of conductive particles therein, on the bond pad; and a bond ball inserted into the B-stage polymer for forming intermetallic structures between the bond ball and the bond pad.

Abstract: The present invention enables improvement of bonding reliability of the conductive adhesive interposed between a semiconductor chip and a die pad portion. Provided is a semiconductor device, in which a silicon chip is mounted over the die pad portion integrally formed with a drain lead, has a source pad over the main surface and a drain electrode of a power MOSFET over the back side, and is bonded onto the die pad portion via an Ag paste. In the device, a source lead and the source pad are electrically coupled via an Al ribbon. Over the back surface of the silicon chip, an Ag nanoparticle coated film is formed, while another Ag nanoparticle coated film is formed over the die pad portion and lead (drain lead and source lead).

Abstract: A method of forming a semiconductor device includes an integrated circuit (IC) die which is provided with a substrate with surfaces. At least one through substrate via (TSV) is formed through the substrate to a protruding integral tip that includes sidewalls and a distal end. A metal layer is formed on the bottom surface of the IC die, and the sidewalls and the distal end of the protruding integral tips. Completing fabrication of at least one functional circuit including at least one ground pad on the top surface of the semiconductor, wherein the ground pad is coupled to said TSV.

Abstract: A method generates at least one electrical connection from at least one electronic component, which is positioned on a substrate inside an encapsulation, to outside the encapsulation. The functional capability of the electrical connection is to be provided at ambient temperatures greater than 140° C. and in the event of large power losses and extreme environmental influences. A reactive nanofilm, having targeted reaction, which can be triggered exothermically by laser, is used to produce hermetically sealed electrical connections. Using the nanofilm, an output of an electrical connection and a contact of the electrical connection to at least one further electrical contact can be provided.

Abstract: Devices and methods for electrical interconnection for microelectronic circuits are disclosed. One method of electrical interconnection includes forming a bundle of microfilaments, wherein at least two of the microfilaments include electrically conductive portions extending along their lengths. The method can also include bonding the microfilaments to corresponding bond pads of a microelectronic circuit substrate to form electrical connections between the electrically conductive portions and the corresponding bond pads. A microelectronic circuit can include a bundle of microfilaments bonded to corresponding bond pads to make electrical connection between corresponding bonds pads and electrically-conductive portions of the microfilaments.

Abstract: The present invention relates to an adhesive film, a dicing die bonding film and a semiconductor device. More specifically, the adhesive film of the present invention is characterized by comprising a base film and an adhesive layer and having a yield strength of 20 to 50 gf and a slope of tensile elastic region of 30 to 80 gf/mm at a thickness of 5 to 50 ?m. In the present adhesive film, the yield strength and the slope of tensile elastic region are controlled so that the incidence of burrs may be predicted and controlled depending on thickness of an adhesive layer. The dicing die bonding film, and the semiconductor device comprising the same have lower incidence of burrs and an excellent workability and reliability.

Abstract: A method of forming a microball grid array includes adhering a microball precursor material to a transfer medium under conditions to reflect a selective charge pattern. The method includes transferring the microball precursor material from the transfer medium across a gap and to an integrated circuit substrate under conditions to reflect the selective charge pattern. The method includes achieving the microball grid array without the aid of a mask.

Abstract: An assembly and method of making same are provided. The assembly can include a first component including a dielectric region having an exposed surface, a conductive pad at the surface defined by a conductive element having at least a portion extending in an oscillating or spiral path along the surface, and a an electrically conductive bonding material joined to the conductive pad and bridging an exposed portion of the dielectric surface between adjacent segments. The conductive pad can permit electrical interconnection of the first component with a second component having a terminal joined to the pad through the electrically conductive bonding material. The path of the conductive element may or may not overlap or cross itself.

Abstract: A method for assembling an optically pumped solid-state laser having an extended cavity. The method includes the steps of providing a casing, mounting a TEC and a base plate in the casing, and mounting a plurality of laser components on the base plate using a UV and heat curing adhesive. Once the laser components are correctly positioned and aligned on the base plate, the adhesive is pre-cured using UV radiation. Final curing of the adhesive is obtained by subjecting the entire laser package to an ambient temperature of at least 100° C. The base plate is preferably selected to have a CTE similar to that of the laser components in order to facilitate the high temperature curing. A preferred material for the base plate is AlSiC.

Abstract: In one or more embodiments, a method comprising applying thermo compression to a package assembly including a lid, a die, and a package substrate to assemble the package assembly is disclosed. The method may include assembling the package assembly without coupling a biasing mechanism to the lid. Heat may be applied to a bond head coupled with a pick and place tool. Heat may be applied to a bond stage coupled to a carrier for holding the package assembly during processing. An adhesive applied to the lid or package substrate may be allowed to at least partially cure. The method may further include, in an oven, reflowing a thermal interface material (TIM) coupled to the lid and the die, curing the TIM, and/or curing the adhesive, without using clips.

Abstract: A module having a discrete passive element and a semiconductor device, and method of forming the same. In one embodiment, the module includes a patterned leadframe, a discrete passive element mounted on an upper surface of the leadframe, and a thermally conductive, electrically insulating material formed on an upper surface of the discrete passive element. The module also includes a semiconductor device bonded to an upper surface of the thermally conductive, electrically insulating material.

Abstract: In fabrication of a semiconductor device mounted on a wiring board, a semiconductor circuit portion is formed over a glass substrate. Then, an interposer having connection terminals are bonded to the semiconductor circuit portion. After that, the glass substrate is peeled off from the semiconductor circuit portion, and a mold resin is poured to cover the periphery of the semiconductor circuit portion from a direction of the separation plane. Then, the mold resin is heated under predetermined conditions to be hardened.

Abstract: A system for bonding electrical devices using an electrically conductive adhesive to adhere the electrical devices together, the system comprising: an ultrasonic transducer to generate an ultrasonic vibration; and an ultrasonic to thermal energy apparatus operatively attached to and covering an operational end of the ultrasonic transducer, the ultrasonic to thermal energy apparatus damping the ultrasonic vibration to minimize ultrasonic vibration transmitted to a first electrical device and causing the conversion of the ultrasonic vibration to a heating pulse which is conducted through the first electrical device to the adhesive; wherein the adhesive is softened by the heating pulse to bond the electrical devices together.

Abstract: A thermal management configuration for a flip chip semiconductor device is disclosed. The device includes a high power silicon based die having a metal bonding surface. A plurality of interconnects are formed on the metal surface and connected to a substrate. A plurality of thermal management stud bumps are formed on the metal bonding surface, the thermal management stud bumps positioned distinct from the interconnects and local to die hot spots, exposed ends of the thermal management stud bumps spaced from the substrate.

Abstract: A wiring structure having a wiring-terminal-connection adhesive that includes a curing agent capable of generating a free radical upon heating, a radically polymerizable substance and silicone particles.