Involving Use Of Mechanical Auxiliary Part Without Use Of Alloying Or Soldering Process, E.g., Pressure Contacts (epo) Patents (Class 257/E21.515)
  • Patent number: 8912088
    Abstract: The present invention provides a transfer substrate for transferring a metal wiring material to a transfer-receiving object, the transfer substrate comprising a substrate, at least one metal wiring material formed on the substrate and an underlying metal film formed between the substrate and the metal wiring material, wherein the metal wiring material is a molded article prepared by sintering, e.g., gold powder having a purity of 99.9% by weight or more and an average particle size of 0.01 ?m to 1.0 ?m and the underlying metal film is composed of a metal such as gold or an alloy. The transfer substrate is capable of transferring a metal wiring material to the transfer-receiving object even at a temperature for heating the transfer-receiving object of 80 to 300° C.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: December 16, 2014
    Assignee: Tanaka Kikinzoku Kogyo K.K.
    Inventors: Toshinori Ogashiwa, Masaaki Kurita, Takashi Nishimori, Yukio Kanehira
  • Patent number: 8828841
    Abstract: A system and method for forming an isolation trench is provided. An embodiment comprises forming a trench and then lining the trench with a dielectric liner. Prior to etching the dielectric liner, an outgassing process is utilized to remove any residual precursor material that may be left over from the deposition of the dielectric liner. After the outgassing process, the dielectric liner may be etched, and the trench may be filled with a dielectric material.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: September 9, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Tang Peng, Bing-Hung Chen, Tze-Liang Lee, Hao-Ming Lien
  • Patent number: 8796724
    Abstract: This invention is about a reliable light-emitting system and a method to make it. The light-emitting system is mounted on a carrier with a non-conductive adhesive such that at least one of the p-contact layer and n-contact layer of the light-emitting device is in direct contact with conductive patterns formed on the carrier.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: August 5, 2014
    Inventors: Todd W Hodrinsky, Donald T Wesson, Jr., Deborah D Cebry, Matthew D Gidman, Robert M Sarazin
  • Patent number: 8604627
    Abstract: The present invention aims at providing a semiconductor device capable of reliably preventing a wire bonded to an island from being disconnected due to a thermal shock, a temperature cycle and the like in mounting and capable of preventing remarkable increase in the process time. In the semiconductor device according to the present invention, a semiconductor chip is die-bonded to the surface of an island, one end of a first wire is wire-bonded to an electrode formed on the surface of the semiconductor chip to form a first bonding section and the other end of the first wire is wire-bonded to the island to form a second bonding section, while the semiconductor device is resin-sealed. A double bonding section formed by wire-bonding a second wire is provided on the second bonding section of the first wire wire-bonded onto the island.
    Type: Grant
    Filed: April 14, 2006
    Date of Patent: December 10, 2013
    Assignee: Rohm Co., Ltd.
    Inventors: Hideki Hiromoto, Sadamasa Fujii, Tsunemori Yamaguchi
  • Patent number: 8581422
    Abstract: A semiconductor module includes a semiconductor device, a first conductive member, a second conductive member, a cylinder, and a cover. The first conductive member is in contact with a first electrode of the semiconductor device. The second conductive member is in contact with a second electrode of the semiconductor device. The cylinder encompasses the semiconductor device and is fixed to the first conductive member, and a first thread groove is formed on the cylinder. A second thread groove is formed on the cover. The cover is fixed to the cylinder by an engagement of the second thread groove with the first thread groove. The semiconductor device and the second conductive member are fixed by being sandwiched between the first conductive member and the cover. The second conductive member includes a portion extending from inside to outside the cylinder by penetrating an outer peripheral wall of the cylinder.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: November 12, 2013
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Masaki Aoshima
  • Patent number: 8569850
    Abstract: A sensor for acoustic applications such as a silicone microphone is provided containing a backplate provided with apertures and a flexible diaphragm formed from a silicon on insulator (SOI) wafer which includes a layer of heavily doped silicon, a layer of silicon and an intermediate oxide layer that is connected to, and insulated from the backplate. The arrangement of the diaphragm in relation to the rest of the sensor and the sensor location, being mounted over the aperture in a PCB, reduces the acoustic signal pathway which allows the sensor to be both thinner and more importantly, enables there to be a greater back volume.
    Type: Grant
    Filed: October 10, 2007
    Date of Patent: October 29, 2013
    Assignee: Sensfab Pte Ltd
    Inventors: Kitt-Wai Kok, Kok Meng Ong, Kathirgamasundaram Sooriakumar, Bryan Keith Patmon
  • Patent number: 8530345
    Abstract: An electronic apparatus and method of fabrication of the apparatus, the apparatus including a first electronic device having an interconnection surface with a first plurality of interconnection pads extending from the surface by a first distance and a second plurality of alignment posts extending from the surface by a second distance greater than the first distance, and a second electrical device having an interconnection surface with a first plurality of electrical interconnection pads, each pad arranged to contact a corresponding first electronic device interconnection surface pad upon assembly of the first electronic device interconnection surface upon the second electronic device interconnection surface, the second electronic device interconnection surface including a third plurality of alignment posts, each located to be adjacent to at least one of the first electronic device alignment posts upon assembly.
    Type: Grant
    Filed: February 12, 2013
    Date of Patent: September 10, 2013
    Assignee: International Business Machines Corporation
    Inventors: David Justin West, David John Russell
  • Patent number: 8524593
    Abstract: An apparatus and a process for the manufacture of a solder-bump adhered wafer substrate for use in the semiconductor industry, comprising one or more of the following steps including: arranging a first compressive member and a second compressive member in an opposed, compressibly displaceable, spaced-apart relationship, with a pattern plate disposed therebetween with the pattern plate having a plurality of aligned through-holes arranged thereon; filling the through-holes with a molten solder; compressing the solder and the pattern plate between the first and second opposed compressive members to compact the solder therein and cleans the pattern plate of excess solder; chilling the pattern plate to solidify the molten solder in the through-holes; and removing the pattern plate from the spaced-apart compressive members to produce a wafer with solder bumps thereon.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: September 3, 2013
    Assignee: Semigear Inc
    Inventors: Chunghsin Lee, Jian Zhang
  • Patent number: 8481366
    Abstract: A semiconductor device is provided that includes a semiconductor chip and a resin section that molds the semiconductor chip and has a first through-hole. A through electrode that is electrically coupled to the semiconductor chip, extends through the resin section, and extends between a top edge and a bottom edge of an inner surface of the first through-hole. A cavity which extends between planes corresponding to an upper surface and a lower surface of the resin section is formed inside the first through-hole.
    Type: Grant
    Filed: April 26, 2011
    Date of Patent: July 9, 2013
    Assignee: Spansion LLC
    Inventors: Masahiko Harayama, Kouichi Meguro, Junichi Kasai
  • Patent number: 8415792
    Abstract: An electronic apparatus and method of fabrication of the apparatus, the apparatus including a first electronic device having an interconnection surface with a first plurality of interconnection pads extending from the surface by a first distance and a second plurality of alignment posts extending from the surface by a second distance greater than the first distance, and a second electrical device having an interconnection surface with a first plurality of electrical interconnection pads, each pad arranged to contact a corresponding first electronic device interconnection surface pad upon assembly of the first electronic device interconnection surface upon the second electronic device interconnection surface, the second electronic device interconnection surface including a third plurality of alignment posts, each located to be adjacent to at least one of the first electronic device alignment posts upon assembly.
    Type: Grant
    Filed: August 4, 2010
    Date of Patent: April 9, 2013
    Assignee: International Business Machines Corporation
    Inventors: David Justin West, David John Russell
  • Patent number: 8389328
    Abstract: Provided is a method of manufacturing an electronic device having a first electronic component having a first terminal and a second electronic component having a second terminal, wherein the first electric component is electrically connected to the second electronic component by connecting the first terminal to the second terminal with solder, the method including: providing a resin layer having a flux action between the first terminal and the second terminal to obtain a laminate including the first electronic component, the second electronic component, and the resin layer, wherein a solder is provided on the first terminal or the second terminal; soldering the first terminal and the second terminal; and curing the resin layer while pressing the laminate with a pressurized fluid.
    Type: Grant
    Filed: October 30, 2009
    Date of Patent: March 5, 2013
    Assignee: Sumitomo Bakelite Co., Ltd.
    Inventors: Toru Meura, Kenzou Maejima, Yoji Ishimura, Mina Nikaido
  • Patent number: 8368207
    Abstract: A pressure-contact power semiconductor module is arranged on a heat sink. The power semiconductor module is used with at least one substrate provided with conductor tracks and power semiconductor components. The module has a mounting body, on the underside of which the at least one substrate is arranged, and which is formed with cutouts. The module also includes a load connection element which is provided with contact feet that project away from strip sections and make pressure contact with the conductor tracks. The power semiconductor module additionally has a dimensionally stable cover, which covers the mounting body on all sides and is connected to the mounting body by means of snap-action latching connections. At least one pad element is restrained between the cover and the strip sections of the load connection elements.
    Type: Grant
    Filed: April 4, 2008
    Date of Patent: February 5, 2013
    Assignee: Semikron Elektronik GmbH & Co., KG
    Inventors: Jürgen Steger, Frank Ebersberger
  • Patent number: 8278143
    Abstract: A manufacturing method for an electronic device joining a first metallic bond part formed on a first electronic component and a second metallic bond part formed on a second electronic component includes a first process for placing the first metallic bond part directly against the second metallic bond part, applying pressure to the first electronic component and the second electronic component, joining the first metallic bond part to the second metallic bond part with solid-phase diffusion, and releasing the applied pressure, and a second process for heating the first electronic component and the second electronic component at a predetermined temperature such that the first metallic bond part and the second metallic bond part are joined together by melting at least one of the first metallic bond part and the second metallic bond part.
    Type: Grant
    Filed: June 22, 2011
    Date of Patent: October 2, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Yoichiro Kurita
  • Patent number: 8193092
    Abstract: Semiconductor devices and methods of manufacturing semiconductor devices. One example of a method of fabricating a semiconductor device comprises forming a conductive feature extending through a semiconductor substrate such that the conductive feature has a first end and a second end opposite the first end, and wherein the second end projects outwardly from a surface of the substrate. The method can further include forming a dielectric layer over the surface of the substrate and the second end of the conductive feature such that the dielectric layer has an original thickness. The method can also include removing a portion of the dielectric layer to an intermediate depth less than the original thickness such that at least a portion of the second end of the conductive feature is exposed.
    Type: Grant
    Filed: July 31, 2007
    Date of Patent: June 5, 2012
    Assignee: Micron Technology, Inc.
    Inventor: David S. Pratt
  • Patent number: 8119427
    Abstract: In one aspect of the present invention, a method of LED die-bonding includes coating the back side of an LED chip with a magnetic material, placing the LED chip in a packaging cup such that the back side of the LED chip is in contact with the bottom of the packaging cup, applying a magnetic field in a region near the bottom of the packaging cup so as to exert a magnetic force on the LED chip via the magnetic material coated on the back side of the LED chip, thereby holding the LED chip in place against the bottom of the packaging cup, while the magnetic field is applied, bonding one end of a first conductive wire to an anode of the LED and the other end of the first conductive wire to a first electrode, and bonding one end of a second conductive wire to a cathode of the LED and the other end of the second conductive wire to a second electrode, where the first electrode and the second electrode are attached to the packaging cup, and filling the packaging cup with an epoxy, and curing the epoxy.
    Type: Grant
    Filed: January 6, 2011
    Date of Patent: February 21, 2012
    Assignee: Chi Mei Lighting Technology Corporation
    Inventor: Tsung-Hung Lu
  • Patent number: 7982320
    Abstract: An apparatus and a process for the manufacture of a solder-bump adhered wafer substrate for use in the semiconductor industry, comprising one or more of the following steps including: arranging a first compressive member and a second compressive member in an opposed, compressibly displaceable, spaced-apart relationship, with a pattern plate disposed therebetween with the pattern plate having a plurality of aligned through-holes arranged thereon; filling the through-holes with a molten solder; compressing the solder and the pattern plate between the first and second opposed compressive members to compact the solder therein and cleans the pattern plate of excess solder; chilling the pattern plate to solidify the molten solder in the through-holes; and removing the pattern plate from the spaced-apart compressive members to produce a wafer with solder bumps thereon.
    Type: Grant
    Filed: December 14, 2009
    Date of Patent: July 19, 2011
    Assignee: Semigear Inc.
    Inventors: Chunghsin Lee, Jian Zhang
  • Patent number: 7977158
    Abstract: A manufacturing method for an electronic device joining a first metallic bond part formed on a first electronic component and a second metallic bond part formed on a second electronic component includes a first process for placing the first metallic bond part directly against the second metallic bond part, applying pressure to the first electronic component and the second electronic component, joining the first metallic bond part to the second metallic bond part with solid-phase diffusion, and releasing the applied pressure, and a second process for heating the first electronic component and the second electronic component at a predetermined temperature such that the first metallic bond part and the second metallic bond part are joined together by melting the first metallic bond part and the second metallic bond part.
    Type: Grant
    Filed: July 8, 2010
    Date of Patent: July 12, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Yoichiro Kurita
  • Patent number: 7968907
    Abstract: An over-voltage protection thyristor has reduced junction capacitance making it suitable for use in high bandwidth applications. The reduced capacitance is achieved through the introduction of a deep base region. The deep base region has a graded doping concentration which reduces with depth into the substrate. The thyristor is useful for protecting sensitive electrical equipment from transient surges.
    Type: Grant
    Filed: December 9, 2008
    Date of Patent: June 28, 2011
    Assignee: Pan Jit Americas, Inc.
    Inventors: George Templeton, James Washburn
  • Patent number: 7829994
    Abstract: A reconfigurable high performance computer occupies less than 360 cubic inches and has an approximate compute power of 0.7 teraflops per second while consuming less than 1000 watts. The computer includes a novel stack of semiconductor substrate assemblies. Some semiconductor substrate assemblies involve field programmable gate array (FPGA) dice that are directly surface mounted, as bare die, to a semiconductor substrate. Other semiconductor substrate assemblies of the stack involve bare memory integrated circuit dice that are directly surface mounted to a semiconductor substrate. Elastomeric connectors interconnect adjacent semiconductor substrates proceeding down the stack. Tines of novel comb-shaped power bus bar assembly structures extend into the stack to supply DC supply voltages. The supply voltages are supplied from bus bars, through vias in the semiconductor substrates, and to the integrated circuits on the other side of the substrates.
    Type: Grant
    Filed: October 16, 2007
    Date of Patent: November 9, 2010
    Assignee: siXis, Inc.
    Inventor: Robert O. Conn
  • Patent number: 7816793
    Abstract: One embodiment of the present invention provides a system for facilitating proximity communication between semiconductor chips. The system includes a base chip and a bridge chip, each of which includes an active face upon which active circuitry and signal pads reside, and a back face opposite the active face. The active face of the bridge chip is bonded to the active face of the base chip. Then, an identified portion of the active face of the bridge chip is thinned via etching and is removed by planarizing the back face of the bridge chip, thereby creating an opening in the bridge chip that exposes a portion of the active face of the base chip.
    Type: Grant
    Filed: February 23, 2009
    Date of Patent: October 19, 2010
    Assignee: Oracle America, Inc.
    Inventors: Ashok V. Krishnamoorthy, John E. Cunningham
  • Patent number: 7772026
    Abstract: A micro electro-mechanical system (MEMS) device package and a method of manufacturing the same are provided.
    Type: Grant
    Filed: November 10, 2005
    Date of Patent: August 10, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-seok Kim, Yun-kwon Park, Kuang-woo Nam, Seok-chul Yun, In-sang Song
  • Patent number: 7772032
    Abstract: A manufacturing method for manufacturing an electronic device includes a first electronic component and a second electronic component; and a bond part for the first electronic component joined to another bond part for the second electronic component. In a first process of this manufacturing method, the metallic bond part for the first electronic component is placed directly against the metallic bond part for the second electronic component, pressure is applied to the first electronic component and the second electronic component and, after metallically joining the above two bond parts, the pressure applied to the first electronic component and the second electronic component is released. In a second process in the manufacturing method, a clamping member affixes the relative positions of the joined first electronic component and second electronic component, and heats the first electronic component and the second electronic component to maintain a specified temperature.
    Type: Grant
    Filed: November 18, 2008
    Date of Patent: August 10, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Yoichiro Kurita
  • Publication number: 20090302436
    Abstract: A shielded semiconductor device is made by mounting semiconductor die to a first substrate. An encapsulant is formed over the semiconductor die and first substrate. A dicing channel is formed through the encapsulant between the semiconductor die. A hole is drilled in the first substrate along the dicing channel on each side of the semiconductor die. A shielding layer is formed over the encapsulant and semiconductor die. The hole is lined with the shielding layer. The first substrate is singulated to separate the semiconductor die. The first substrate is mounted to a second substrate. A metal pillar is formed in the opening to electrically connect the shielding layer to a ground plane in the second substrate. The metal pillar includes a hook for a mechanically secure connection to the shielding layer. An interconnect structure is formed on the first substrate to electrically connect the semiconductor die to the second substrate.
    Type: Application
    Filed: June 10, 2008
    Publication date: December 10, 2009
    Applicant: STATS CHIPPAC, LTD.
    Inventors: OhHan Kim, SeungWon Kim, JoungUn Park
  • Publication number: 20090236721
    Abstract: A semiconductor device in accordance with one embodiment of the invention can include a substrate onto which a wiring pattern is formed. In addition, the semiconductor device can include a plurality of semiconductor packages. Each semiconductor package can include a lead frame that is coupled to an electrode of a semiconductor chip. Each lead frame can be located on a side surface and a bottom surface of the semiconductor package. In addition, the semiconductor device can include a pressure-contact section for receiving the plurality of semiconductor packages and for causing the plurality of semiconductor packages to come into contact with the wiring pattern.
    Type: Application
    Filed: September 19, 2008
    Publication date: September 24, 2009
    Inventor: Kouichi MEGURO
  • Publication number: 20090179315
    Abstract: Disclosed are spring structures that provide solderless electrical connections in semiconductor die packages. An exemplary spring structure comprises a first portion adapted to make an electrical connection to a conductive region of a semiconductor die, a second portion adapted to make an electrical connection to a conductive region of a leadframe, and a third portion disposed between the first and second portions. During a molding process, the third portion is compressively strained to impart forces to the first and second portions that maintain these portions in contact with the conductive regions of the die and leadframe. After the molding material sets, the third portion remains in a state of compressive strain, and imparts forces on the first and second portions that maintain the electrical connections. The spring structure may be made of less expensive materials, and does not require cleaning, fluxing, or reflowing, thereby reducing manufacturing cost and time.
    Type: Application
    Filed: January 14, 2008
    Publication date: July 16, 2009
    Inventor: Armand Vincent Jereza
  • Patent number: 7504330
    Abstract: A method of forming an insulative film includes a step of vacuum laminating an insulative organic material on a substrate that has a peripheral ring electrode formed in a peripheral region of the substrate and a device element(s) formed inside the peripheral region, and has a surface configuration including raised parts. A first dummy pattern is formed in a region between the peripheral ring electrode and the device element on the substrate.
    Type: Grant
    Filed: August 6, 2007
    Date of Patent: March 17, 2009
    Assignee: Fuji Electric Holdings Co., Ltd.
    Inventors: Takayuki Hirose, Masaharu Edo, Akira Sato
  • Patent number: 7208839
    Abstract: Methods relating to forming interconnects through injection of conductive materials, to fabricating semiconductor component assemblies, and to resulting assemblies. A semiconductor component substrate, such as a semiconductor die or other substrate, has dielectric material disposed on a surface thereof, surrounding but not covering interconnect elements, such as bond pads, on that surface. A second semiconductor component substrate, such as a carrier substrate with interconnect elements such as terminal pads, is adhered to the first semiconductor component substrate, forming a semiconductor package assembly having interconnect voids between the corresponding interconnect elements. A flowable conductive material is then injected into each interconnect void using an injection needle that passes through one of the substrates into the interconnect void, forming a conductive interconnect between the bond pads and terminal pads of the substrates.
    Type: Grant
    Filed: May 6, 2005
    Date of Patent: April 24, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Charles E. Larson
  • Patent number: 7109583
    Abstract: An electronic circuit can be produced by placing an electrically conductive compressible circuit bump on a circuit electrode of a mounting surface of first and second circuit devices, such as an integrated circuit and a base substrate. One or more auxiliary bumps can also be placed on one or both of the mounting surfaces of the circuit devices. During mounting, the first circuit device can be positioned over the second circuit device with the circuit bumps connecting circuit contacts on the two mounting surfaces. Pressure can be applied so that the circuit bumps and the auxiliary bumps are compressed between the chip and the base device sufficiently for adhering at least the circuit bumps to the circuit contacts.
    Type: Grant
    Filed: May 6, 2004
    Date of Patent: September 19, 2006
    Assignee: Endwave Corporation
    Inventor: Edwin F. Johnson
  • Patent number: 6975016
    Abstract: A three-dimensional (3-D) integrated chip system is provided with a first wafer including one or more integrated circuit (IC) devices; a second wafer including one or more integrated circuit (IC) devices; and a metal bonding layer deposited on opposing surfaces of the first and second wafers at designated locations to establish electrical connections between active IC devices on the first and second wafers and to provide metal bonding between the adjacent first and second wafers, when the first wafer is pressed against the second wafer using a flexible bladder press to account for height differences of the metal bonding layer across the opposing surfaces of the first and second wafers.
    Type: Grant
    Filed: February 6, 2002
    Date of Patent: December 13, 2005
    Assignee: Intel Corporation
    Inventors: Scot A. Kellar, Sarah E. Kim, R. Scott List