Involving Application Of Mechanical Vibration, E.g., Ultrasonic Vibration (epo) Patents (Class 257/E21.518)
  • Patent number: 10431514
    Abstract: One or more embodiments are directed to a semiconductor package that includes transparent encapsulation material and an opaque encapsulation material. In one embodiment, the opaque encapsulation material is thicker than the transparent encapsulation material; however, the outer surfaces of the opaque and the transparent encapsulation materials are coplanar with each other.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: October 1, 2019
    Assignee: STMicroelectronics (Malta) Ltd
    Inventors: David Bonnici, Brenda Farrugia
  • Patent number: 9966166
    Abstract: An electric wire and a shielding member configured to electrically shield the electric wire by enclosing an outer circumference thereof. A core wire of the electric wire has a single-core portion which is formed by applying pressure to a portion of a conductor obtained by twisting a plurality of strands together to reduce their cross section. This causes the strands to be brought into intimate contact with each other and form a single body, and a stranded wire portion in which the strands remain in a twisted-together state with no pressure having been applied thereto. The shielding member has a first shielding portion enclosing a portion of the electric wire where the core wire constitutes the single-core portion, and a second shielding portion enclosing a portion of the electric wire where the core wire constitutes the stranded wire portion. The second shielding portion has higher flexibility than the first shielding portion.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: May 8, 2018
    Assignee: Sumitomo Wiring Systems, Ltd.
    Inventor: Hirokazu Nakai
  • Patent number: 9859234
    Abstract: A method of processing an interconnection element can include providing a substrate element having front and rear opposite surfaces and electrically conductive structure, a first dielectric layer overlying the front surface and a plurality of conductive contacts at a first surface of the first dielectric layer, and a second dielectric layer overlying the rear surface and having a conductive element at a second surface of the second dielectric layer. The method can also include removing a portion of the second dielectric layer so as to reduce the thickness of the portion, and to provide a raised portion of the second dielectric layer having a first thickness and a lowered portion having a second thickness. The first thickness can be greater than the second thickness. At least a portion of the conductive element can be recessed below a height of the first thickness of the second dielectric layer.
    Type: Grant
    Filed: August 6, 2015
    Date of Patent: January 2, 2018
    Assignee: Invensas Corporation
    Inventors: Cyprian Emeka Uzoh, Guilian Gao, Bongsub Lee, Scott McGrath, Hong Shen, Charles G. Woychik, Arkalgud R. Sitaram, Akash Agrawal
  • Patent number: 9781828
    Abstract: A module substrate includes a plurality of electronic components mounted on at least one surface of a base substrate and a columnar terminal connection substrate connected to the one surface of the base substrate on which a plurality of the electronic components are mounted. The terminal connection substrate includes a plurality of conductor portions, at least one corner of the columnar terminal connection substrate is chamfered with a flat surface and/or curved surface, and the terminal connection substrate is connected at a side surface thereof contacting the chamfered surface, to the one surface of the base substrate.
    Type: Grant
    Filed: April 16, 2013
    Date of Patent: October 3, 2017
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Issei Yamamoto, Yoshihito Otsubo
  • Patent number: 9502371
    Abstract: A method of forming a wire interconnect structure includes the steps of: (a) forming a wire bond at a bonding location on a substrate using a wire bonding tool; (b) extending a length of wire, continuous with the wire bond, to another location; (c) pressing a portion of the length of wire against the other location using the wire bonding tool; (d) moving the wire bonding tool, and the pressed portion of the length of wire, to a position above the wire bond; and (e) separating the length of wire from a wire supply at the pressed portion, thereby providing a wire interconnect structure bonded to the bonding location.
    Type: Grant
    Filed: July 1, 2013
    Date of Patent: November 22, 2016
    Assignee: Kulicke and Soffa Industries, Inc.
    Inventors: Thomas J. Colosimo, Jr., Jon W. Brunner
  • Patent number: 9329422
    Abstract: A manufacturing method according to an embodiment of the present invention includes: a step of forming a tapered first groove on a surface of a semiconductor wafer; a step of forming a notch groove having a narrow width in a bottom portion of the first groove; a step of laminating the semiconductor wafer to a mother glass substrate using a sealing material; a step of forming a tapered second groove on a back surface of the semiconductor wafer; a step of separating a semiconductor substrate of the semiconductor wafer by cutting the semiconductor wafer from the second groove toward the notch groove; and a step of separating respective counter substrates by cutting the mother glass substrate along a scribe groove.
    Type: Grant
    Filed: February 25, 2015
    Date of Patent: May 3, 2016
    Assignee: JVC KENWOOD Corporation
    Inventor: Masato Sugihara
  • Patent number: 8907485
    Abstract: An integrated circuit wire bond connection is provided having an aluminum bond pad (51) that is directly bonded to a copper ball (52) to form an aluminum splash structure (53) and associated crevice opening (55) at a peripheral bond edge of the copper ball (54), where the aluminum splash structure (53) is characterized by a plurality of geometric properties indicative of a reliable copper ball bond, such as lateral splash size, splash shape, relative position of splash-ball crevice to the aluminum pad, crevice width, crevice length, crevice angle, and/or crevice-pad splash index.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: December 9, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Leo M. Higgins, III, Chu-Chung Lee
  • Patent number: 8796563
    Abstract: In ultrasonic bonding of a metal terminal to a substrate pad, a thin buffer metal layer which is formed of a soft metal or a highly slidable metal is interposed between a terminal edge and a pad so as to prevent direct contact between an end of the terminal and the pad upon bonding. This makes it possible to prevent abrasion and a crack in the pad at the end of the terminal caused by pressure and an ultrasonic wave upon the ultrasonic bonding. This makes it possible to realize a compact bonded structure with high reliability.
    Type: Grant
    Filed: January 29, 2010
    Date of Patent: August 5, 2014
    Assignee: Hitachi Automotive Systems, Ltd.
    Inventors: Ukyo Ikeda, Masato Nakamura, Shiro Yamashita
  • Patent number: 8772088
    Abstract: In a high frequency module, electronic components are mounted on a mounting surface of a collective substrate including a plurality of unit substrates that include a via conductor electrically conducted to a ground potential in a peripheral portion thereof, and the mounting surface and the electronic components are encapsulated with an encapsulation layer. The collective substrate is cut on the encapsulation layer side, thereby forming a half-cut groove penetrating through the encapsulation layer and extending halfway along the collective substrate in a thickness direction such that the via conductor is exposed only at a bottom surface of the half-cut groove. A conductive shield layer is formed to cover the encapsulation layer and is electrically conducted to the exposed via conductor. The collective substrate is then cut into individual unit substrates each including the conductive shield layer electrically conducted to the ground potential through the via conductor.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: July 8, 2014
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Takayuki Horibe
  • Patent number: 8729687
    Abstract: A stacked integrated circuit package-in-package system is provided including forming a first external interconnect; mounting a first integrated circuit die below the first external interconnect; stacking a second integrated circuit die over the first integrated circuit die in an offset configuration not over the first external interconnect; connecting the first integrated circuit die with the first external interconnect; and encapsulating the second integrated circuit die with the first external interconnect and the first integrated circuit die partially exposed.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: May 20, 2014
    Assignee: STATS ChipPac Ltd.
    Inventors: Hun Teak Lee, Tae Keun Lee, Soo Jung Park
  • Publication number: 20140054781
    Abstract: An integrated circuit wire bond connection is provided having an aluminum bond pad (51) that is directly bonded to a copper ball (52) to form an aluminum splash structure (53) and associated crevice opening (55) at a peripheral bond edge of the copper ball (54), where the aluminum splash structure (53) is characterized by a plurality of geometric properties indicative of a reliable copper ball bond, such as lateral splash size, splash shape, relative position of splash-ball crevice to the aluminum pad, crevice width, crevice length, crevice angle, and/or crevice-pad splash index.
    Type: Application
    Filed: August 24, 2012
    Publication date: February 27, 2014
    Inventors: Leo M. Higgins, III, Chu-Chung Lee
  • Patent number: 8609454
    Abstract: A self-assembly apparatus for assembling a plurality of devices with a predetermined aspect ratio is provided. The self-assembly apparatus includes a guiding element, a vibration device, and a magnetic field inducing device. The guiding element has a mesh structure. The vibration device is coupled to the guiding element and configured to vibrate the guiding element. The magnetic field inducing device is disposed below the guiding element and configured to generate a time-varying magnetic field to rotate each of the devices. Through a collective effect of the vibration of the guiding element, the time-varying magnetic field, and the self-gravity of each of the devices, the devices are positioned on a plate between the guiding element and the magnetic field inducing device through the mesh structure.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: December 17, 2013
    Assignee: Industrial Technology Research Institute
    Inventors: Ming-Ji Dai, Chun-Kai Liu, Heng-Chieh Chien, Li-Ling Liao, Ker-Win Wang, Yen-Lin Tzeng, Yan-Bo Lin
  • Patent number: 8604627
    Abstract: The present invention aims at providing a semiconductor device capable of reliably preventing a wire bonded to an island from being disconnected due to a thermal shock, a temperature cycle and the like in mounting and capable of preventing remarkable increase in the process time. In the semiconductor device according to the present invention, a semiconductor chip is die-bonded to the surface of an island, one end of a first wire is wire-bonded to an electrode formed on the surface of the semiconductor chip to form a first bonding section and the other end of the first wire is wire-bonded to the island to form a second bonding section, while the semiconductor device is resin-sealed. A double bonding section formed by wire-bonding a second wire is provided on the second bonding section of the first wire wire-bonded onto the island.
    Type: Grant
    Filed: April 14, 2006
    Date of Patent: December 10, 2013
    Assignee: Rohm Co., Ltd.
    Inventors: Hideki Hiromoto, Sadamasa Fujii, Tsunemori Yamaguchi
  • Patent number: 8581378
    Abstract: Terminals (2b, 2c) are divided into two along a common boundary, coatings (10, 11) most suitable for two conductive bonding materials (5, 6) to be used are exposed on the terminals (2b, 2c), the most suitable one of the coatings (10, 11) is selected, and the corresponding conductive bonding material (5, 6) is bonded onto the coating. Thus it is possible to improve the reliability of bonding and easily reduce a bonding resistance while suppressing a decrease in the reliability of a semiconductor element 3.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: November 12, 2013
    Assignee: Panasonic Corporation
    Inventors: Toshiyuki Yokoe, Chie Fujioka, Daichi Kumano
  • Patent number: 8569163
    Abstract: A risk of an electrical short between electrode pads of a semiconductor device can be reduced to thereby improve quality of the semiconductor device. During ball bonding in wire bonding, in each of the electrode pads of a semiconductor chip which are arrayed along an ultrasonic wave application direction (ultrasonic vibration direction), a ball at the tip of a copper wire and the electrode pad are coupled to each other while being rubbed against each other in a direction intersecting the ultrasonic wave application direction. Thus, the amount of AL splash formed on the electrode pad can be minimized to make the AL splash smaller. As a result, the quality of the semiconductor device assembled by the above-mentioned ball bonding can be improved.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: October 29, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Masahiko Sekihara, Takanori Okita
  • Patent number: 8569850
    Abstract: A sensor for acoustic applications such as a silicone microphone is provided containing a backplate provided with apertures and a flexible diaphragm formed from a silicon on insulator (SOI) wafer which includes a layer of heavily doped silicon, a layer of silicon and an intermediate oxide layer that is connected to, and insulated from the backplate. The arrangement of the diaphragm in relation to the rest of the sensor and the sensor location, being mounted over the aperture in a PCB, reduces the acoustic signal pathway which allows the sensor to be both thinner and more importantly, enables there to be a greater back volume.
    Type: Grant
    Filed: October 10, 2007
    Date of Patent: October 29, 2013
    Assignee: Sensfab Pte Ltd
    Inventors: Kitt-Wai Kok, Kok Meng Ong, Kathirgamasundaram Sooriakumar, Bryan Keith Patmon
  • Publication number: 20120329182
    Abstract: When metal junction between a first electrode and a second electrode is executed as ultrasonic bonding between metals including at least copper, the ultrasonic bonding is performed in a state that a contact interface between the first electrode and the second electrode is covered with a bonding auxiliary agent. As a result, formation of oxide at a bonding interface between the first electrode and the second electrode due to execution of the ultrasonic bonding can be suppressed. Therefore, while a desired bonding strength is ensured, ultrasonic bonding with copper used for the first electrode or the second electrode can be fulfilled and cost cuts in mounting of semiconductor devices can be achieved.
    Type: Application
    Filed: October 26, 2011
    Publication date: December 27, 2012
    Inventors: Teppei Kojio, Masashi Matsumori, Tadahiko Sakai, Takatoshi Ishikawa
  • Patent number: 8304874
    Abstract: A stacked integrated circuit package-in-package system is provided including forming a first external interconnect; mounting a first integrated circuit die below the first external interconnect; stacking a second integrated circuit die over the first integrated circuit die in an offset configuration not over the first external interconnect; connecting the first integrated circuit die with the first external interconnect; and encapsulating the second integrated circuit die with the first external interconnect and the first integrated circuit die partially exposed.
    Type: Grant
    Filed: December 9, 2006
    Date of Patent: November 6, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Hun Teak Lee, Tae Keun Lee, Soo Jung Park
  • Patent number: 8298947
    Abstract: A semiconductor device has a chip (101) with gold studs (212) assembled on a tape substrate (102), which has solder balls (103) for attachment to external parts. The tape substrate (about 30 to 70 ?m thick) has on its first surface first copper contact pads (221) covered with a continuous thin nickel layer (222) of about 0.04 to 0.12 ?m thickness. Gold including stud (212) is contacting the nickel. On the second substrate surface are second copper contact pads (231) covered with an alloy layer (about 2 to 3 ?m thick) including gold, copper/tin alloys, and copper/nickel/tin alloys; the alloys are metallurgically attached to the second copper pad and substantially free of unalloyed nickel. A reflow body (103) comprising tin is metallurgically attached to the alloy layer of each second pad.
    Type: Grant
    Filed: November 2, 2010
    Date of Patent: October 30, 2012
    Assignee: Texas Instruments Incorporated
    Inventor: Mutsumi Masumoto
  • Patent number: 8174101
    Abstract: Microelectronic devices, associated assemblies, and associated methods are disclosed herein. For example, certain aspects of the invention are directed toward a microelectronic device that includes a microfeature workpiece having a side and an aperture in the side. The device can further include a workpiece contact having a surface. At least a portion of the surface of the workpiece contact can be accessible through the aperture and through a passageway extending between the aperture and the surface. Other aspects of the invention are directed toward a microelectronic support device that includes a support member having a side carrying a support contact that can be connectable to a workpiece contact of a microfeature workpiece. The device can further include recessed support contact means carried by the support member. The recessed support contact means can be connectable to a second workpiece contact of the microfeature workpiece.
    Type: Grant
    Filed: September 1, 2005
    Date of Patent: May 8, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Teck Kheng Lee, David Yih Ming Chai, Hong Wan Ng
  • Patent number: 8129220
    Abstract: A system for bonding electrical devices using an electrically conductive adhesive to adhere the electrical devices together, the system comprising: an ultrasonic transducer to generate an ultrasonic vibration; and an ultrasonic to thermal energy apparatus operatively attached to and covering an operational end of the ultrasonic transducer, the ultrasonic to thermal energy apparatus damping the ultrasonic vibration to minimize ultrasonic vibration transmitted to a first electrical device and causing the conversion of the ultrasonic vibration to a heating pulse which is conducted through the first electrical device to the adhesive; wherein the adhesive is softened by the heating pulse to bond the electrical devices together.
    Type: Grant
    Filed: August 24, 2009
    Date of Patent: March 6, 2012
    Assignee: Hong Kong Polytechnic University
    Inventor: Derek Siu Wing Or
  • Publication number: 20110304031
    Abstract: Disclosed is a semiconductor device including a printed-circuit board which includes a plurality of first electrodes, a plurality of second electrodes and a semiconductor chip on which a plurality of first connection pads are aligned in a first line being disposed along an outer circumference side of a top surface and a plurality of second connection pads are aligned in a second line being disposed inside of and apart from the first line, when the semiconductor chip is seen from above, and any of the plurality of first connection pads are used for a power voltage terminal and a system reset terminal of the semiconductor device.
    Type: Application
    Filed: June 10, 2011
    Publication date: December 15, 2011
    Applicant: CASIO COMPUTER CO., LTD.
    Inventors: Teiji SHINDO, Shinji Ota
  • Patent number: 8058639
    Abstract: A light-emitting apparatus of the present invention includes: a mounting base 260 which has a wire 265; and a nitride-based semiconductor light-emitting device flip-chip mounted on the mounting base 260. The nitride-based semiconductor light-emitting device 100 includes a GaN-based substrate 10 which has an m-plane surface 12, a semiconductor multilayer structure 20 provided on the m-plane surface 12 of the GaN-based substrate 10, and an electrode 30 provided on the semiconductor multilayer structure 20. The electrode 30 includes an Mg layer 32. The Mg layer 32 is in contact with the surface of the p-type semiconductor region of the semiconductor multilayer structure 20. The electrode 30 is coupled to the wire 265.
    Type: Grant
    Filed: April 5, 2010
    Date of Patent: November 15, 2011
    Assignee: Panasonic Corporation
    Inventors: Akira Inoue, Masaki Fujikane, Toshiya Yokogawa
  • Patent number: 8049311
    Abstract: An electronic component includes a number of leads and at least one cooling element. The bottom surface of the cooling element is exposed and the material of the cooling element is different from the material of the leads. At least one semiconductor chip is provided on the cooling element. An encapsulation compound covers at least part of the leads, at least part of the semiconductor chip(s), and at least part of the cooling element(s).
    Type: Grant
    Filed: May 4, 2009
    Date of Patent: November 1, 2011
    Assignee: Infineon Technologies AG
    Inventors: Chee Chian Lim, Yoke Chin Goh, Koh Hoo Goh, May Ting Hng
  • Publication number: 20110163431
    Abstract: Retaining regions 310a and 310b are added to a pad shaped portion 303a of leads and a die pad 302 that are electrically connected via a conductive ribbon 309, so that during the bonding of the ribbon, strong ultrasonic waves can be applied in a state in which the retaining regions 310a and 310b are pressed and fixed. It is therefore possible to reduce a resistance at a joint while firmly bonding the conductive ribbon 309. Further, the bonding strength of the conductive ribbon 309 increases and thus it is possible to eliminate the need for stacking the conductive ribbons 309 and easily reduce a stress caused by ultrasonic waves on a semiconductor chip 306.
    Type: Application
    Filed: September 8, 2009
    Publication date: July 7, 2011
    Applicant: PANASONIC CORPORATION
    Inventors: Chie Fujioka, Toshiyuki Yokoe, Daichi Kumano
  • Publication number: 20110163392
    Abstract: By increasing the area of a source electrode 3a of a semiconductor element 3 and the area of a source terminal 2b of a lead frame 2, it is possible to extend a joint 8a of the source electrode 3a bonded to a conductive ribbon 6 and a joint 8b of the source terminal 2b. Thus it is possible to reduce an on resistance and easily reduce the number of times a bonding tool comes into contact with the joints to reduce a stress on the semiconductor element 3.
    Type: Application
    Filed: September 17, 2009
    Publication date: July 7, 2011
    Applicant: PANASONIC CORPORATION
    Inventors: Chie Fujioka, Toshiyuki Yokoe, Daichi Kumano
  • Publication number: 20110111561
    Abstract: Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods are disclosed. A system in accordance with a particular embodiment includes a first semiconductor substrate having a first substrate material, and a penetrating structure carried by the first semiconductor substrate. The system further includes a second semiconductor substrate having a second substrate material with a preformed recess. The penetrating structure of the first semiconductor substrate is received in the recess of the second semiconductor substrate and is mechanically engaged with the recess and secured to the second semiconductor substrate.
    Type: Application
    Filed: January 14, 2011
    Publication date: May 12, 2011
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Owen R. Fay, Warren M. Farnworth, David R. Hembree
  • Publication number: 20110045640
    Abstract: A system for bonding electrical devices using an electrically conductive adhesive to adhere the electrical devices together, the system comprising: an ultrasonic transducer to generate an ultrasonic vibration; and an ultrasonic to thermal energy apparatus operatively attached to and covering an operational end of the ultrasonic transducer, the ultrasonic to thermal energy apparatus damping the ultrasonic vibration to minimize ultrasonic vibration transmitted to a first electrical device and causing the conversion of the ultrasonic vibration to a heating pulse which is conducted through the first electrical device to the adhesive; wherein the adhesive is softened by the heating pulse to bond the electrical devices together.
    Type: Application
    Filed: August 24, 2009
    Publication date: February 24, 2011
    Inventor: Derek Siu Wing Or
  • Publication number: 20100323476
    Abstract: An ultrasonic bonding equipment for manufacturing a semiconductor device comprises a tip portion. The tip portion has a top surface which is faced to a member to be bonded, and propagates an ultrasonic vibration to the top surface. A plurality of protruding portions are provided on the top surface. Each of the protruding portions has: a first pair of opposite side surfaces inclined with respect to the top surface; and a second pair of opposite side surfaces substantially vertical to the top surface. A semiconductor device comprises: a semiconductor chip; a lead; and a bonding strap electrically connecting the semiconductor chip and the lead. A recess is formed on an upper surface of the bonding strap in at least one of a first region where the bonding strap and the semiconductor chip are connected and a second region where the bonding strap and the lead is connected.
    Type: Application
    Filed: August 10, 2010
    Publication date: December 23, 2010
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masataka NANBA, Shigeru Tanabe
  • Publication number: 20100264534
    Abstract: A chip package structure includes a circuit substrate, a chip, at least one bonding wire, and an adhesive layer. The circuit substrate has a bonding surface and at least one pad disposed on the bonding surface. The chip is disposed on the bonding surface of the circuit substrate and has an active surface away from the circuit substrate and at least one contact pad disposed on the active surface. The bonding wire is connected between the contact pad and the pad, such that the chip is electrically connected to the circuit substrate through the bonding wire. The bonding wire includes a copper layer, a nickel layer covering the copper layer, and a gold layer covering the nickel layer. The adhesive layer is disposed between the pad and the bonding wire and between the contact pad and the bonding wire and respectively covers two terminals of the bonding wire.
    Type: Application
    Filed: August 17, 2009
    Publication date: October 21, 2010
    Applicant: Unimicron Technology Corp.
    Inventor: Chung-Pan Wu
  • Publication number: 20100264531
    Abstract: The present invention includes a temporary fixing step of temporarily fixing a semiconductor element on an adherend interposing an adhesive sheet therebetween, a wire-bonding step of bonding wires to the semiconductor element, and a step of sealing the semiconductor element with a sealing resin, and in which the loss elastic modulus of the adhesive sheet at 175° C. is 2000 Pa or more.
    Type: Application
    Filed: July 2, 2010
    Publication date: October 21, 2010
    Inventors: Sadahito Misumi, Takeshi Matsumura, Kazuhito Hosokawa, Hiroyuki Kondo
  • Patent number: 7814645
    Abstract: A mounting apparatus applies ultrasonic vibration exactly to a junction between a SMD and a SMD receiving device and maintains the junction at the suitable temperature, in simple construction in ultrasonic bonding of the SMD and the SMD receiving device held by holding unit. This includes SMD holding unit, SMD receiving device holding unit, moving unit moving at least one of the SMD holding unit and SMD receiving device holding units to contact each other, vibration generating unit applying ultrasonic vibration to the a contact portion between the SMD and the SMD receiving device, pressing unit applying an bias force between the SMD and SMD receiving device, heating unit arranged movably so as to surround in a noncontact manner a portion of the SMD holding unit near the SMD and heating the SMD holding unit, and interlocking unit interlocking the heating unit with the SMD holding unit.
    Type: Grant
    Filed: July 18, 2008
    Date of Patent: October 19, 2010
    Assignee: TDK Corporation
    Inventors: Toru Mizuno, Tomomi Asakura, Yuji Saito, Hiroyuki Takano, Toshinobu Miyagoshi
  • Patent number: 7804160
    Abstract: An ultrasonic bonding equipment for manufacturing a semiconductor device comprises a tip portion. The tip portion has a top surface which is faced to a member to be bonded, and propagates an ultrasonic vibration to the top surface. A plurality of protruding portions are provided on the top surface. Each of the protruding portions has: a first pair of opposite side surfaces inclined with respect to the top surface; and a second pair of opposite side surfaces substantially vertical to the top surface. A semiconductor device comprises: a semiconductor chip; a lead; and a bonding strap electrically connecting the semiconductor chip and the lead. A recess is formed on an upper surface of the bonding strap in at least one of a first region where the bonding strap and the semiconductor chip are connected and a second region where the bonding strap and the lead is connected.
    Type: Grant
    Filed: November 8, 2005
    Date of Patent: September 28, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masataka Nanba, Shigeru Tanabe
  • Patent number: 7754529
    Abstract: In a flip chip mounted body in which a semiconductor chip (20) having a plurality of electrode terminals (21) is disposed so as to be opposed to a wiring board (10) having a plurality of connection terminals (11), with the connection terminals (11) and the electrode terminals (21) being connected electrically, a resin (13) containing electrically conductive particles (12) is supplied between the connection terminals (11) and the electrode terminals (21), the electrically conductive particles (12) and the resin (13) are heated and melted, and vibrations are applied so as to make them flow. The molten electrically conductive particles (12) are allowed to self-assemble between the connection terminals (11) and the electrode terminals (21), thereby forming connectors (22) that connect them electrically.
    Type: Grant
    Filed: February 2, 2006
    Date of Patent: July 13, 2010
    Assignee: Panasonic Corporation
    Inventors: Yoshihiro Tomita, Koichi Hirano, Seiji Karashima, Takashi Ichiryu, Toshio Fujii
  • Publication number: 20100167468
    Abstract: A method of manufacturing a semiconductor device includes a bonding step of bonding a chip on a wiring board by means of a bonding layer, and a wire bonding step of bonding a wire to a pad on the chip while applying ultrasonic vibration after the bonding step. A material having an elastic modulus of 100 MPa or higher at a process temperature in the wire bonding step is used as the bonding layer.
    Type: Application
    Filed: December 28, 2009
    Publication date: July 1, 2010
    Applicant: Renesas Technology Corp.
    Inventors: Hirohisa SHIMOKAWA, Naoki Izumi
  • Publication number: 20100051701
    Abstract: This invention provides a thin type of noncontact IC tag label that allows materials costs to be reduced without using an antenna-supporting base film. The noncontact IC tag label includes an electroconductive layer 6 of a required antenna pattern shape, an IC chip 3 mounted on one face of the electroconductive layer 6, and a surface protection sheet 4 supporting the electroconductive layer 6 and the IC chip 3 from a side of the one face of the electroconductive layer 6 via a first pressure-sensitive adhesive layer 5. An adhesive resin layer 7 having the same shape as the antenna pattern shape of the electroconductive layer 6 is provided on the other face of the electroconductive layer 6. The adhesive resin layer 7 is temporarily bonded in separable manner onto a release paper 9 formed from paper or a plastic base material.
    Type: Application
    Filed: October 16, 2007
    Publication date: March 4, 2010
    Applicant: Dai Nippon Printing Co., Ltd.
    Inventors: Tetsuji Ogata, Hideto Sakata
  • Publication number: 20100052133
    Abstract: A semiconductor device includes a plurality of semiconductor packages each with a semiconductor element and a flexible board. The flexible board is wider than the semiconductor element and is electrically connected to the semiconductor element. The plurality of semiconductor packages are stacked on one surface of a mother board. The semiconductor element is positioned between the flexible boards of the semiconductor packages in adjacent layers. The flexible boards in the adjacent layers are joined together at junction portions positioned at a part of the flexible boards which sticks out from an area in which the semiconductor elements and the flexible boards overlap. A reinforcing resin is provided in at least a part of the area between the flexible boards in the adjacent layers and between the junction portion of the flexible boards and the corresponding semiconductor element. The reinforcing resin contacts at least a part of the adjacent flexible board.
    Type: Application
    Filed: July 1, 2009
    Publication date: March 4, 2010
    Applicant: Elpida Memory, Inc.
    Inventors: Hisashi TANIE, Hiroshi Moriya, Masahiro Yamaguchi, Emi Sawayama
  • Patent number: 7635913
    Abstract: A stacked integrated circuit package-in-package system is provided including forming a substrate with a top contact, mounting a first device having a first terminal over the substrate, stacking a second device having a second terminal over the first device in an offset configuration, connecting the first terminal to the top contact below the first terminal, and connecting the second terminal to the top contact below the second terminal.
    Type: Grant
    Filed: December 9, 2006
    Date of Patent: December 22, 2009
    Assignee: Stats Chippac Ltd.
    Inventors: OhSug Kim, Jong-Woo Ha, Jong Wook Ju
  • Patent number: 7612429
    Abstract: A chip resistor (A1) comprises a first insulation layer (2A) covering the regions between a plurality of electrodes (3) on a rear surface (10a) of a resistor (1), and a second insulation layer covering a pair of side faces of the resistor (1). Inadvertent adhesion of solder to an improper part of the resistor (1) can thereby be eliminated. A solder layer (4) is preferably formed on a pair of end faces (10d) of the resistor (1). In so doing, a solder fillet can be formed appropriately.
    Type: Grant
    Filed: October 30, 2003
    Date of Patent: November 3, 2009
    Assignee: Rohm Co., Ltd.
    Inventors: Torayuki Tsukada, Tadatoshi Miwa
  • Publication number: 20090000107
    Abstract: A method is provided for producing a smart card comprising a chip module with at least one contacting area, the chip module arrangeable in a mounting location of a substrate, wherein one contacting loop is formed from a wire connector fed by a wire guiding unit for at least one of the contacting areas, respectively by attaching a first section of the wire conductor to a surface of the substrate outside the mounting location, wherein a second section of the wire conductor proximate to the first section is guided to form the contacting loop along with and protruding from the surface, wherein a subsequent third section of the wire conductor is attached to the surface outside the mounting location, wherein the chip module is inserted into the mounting location and wherein the second section is bent over and electrically contacted to the contacting area.
    Type: Application
    Filed: June 29, 2007
    Publication date: January 1, 2009
    Inventors: Matthias KOCH, Bernd GEBHARDT
  • Patent number: 7456091
    Abstract: A semiconductor device of the present invention includes a chip which has a pad; a bump electrode formed on the pad; and a wire whose stitch bonding is made on the bump electrode. The wire satisfies a condition: (modulus-of-elasticity/breaking strength per unit area) ?400.
    Type: Grant
    Filed: March 16, 2006
    Date of Patent: November 25, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Hidetoshi Kuraya, Hideyuki Arakawa, Fumiaki Aga
  • Publication number: 20080213945
    Abstract: A semiconductor device includes a mount substrate and a semiconductor chip mounted upon the mount substrate via a metal bump, wherein metal bump includes an inner part joined to the semiconductor chip and an outer part covering the inner part, the outer part having an increased hardness as compared with the inner part.
    Type: Application
    Filed: March 14, 2008
    Publication date: September 4, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Tomoyuki Abe, Shinya Iijima
  • Patent number: 7413935
    Abstract: A method of fabricating a semiconductor device includes hardening resin at a temperature that is less than or equal to the boiling point of the resin and until the hardening reaction ratio of the resin has reached at least 80%, the resin being disposed between a wiring board which has an interconnecting pattern and a semiconductor chip which has a plurality of electrodes and which is mounted on the wiring board in such a manner that the electrodes are in contact with the interconnecting pattern. A eutectic alloy joint is then formed between the electrodes and the interconnecting pattern.
    Type: Grant
    Filed: January 12, 2005
    Date of Patent: August 19, 2008
    Assignee: Seiko Epson Corporation
    Inventor: Takahiro Imai
  • Patent number: 7371661
    Abstract: A wafer bonding method, comprising steps of: coating a medium layer respectively on the surfaces of two wafers; removing impurities formed on the surface of each medium layer; laminating the two wafers while enabling the surface coated with the medium layer of one of the two wafers to face the surface coated with the medium layer of another wafer; and applying an ultra-sonic oscillation and a bonding pressure upon the laminated wafers for bonding the two wafers.
    Type: Grant
    Filed: May 12, 2006
    Date of Patent: May 13, 2008
    Assignee: Industrial Technology Research Institute
    Inventors: Chun-Hao Chang, Shih-Chieh Liao, Guo-Shing Huang, Wei-Yu Chen, Chuan-Sheng Zhuang
  • Publication number: 20070284738
    Abstract: A wiring board includes an insulating base; an adhesive layer formed on the surface of the insulating base; a conductor wiring formed on the surface of the adhesive layer; and a bump formed crossing the longitudinal direction of the conductor wiring over regions on the adhesive layer on both sides of the conductor wiring, wherein the back face at a part of the conductor wiring where the bump is formed, and the back faces and parts of the side faces of the bump formed above the regions of the adhesive layer on both sides of the conductor wiring, are embedded in the surface of the adhesive layer so as to be adhered to the adhesive layer. Even when the wiring width of the conductor wiring is decreased, the conductor wiring can be adhered to the wiring board firmly.
    Type: Application
    Filed: April 30, 2007
    Publication date: December 13, 2007
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Nozomi SHIMOISHIZAKA, Yoshifumi NAKAMURA
  • Patent number: 7294853
    Abstract: A substrate (1) is formed from a non-electrically conducting material and is for mounting a semiconductor chip (10). The substrate has a semiconductor chip mounting portion (6). A number of first electrically conducting contact portions (5) are formed on the surface of the material and associated with the mounting portion (6). A second electrically conducting contact portion (3) is formed on the surface of the material, and the second electrically conducting contact portion (3) is adapted to be coupled to testing equipment. A number of electrically conducting paths (4) are formed on the surface of the material. The conducting paths (4) electrically connect the second electrically conducting contact portion (3) to a minority of the first electrically conducting contact portions (5).
    Type: Grant
    Filed: April 6, 2001
    Date of Patent: November 13, 2007
    Assignee: Infineon Technologies, A.G.
    Inventor: Liang Kng Ian Koh
  • Patent number: 7241678
    Abstract: An integrated die bumping process includes providing a load board, defining a plurality of die regions on a surface of the load board for placing dice of a plurality of die specifications, affixing a plurality of dice respectively on the die regions according to the plurality of die specifications, and performing a die bumping process.
    Type: Grant
    Filed: January 6, 2005
    Date of Patent: July 10, 2007
    Assignee: United Microelectronics Corp.
    Inventors: Kai-Kuang Ho, Kuo-Ming Chen
  • Patent number: 7229854
    Abstract: A component mounting apparatus includes a component feeder (20) that feeds a component (2) with its bump electrodes facing down, a mounting head (5) that mounts the component onto a substrate (3), a supporting base (8) that secures the substrate, and a positioning device (6, 7) that aligns the component with the substrate. The mounting head includes an ultrasonic vibration generator (24), an ultrasonic vibration propagation member (34, 38, 54) that conveys the ultrasonic vibration provided by the ultrasonic vibration generator to a working face (33, 41, 57) holding the component as vibration parallel thereto, a pressure loader (22, 23, 39, 55, 59) that applies a pressure load to the working face from a position immediately thereabove in the direction perpendicular thereto, and a heater (32, 47, 49, 50, 51, 52, 53) that heats the vicinity of the working face. Thereby, ultrasonic bonding is carried out with high reliability even if the component has a number of bump electrodes (2a) on its face.
    Type: Grant
    Filed: March 27, 2003
    Date of Patent: June 12, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shozo Minamitani, Takaharu Mae, Yasuharu Ueno, Akira Yamada, Shinji Kanayama, Makoto Akita, Nobuhisa Watanabe, Akira Mori, Hiroyuki Naito, Shinya Marumo, Makoto Morikawa
  • Patent number: 7172958
    Abstract: A high-frequency wiring structure includes a microstrip line having a ground conductor, a dielectric disposed on the ground conductor, and a transmission conductor that is at least partially disposed in the dielectric. The transmission conductor is defined by a flat bottom parallel to the ground conductor, a pair of flat sides that are perpendicular to the ground conductor and are positioned on both sides of the flat bottom in the wiring width direction, and curved parts that continuously join the flat bottom and the pair of flat sides. The curved parts have a radius of curvature within the range of 5% to 50% of the thickness of the transmission conductor.
    Type: Grant
    Filed: February 2, 2005
    Date of Patent: February 6, 2007
    Assignee: ALPS Electric Co., Ltd.
    Inventor: Yorihiko Sasaki