Abstract: Representative implementations of devices and techniques provide correction for a defective die in a wafer-to-wafer stack or a die stack. A correction die is coupled to a die of the stack with the defective die. The correction die electrically replaces the defective die. Optionally, a dummy die can be coupled to other die stacks of a wafer-to-wafer stack to adjust a height of the stacks.

Abstract: In one embodiment, systems and methods include using a Langmuir probe to measure a plasma. The Langmuir probe comprises a housing, wherein the housing comprises an outer diameter and an inner diameter, wherein the inner diameter defines an internal cavity. The Langmuir probe further comprises a plurality of bodies, wherein the plurality of bodies is disposed at least partially within the inner cavity, wherein each of the plurality of bodies comprise a set of internal cavities. The Langmuir probe further comprises a plurality of double Langmuir probes disposed each set of the internal cavities.

Abstract: A semiconductor package includes multiple dies that share the same package pin. An output enable register provided on each die is used to select the die that drives an output to the shared pin. A hardware arbitration circuit ensures that two or more dies do not drive an output to the shared pin at the same time.

Abstract: A package substrate film including a film substrate including upper and lower surfaces; a test pattern including an upper test line pattern extending on the upper surface of the film substrate; a lower test line pattern extending on the lower surface of the film substrate; a first test via pattern penetrating the film substrate and connecting the upper test line pattern to the lower test line pattern; a second test via pattern penetrating the film substrate outside the first test via pattern and connecting the upper test line pattern to the lower test line pattern; and a test pad between the first test via pattern and the second test via pattern, the test pad including first test pad at an outer side of the first test via pattern; and second test pad at an inner side of the second test via pattern and facing the first test pad.

Abstract: A method of fabricating an integrated circuit is disclosed. The method comprises defining a multi-layer semiconductor device structure on a substrate using standard cells, defining an input port on the M0OD or PO layer of the semiconductor device structure and an output port on the M0OD layer, and defining a metal-1 layer over the M0OD and PO layers, the metal-1 layer having a first set of conduction paths and a second set of conduction paths. The method further comprises defining a metal-2 layer over the metal-1 layer and configuring the first set of metal-1 conduction paths and the metal-2 conduction paths to interconnect circuit components in different cells, wherein inter cell connections in the semiconductor device structure are made using the first set of metal-1 conduction paths or a combination of the first set of metal-1 and the metal-2 conduction paths.

Abstract: A wafer manufacturing method includes a wafer preparing step of preparing a wafer including a semiconductor device formed in each of a plurality of regions demarcated by a plurality of streets intersecting each other, a removing step of separating, from the wafer, a defective device region including a semiconductor device determined to be a defective product among a plurality of the semiconductor devices formed in the wafer, and a fitting step of fitting, into a through hole formed by separating the defective device region from the wafer, a device chip including a semiconductor device as a non-defective product having same functions as those of the semiconductor device determined to be a defective product and having a size capable of being fitted into the through hole.

Abstract: A semiconductor device includes a first die connected to a first channel, the first die comprising a first memory chip; and a second die connected to a second channel, the second die comprising a second memory chip, the first and second channels being independent of each other and a storage capacity and a physical size of the second die being the same as those of the first die. The first and second dies are disposed in one package, and the package includes an interconnection circuit disposed between the first die and the second die to transfer signals between the first memory chip and the second memory chip.

Abstract: A wafer manufacturing method includes a wafer preparing step of preparing a wafer including a semiconductor device formed in each of a plurality of regions demarcated by a plurality of streets intersecting each other, a removing step of removing, from the wafer, a defective device region including a semiconductor device determined to be a defective product among a plurality of the semiconductor devices formed in the wafer, and a fitting step of fitting, into a removed region formed by removing the defective device region from the wafer, a device chip including a semiconductor device as a non-defective product having same functions as those of the semiconductor device determined to be a defective product and having a size capable of being fitted into the removed region.

Abstract: Embodiments include semiconductor packages. A semiconductor package includes a plurality of dies on a package substrate, and a plurality of smart dies on the package substrate, where the plurality of smart dies include a plurality of interconnects and a plurality of capacitors. The semiconductor package also includes a plurality of routing lines coupled to the dies and the smart dies, where the routing lines are communicatively coupled to the interconnects of the smart dies, where each of the dies has at least two or more routing lines to communicatively couple the dies together, and where one of the routing lines is via the interconnects of the smart dies. The capacitors may be a plurality of metal-insulator-metal (MIM) capacitors. The dies may be a plurality of active dies. The routing lines may communicatively couple first and second active dies to first and second smart dies.

Abstract: The present disclosure provides a semiconductor structure having a test structure. The semiconductor structure includes a semiconductor substrate, a memory device and a test structure. The memory device is disposed on the semiconductor substrate, and includes a device area and an edge area. The edge area surrounds the device area. The test structure is disposed on the semiconductor substrate, and includes a dummy area, a test edge area and a plurality of unit cells. The test edge area surrounds the dummy area. The plurality of unit cells are disposed in the test edge area, and the dummy area is free of the unit cells. A dimension of the test edge area in a top view is different from a dimension of the edge area in the top view.

Abstract: A chip testing apparatus and system suitable for performing testing on multiple chips in a chip cluster are provided. The chip testing apparatus includes a signal interface and a test design circuit. The signal interface transmits an input signal and multiple driving signals in parallel from a test equipment to each of the chips. The test design circuit receives multiple output signals from the chips through the signal interface and serially outputs a test data to the test equipment according to the output signals.

Abstract: Representative implementations of devices and techniques provide correction for a defective die in a wafer-to-wafer stack or a die stack. A correction die is coupled to a die of the stack with the defective die. The correction die electrically replaces the defective die. Optionally, a dummy die can be coupled to other die stacks of a wafer-to-wafer stack to adjust a height of the stacks.

Abstract: The present disclosure provides a semiconductor structure having a test structure. The semiconductor structure includes a semiconductor substrate, a memory device and a test structure. The memory device is disposed on the semiconductor substrate, and includes a device area and an edge area. The edge area surrounds the device area. The test structure is disposed on the semiconductor substrate, and includes a dummy area, a test edge area and a plurality of unit cells. The test edge area surrounds the dummy area. The unit cells have a first group disposed in the dummy area and a second group disposed in the test edge area. The second group of unit cells includes the outermost unit cells of the plurality of unit cells. A shape surrounded by the edge area in a top view is different from a shape surrounded by the test edge area in the top view.

Abstract: A method includes: providing a first substrate on which a plurality of first semiconductor devices is formed; providing a second substrate on which a plurality of second semiconductor devices is formed; and coupling the first and second substrates by contacting respective dummy pads of the first and second substrates, wherein at least one of the dummy pads of the first and second substrates comprises plural peaks and valleys.

Abstract: A system to test a PLL circuit driven by a reference clock includes a first counter coupled to a reference clock output, a first buffer coupled to the first counter, a second counter coupled to a controlled-oscillator (CO) output of the PLL circuit, a second buffer coupled to the second counter, and a processor configured to compute a PLL lock time according to second count values in the second buffer, and to compute a PLL startup slope according to the first count values in the first buffer and the second count values in the second buffer. A method includes powering up a PLL circuit of a wafer, sampling count values of a reference clock and second count values of the PLL circuit and computing a PLL performance parameter according to the sampled count values in a buffer.

Abstract: A semiconductor package includes a buffer wafer including: a first surface; and a second surface opposite to the first surface, a stacked structure including a plurality of chips being stacked on the first surface of the buffer wafer; a first detection line formed around a periphery of the stacked structure on the first surface of the buffer wafer; and a mold layer covering the stacked structure, the first detection line and the first surface of the buffer wafer.

Abstract: A method for determining redundancy usage rate from a group of memory parameters and a memory yield of a System on a Chip (SoC), using the probabilistic redundancy usage rate and using that rate to calculate an optimal RSMA size. An SoC is then fabricated with the optimal RSMA size.

Abstract: A method includes: providing a first substrate on which a plurality of first semiconductor devices is formed; providing a second substrate on which a plurality of second semiconductor devices is formed; and coupling the first and second substrates by contacting respective dummy pads of the first and second substrates, wherein at least one of the dummy pads of the first and second substrates comprises plural peaks and valleys.

Abstract: A test socket of a flexible semiconductor chip package includes a first bending jig having a convex contour, a second bending jig having a concave contour, and a semiconductor chip package. The second bending jig is disposed to matingly engage the first bending jig. The semiconductor chip package is disposed between the first bending jig and the second bending jig, and includes a flexible tape and a semiconductor chip. The semiconductor chip is disposed on a surface of the flexible tape. Each of the first and second bending jigs has a horizontal length longer than a length of the semiconductor chip and less than a length of the flexible tape.

Abstract: Systems and methods for utilizing a defect map to configure an automata processor in order to avoid defects when configuring the automata processor. A system includes automata processor having a state machine lattice. The system also includes a non-volatile memory having a defect map stored thereon and indicating logical defects found on the automata processor. By including the defect map, a compiler may access the defect map to map out defects in the automata processor during configuring to avoid such defects.

Abstract: Physical synthesis for a circuit design can include determining, using a processor, a candidate net from a circuit design, wherein the candidate net spans a plurality of dies of a multi-die integrated circuit, and modifying, using the processor, the candidate net by performing physical synthesis resulting in a modified candidate net. The physical synthesis includes relocating a driver or a load of the candidate net or replicating the driver of the candidate net. An incremental routing can be performed on the modified candidate net using the processor. Further, the modified candidate net can be selectively committed using the processor based upon a timing analysis.

Abstract: A test probe head for probe testing multiple chips on a wafer in a single probing. A probe head substrate includes an array of probe tip attach pads on one surface. The array includes a subarray for each probe head chip test site. Probe tips attached to each probe tip attach pad have an across the head tip height variation less than one micrometer (1 ?m). The subarray probe tips may be on a pitch at or less than fifty microns (50 ?m). The test probe head may be capable of test probing all chips in a quadrant and even up to all chips on a single wafer in a single probing.

Abstract: Provided is a semiconductor device including chip identification (ID) generation circuits. The semiconductor device may be a multi-chip package including a plurality of memory chips, and each of the memory chips includes a chip ID generation circuit configured to selectively modify a chip ID of a corresponding memory chip. The chip ID generation circuit determines the chip ID of the memory chip by testing the chip ID of the memory chip by using a mode register, and selectively programs the chip ID of the memory chip by using at least two fuse sets. The chip ID generation circuit may block an output of the chip ID of the memory chip when the memory chip is determined as a defective chip or is selected to stop its use.

Abstract: Systems and methods for utilizing a defect map to configure an automata processor in order to avoid defects when configuring the automata processor. A system includes automata processor having a state machine lattice. The system also includes a non-volatile memory having a defect map stored thereon and indicating logical defects found on the automata processor. By including the defect map, a compiler accesses the defect map to map out defects in the automata processor during configuring to avoid such defects.

Abstract: Technology is described for selectively disconnecting a communal module (e.g., horizontal power and signal distribution network) from conductive traces (e.g., vertical columns) that are coupled to cell elements. In one example, a matrix type integrated circuit includes a two dimensional (2D) array of cell elements, a plurality of conductive traces, a communal module, and a plurality of switches. Each cell element in the 2D array provides a similar function. The plurality of conductive traces is substantially parallel to a first axis of the 2D array. Each conductive trace is coupled to a conductive interconnect of cell elements adjacent to the conductive trace. The communal module is configured to provide distribution of at least one electrical signal to the cell elements in the 2D array via at least two conductive traces that are substantially parallel to the first axis.

Abstract: A wafer-level method for fabricating a plurality of cameras includes modifying an image sensor wafer to reduce risk of the image sensor wafer warping, and bonding the image sensor wafer to a lens wafer to form a composite wafer that includes the plurality of cameras. A wafer-level method for fabricating a plurality of cameras includes bonding an image sensor wafer to a lens wafer, using a pressure sensitive adhesive, to form a composite wafer that includes the plurality of cameras.

Abstract: A tester configured to test a strip of devices is provided. The tester may include a communications system, a plurality of communication lines, a plurality of multiplexors, each multiplexor having at least two outputs, wherein each multiplexor is configured to receive a signal generated by the communications system via one of the plurality of communication lines, and each multiplexor may be selectably coupled to at least two of the devices in the strip of devices. The tester may be configured to index the plurality of communication lines to a first subset of the devices, initiate at least one test, command the devices to generate data for each of the at least one tests, retrieve data from a first set of the devices, and retrieve data from a second set of the devices.

Abstract: A method for fabricating a finFET device having an insulating layer that insulates the fin from a substrate is described. The insulating layer can prevent leakage current that would otherwise flow through bulk semiconductor material in the substrate. The structure may be fabricated starting with a bulk semiconductor substrate, without the need for a semiconductor-on-insulator substrate. Fin structures may be formed by epitaxial growth, which can improve the uniformity of fin heights in the devices.

Abstract: In a testing method for an LD, an LD die is held. Then, electric current increasing with a fixed increment and having a sequence of current values is supplied to the LD die to drive the LD die to emit light and a sequence of voltage values across the LD die and corresponding to the sequence of current values, respectively, is metered. A sequence of power values corresponding to the sequence of current values, respectively, is also metered. Next, an electro-optical property of the LD die is determined according to the sequence of current values, the sequence of voltage values, and the sequence of power values. Finally, if the LD die is determined to be qualified based upon the electro-optical property of the LD die, the LD die is packaged into the LD.

Abstract: A chip is layered on a rewiring member. A plurality of connecting members and a plurality of redundant connecting members are arranged in the chip, and electrically connect the chip to the rewiring member. Redundant circuits are embedded in each of the rewiring member and the chip. When one of the connecting members is faulty, the redundant circuits cause one of the redundant connecting members to transmit a signal between the rewiring member and the chip, instead of the faulty connecting member. The connecting members have first and second subsets arranged in first and second regions, respectively. A distance between the rewiring member and the chip exceeds a predetermined threshold value in the first region in contrast to the second region. The first subset has a higher proportion of connecting members that the redundant circuits can replace with a subset of the redundant connecting members than the second subset.

Abstract: A stacked semiconductor chip comprising multiple unit chips contains multiple instances of a first chip component that have a low yield and are distributed among the multiple unit chips. An instance of the first chip component within a first unit chip is logically paired with at least another instance of the first chip component within at least another unit chip so that the combination of the multiple instances of the first chip component across the multiple unit chips constitute a functional block providing the functionality of a fully functional instance of the first chip component. The stacked semiconductor chip may include multiple instances of a second chip component having a high yield and distributed across the multiple unit chips. Multiple low yield components constitute a functional block providing an enhanced overall yield, while high yield components are utilized to their full potential functionality.

Abstract: At least one MOS parameter of a MOS fuse is characterized to provide at least one MOS parameter reference value. Then, the MOS fuse is programmed by applying a programming signal to the fuse terminals so that programming current flows through the fuse link. The fuse resistance is measured to provide a measured fuse resistance associated with a first logic value. A MOS parameter of the programmed MOS fuse is measured to provide a measured MOS parameter value. The measured MOS parameter value is compared to the reference MOS parameter value to determine a second logic value of the MOS fuse, and a bit value is output based on the comparison.

Abstract: In a testing method for an LD, an LD die is held. Then, electric current increasing with a fixed increment and having a sequence of current values is supplied to the LD die to drive the LD die to emit light and a sequence of voltage values across the LD die and corresponding to the sequence of current values, respectively, is metered. A sequence of power values corresponding to the sequence of current values, respectively, is also metered. Next, an electro-optical property of the LD die is determined according to the sequence of current values, the sequence of voltage values, and the sequence of power values. Finally, if the LD die is determined to be qualified based upon the electro-optical property of the LD die, the LD die is packaged into the LD.

Abstract: A method of manufacturing a layered chip package that includes a main body, and wiring disposed on a side surface of the main body. The main body includes a plurality of layer portions. The method includes fabricating a plurality of substructures, and completing the layered chip package by fabricating the main body using the plurality of substructures and by forming the wiring on the main body.

Abstract: A wafer containing a plurality of electro-optical devices, each device being enclosed in chamber that has a translucent cover. An X-Y matrix of pairs of interconnections on the wafer are connected to the circuitry of the electro-optical devices for addressing the electro-optical devices. The pairs of interconnections extend outside of the chambers enclosing the devices to testing areas on the periphery of the wafer. Testing is done by signals applied through the interconnections while simultaneously exposing the devices to light through the translucent covers.

Abstract: Methods for manufacturing a light source circuit board having one or more light emitting components that include providing at least one circuit component on a light source circuit board, wherein the at least one circuit component has an electrical circuit constant that specifies one or more performance parameters for the light source. The methods also include measuring the electrical circuit constant of the at least one circuit component. The methods also include identifying one or more performance parameters for the light source based on the measured electrical constant.

Abstract: A semiconductor device in one embodiment includes a wiring board having a wiring pattern; an N semiconductor elements(where N denotes a natural number equal to or greater than 2) mounted on a wiring board; and a current detection parts for detecting a current flowing through m semiconductor elements (where m denotes a natural number equal to or greater than 1 but less than M) of M semiconductor elements(where M denotes a natural number equal to or greater than 1 but equal to or less than N) mounted on the wiring board and selected from the N semiconductor elements. The M semiconductor elements are electrically connected in parallel through the wiring pattern, and the m semiconductor elements are electrically connected in parallel to the other semiconductor elements of the M semiconductor elements through the current detection part.

Abstract: To provide improved planarization, techniques in accordance with this disclosure include a CMP station that utilizes localized planarization on a wafer. This localized planarization, which is often carried out in a localized planarization station downstream of a CMP station, applies localized planarization to less than the entire face of the wafer to correct localized non-planar features. Other systems and methods are also disclosed.

Abstract: Methods and apparatus for detecting errors in real time in CMP processing. A method includes disposing a semiconductor wafer onto a wafer carrier in a tool for chemical mechanical polishing (“CMP”); positioning the wafer carrier so that a surface of the semiconductor wafer contacts a polishing pad mounted on a rotating platen; dispensing an abrasive slurry onto the rotating polishing pad while maintaining the surface of the semiconductor wafer in contact with the polishing pad to perform a CMP process on the semiconductor wafer; in real time, receiving signals from the CMP tool into a signal analyzer, the signals corresponding to vibration, acoustics, temperature, or pressure; and comparing the received signals from the CMP tool to expected received signals for normal processing by the CMP tool; outputting a result of the comparing. A CMP tool apparatus is disclosed.

Abstract: The present invention relates generally to assembly techniques. According to the present invention, the alignment and probing techniques to improve the accuracy of component placement in assembly are described. More particularly, the invention includes methods and structures to detect and improve the component placement accuracy on a target platform by incorporating alignment marks on component and reference marks on target platform under various probing techniques. A set of sensors grouped in any array to form a multiple-sensor probe can detect the deviation of displaced components in assembly.

Abstract: A method for manufacturing a semiconductor device includes forming a source electrode and a drain electrode on a front face of a semiconductor substrate which is transparent to visible light, forming a front-side gate electrode between the source electrode and the drain electrode on the front face of the semiconductor substrate; forming an aligning mark on a region of the front face of the semiconductor substrate other than a region between the source electrode and the drain electrode, aligning the semiconductor substrate based on the aligning mark that is seen through the semiconductor substrate, and forming a back-side gate electrode on a back face of the semiconductor substrate in a location opposite the front-side gate electrode.

Abstract: An Electrostatic Post Exposure Bake (EPEB) subsystem comprising an Electrostatic Bake Plate (EBP) configured in a processing chamber in an EPEB subsystem, wherein the EPEB wafer comprises an exposed masking layer having unexposed regions and exposed regions therein and the EPEB wafer is developed using the EBP.

Abstract: A substrate etching method and apparatus are disclosed. In one embodiment, a method for etching is provided that includes, in a plasma processing chamber, etching a feature in a silicon layer using an etch recipe that includes cyclical etching and deposition substeps until an end point is reached, wherein an aspect ratio of the feature increases with a number of cyclical etching and deposition substeps performed over time until the end point is reached; and adjusting a recipe variable of the etch recipe in response to the current aspect ratio of the feature during etching to manage thickness of sidewall polymers when the feature becomes deeper to avoid closing the feature and preventing subsequent etching.

Abstract: A method of depositing a bilayer of tungsten over tungsten nitride by a plasma sputtering process in which krypton is used as the sputter working gas during the tungsten deposition. Argon may be used as the sputtering working gas during the reactive sputtering deposition of tungsten nitride. The beneficial effect of reduction of tungsten resistivity is increased when the thickness of the tungsten layer is less than 50 nm and further increased when less than 35 nm. The method may be used in forming a gate stack including a polysilicon layer over a gate oxide layer over a silicon gate region of a MOS transistor in which the tungsten nitride acts as a barrier. A plasma sputter chamber in which the invention may be practiced includes gas sources of krypton, argon, and nitrogen.

Abstract: A semiconductor device includes at least one first type of pad and at least one second type of pad having a different area from the first type of pad. A pad connection unit electrically couples the at least one second type of pad to an integrated circuit of the semiconductor device during a test mode, and disconnects the at least one second type of pad from the integrated circuit during a normal operating mode.

Abstract: A method for repairing a chip with a stacked structure of chips is provided. First, a first chip is provided, which includes a first circuit block with a first function, a second circuit block with a second function, and a signal path electrically connected to the first and the second circuit blocks. A second chip is provided, which includes a third circuit block with the first function. The functions of the first and the second chips are verified. The first circuit block is disabled if the first circuit block is defective. The third circuit block is electrically connected to the signal path to replace the first circuit block and provide the first function if the second circuit block is functional and the third circuit block is functional.

Abstract: The present invention is directed to a system that programmably interconnects integrated circuit chips and other components at near-intra-chip density. The system's contact structure allows it to adapt to components with a wide variety of contact spacings and interconnection requirements, the use of releasable attachment means allows component placement to be modified as needed, the system identifies the contacts and the components to facilitate specifying the inter-component connections, and the system provides signal conditioning and retiming to minimize issues with signal integrity and signal skew.

Abstract: Stacking techniques are illustrated in example embodiments of the present invention wherein semiconductor dies are mounted in a module to become a MCM which serves as the basic building block. A combination of these modules and dies in a substrate creates a package with specific function or a range of memory capacity. Several example system configurations are provided using BGA and PGA to illustrate the stacking technique. Several pin assignment and signal routing techniques are illustrated wherein internal and external signals are routed from main board to various stacked modules. Expansion can be done both on the vertical and horizontal orientations.

Abstract: A nitride semiconductor free-standing substrate includes a surface inclined in a range of 0.03° to 1.0° from a C-plane, and an off-orientation that an angle defined between a C-axis and a tangent at each point on a whole surface of the substrate becomes maximum is displaced in a range of 0.5° to 16° from a particular M-axis orientation of six-fold symmetry M-axis orientations. The substrate does not include a region of ?0.5°<?<+0.5° on the surface, where ? represents a displacement angle of the off-orientation on a surface of the substrate from the particular M-axis orientation.

Abstract: In a wafer, a plurality of basic chips F is arranged therein. The basic chip F has a memory capacity of i-mega bytes. By dicing, a memory chip including four basic chips F is cut out of the wafer. The memory chip has a memory capacity of 4×i-mega bytes. A dicing line is interposed between four basic chips F configuring the memory chip, Four basic chips F can change word organization by a control signal individually.