Connection Or Disconnection Of Subentities Or Redundant Parts Of Device In Response To Measurement, E.g., Wafer Scale, Memory Devices (epo) Patents (Class 257/E21.526)
  • Patent number: 10330701
    Abstract: A test probe head for probe testing multiple chips on a wafer in a single probing. A probe head substrate includes an array of probe tip attach pads on one surface. The array includes a subarray for each probe head chip test site. Probe tips attached to each probe tip attach pad have an across the head tip height variation less than one micrometer (1 ?m). The subarray probe tips may be on a pitch at or less than fifty microns (50 ?m). The test probe head may be capable of test probing all chips in a quadrant and even up to all chips on a single wafer in a single probing.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: June 25, 2019
    Assignee: International Business Machines Corporation
    Inventors: Bing Dang, Yu Luo, John Knickerbocker, Yang Liu, Steven L. Wright
  • Patent number: 10319451
    Abstract: Provided is a semiconductor device including chip identification (ID) generation circuits. The semiconductor device may be a multi-chip package including a plurality of memory chips, and each of the memory chips includes a chip ID generation circuit configured to selectively modify a chip ID of a corresponding memory chip. The chip ID generation circuit determines the chip ID of the memory chip by testing the chip ID of the memory chip by using a mode register, and selectively programs the chip ID of the memory chip by using at least two fuse sets. The chip ID generation circuit may block an output of the chip ID of the memory chip when the memory chip is determined as a defective chip or is selected to stop its use.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: June 11, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yang-gyoon Loh, Je-min Ryu, Hyun-ki Kim, Yoon-jae Jeong
  • Patent number: 10146555
    Abstract: Systems and methods for utilizing a defect map to configure an automata processor in order to avoid defects when configuring the automata processor. A system includes automata processor having a state machine lattice. The system also includes a non-volatile memory having a defect map stored thereon and indicating logical defects found on the automata processor. By including the defect map, a compiler accesses the defect map to map out defects in the automata processor during configuring to avoid such defects.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: December 4, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Dale Hiscock
  • Patent number: 9947712
    Abstract: Technology is described for selectively disconnecting a communal module (e.g., horizontal power and signal distribution network) from conductive traces (e.g., vertical columns) that are coupled to cell elements. In one example, a matrix type integrated circuit includes a two dimensional (2D) array of cell elements, a plurality of conductive traces, a communal module, and a plurality of switches. Each cell element in the 2D array provides a similar function. The plurality of conductive traces is substantially parallel to a first axis of the 2D array. Each conductive trace is coupled to a conductive interconnect of cell elements adjacent to the conductive trace. The communal module is configured to provide distribution of at least one electrical signal to the cell elements in the 2D array via at least two conductive traces that are substantially parallel to the first axis.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: April 17, 2018
    Assignee: VAREX IMAGING CORPORATION
    Inventor: Pieter Gerhard Roos
  • Patent number: 9553126
    Abstract: A wafer-level method for fabricating a plurality of cameras includes modifying an image sensor wafer to reduce risk of the image sensor wafer warping, and bonding the image sensor wafer to a lens wafer to form a composite wafer that includes the plurality of cameras. A wafer-level method for fabricating a plurality of cameras includes bonding an image sensor wafer to a lens wafer, using a pressure sensitive adhesive, to form a composite wafer that includes the plurality of cameras.
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: January 24, 2017
    Assignee: OmniVision Technologies, Inc.
    Inventors: Alan Martin, Edward Nabighian
  • Patent number: 9285422
    Abstract: A tester configured to test a strip of devices is provided. The tester may include a communications system, a plurality of communication lines, a plurality of multiplexors, each multiplexor having at least two outputs, wherein each multiplexor is configured to receive a signal generated by the communications system via one of the plurality of communication lines, and each multiplexor may be selectably coupled to at least two of the devices in the strip of devices. The tester may be configured to index the plurality of communication lines to a first subset of the devices, initiate at least one test, command the devices to generate data for each of the at least one tests, retrieve data from a first set of the devices, and retrieve data from a second set of the devices.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: March 15, 2016
    Assignee: FREESCALE SEMICONDUCTOR INC.
    Inventors: Chad S. Dawson, Stephen R. Hooper, Peter T. Jones, Mark E. Schlarmann
  • Patent number: 8999815
    Abstract: A method for fabricating a finFET device having an insulating layer that insulates the fin from a substrate is described. The insulating layer can prevent leakage current that would otherwise flow through bulk semiconductor material in the substrate. The structure may be fabricated starting with a bulk semiconductor substrate, without the need for a semiconductor-on-insulator substrate. Fin structures may be formed by epitaxial growth, which can improve the uniformity of fin heights in the devices.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: April 7, 2015
    Assignees: STMicroelectronics, Inc., International Business Machines Corporation
    Inventors: Qing Liu, Junli Wang
  • Patent number: 8729696
    Abstract: In a testing method for an LD, an LD die is held. Then, electric current increasing with a fixed increment and having a sequence of current values is supplied to the LD die to drive the LD die to emit light and a sequence of voltage values across the LD die and corresponding to the sequence of current values, respectively, is metered. A sequence of power values corresponding to the sequence of current values, respectively, is also metered. Next, an electro-optical property of the LD die is determined according to the sequence of current values, the sequence of voltage values, and the sequence of power values. Finally, if the LD die is determined to be qualified based upon the electro-optical property of the LD die, the LD die is packaged into the LD.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: May 20, 2014
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventors: Bing-Heng Lee, Kuo-Fong Tseng
  • Patent number: 8704226
    Abstract: A chip is layered on a rewiring member. A plurality of connecting members and a plurality of redundant connecting members are arranged in the chip, and electrically connect the chip to the rewiring member. Redundant circuits are embedded in each of the rewiring member and the chip. When one of the connecting members is faulty, the redundant circuits cause one of the redundant connecting members to transmit a signal between the rewiring member and the chip, instead of the faulty connecting member. The connecting members have first and second subsets arranged in first and second regions, respectively. A distance between the rewiring member and the chip exceeds a predetermined threshold value in the first region in contrast to the second region. The first subset has a higher proportion of connecting members that the redundant circuits can replace with a subset of the redundant connecting members than the second subset.
    Type: Grant
    Filed: January 11, 2012
    Date of Patent: April 22, 2014
    Assignee: Panasonic Corporation
    Inventors: Takashi Morimoto, Takashi Hashimoto
  • Patent number: 8686559
    Abstract: A stacked semiconductor chip comprising multiple unit chips contains multiple instances of a first chip component that have a low yield and are distributed among the multiple unit chips. An instance of the first chip component within a first unit chip is logically paired with at least another instance of the first chip component within at least another unit chip so that the combination of the multiple instances of the first chip component across the multiple unit chips constitute a functional block providing the functionality of a fully functional instance of the first chip component. The stacked semiconductor chip may include multiple instances of a second chip component having a high yield and distributed across the multiple unit chips. Multiple low yield components constitute a functional block providing an enhanced overall yield, while high yield components are utilized to their full potential functionality.
    Type: Grant
    Filed: September 8, 2012
    Date of Patent: April 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kerry Bernstein, Philip G. Emma, Michael Ignatowski
  • Patent number: 8564023
    Abstract: At least one MOS parameter of a MOS fuse is characterized to provide at least one MOS parameter reference value. Then, the MOS fuse is programmed by applying a programming signal to the fuse terminals so that programming current flows through the fuse link. The fuse resistance is measured to provide a measured fuse resistance associated with a first logic value. A MOS parameter of the programmed MOS fuse is measured to provide a measured MOS parameter value. The measured MOS parameter value is compared to the reference MOS parameter value to determine a second logic value of the MOS fuse, and a bit value is output based on the comparison.
    Type: Grant
    Filed: March 6, 2008
    Date of Patent: October 22, 2013
    Assignee: Xilinx, Inc.
    Inventors: Hsung Jai Im, Sunhom Paak, Boon Yong Ang
  • Publication number: 20130236992
    Abstract: In a testing method for an LD, an LD die is held. Then, electric current increasing with a fixed increment and having a sequence of current values is supplied to the LD die to drive the LD die to emit light and a sequence of voltage values across the LD die and corresponding to the sequence of current values, respectively, is metered. A sequence of power values corresponding to the sequence of current values, respectively, is also metered. Next, an electro-optical property of the LD die is determined according to the sequence of current values, the sequence of voltage values, and the sequence of power values. Finally, if the LD die is determined to be qualified based upon the electro-optical property of the LD die, the LD die is packaged into the LD.
    Type: Application
    Filed: June 27, 2012
    Publication date: September 12, 2013
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: BING-HENG LEE, KUO-FONG TSENG
  • Patent number: 8513034
    Abstract: A method of manufacturing a layered chip package that includes a main body, and wiring disposed on a side surface of the main body. The main body includes a plurality of layer portions. The method includes fabricating a plurality of substructures, and completing the layered chip package by fabricating the main body using the plurality of substructures and by forming the wiring on the main body.
    Type: Grant
    Filed: April 22, 2011
    Date of Patent: August 20, 2013
    Assignees: Headway Technologies, Inc., TDK Corporation, SAE Magnetics (H.K.) Ltd.
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa, Satoru Sueki, Hiroshi Ikejima
  • Patent number: 8507297
    Abstract: A wafer containing a plurality of electro-optical devices, each device being enclosed in chamber that has a translucent cover. An X-Y matrix of pairs of interconnections on the wafer are connected to the circuitry of the electro-optical devices for addressing the electro-optical devices. The pairs of interconnections extend outside of the chambers enclosing the devices to testing areas on the periphery of the wafer. Testing is done by signals applied through the interconnections while simultaneously exposing the devices to light through the translucent covers.
    Type: Grant
    Filed: August 16, 2010
    Date of Patent: August 13, 2013
    Assignee: Spatial Photonics, Inc.
    Inventors: Shaoher X. Pan, Vlad Novotny
  • Publication number: 20130162173
    Abstract: Methods for manufacturing a light source circuit board having one or more light emitting components that include providing at least one circuit component on a light source circuit board, wherein the at least one circuit component has an electrical circuit constant that specifies one or more performance parameters for the light source. The methods also include measuring the electrical circuit constant of the at least one circuit component. The methods also include identifying one or more performance parameters for the light source based on the measured electrical constant.
    Type: Application
    Filed: December 21, 2011
    Publication date: June 27, 2013
    Applicant: LUMENPULSE LIGHTING INC.
    Inventors: Dale Reynolds, Gregory Campbell
  • Publication number: 20130126866
    Abstract: A semiconductor device in one embodiment includes a wiring board having a wiring pattern; an N semiconductor elements(where N denotes a natural number equal to or greater than 2) mounted on a wiring board; and a current detection parts for detecting a current flowing through m semiconductor elements (where m denotes a natural number equal to or greater than 1 but less than M) of M semiconductor elements(where M denotes a natural number equal to or greater than 1 but equal to or less than N) mounted on the wiring board and selected from the N semiconductor elements. The M semiconductor elements are electrically connected in parallel through the wiring pattern, and the m semiconductor elements are electrically connected in parallel to the other semiconductor elements of the M semiconductor elements through the current detection part.
    Type: Application
    Filed: October 26, 2012
    Publication date: May 23, 2013
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Sumitomo Electric Industries, Ltd.
  • Publication number: 20130122613
    Abstract: To provide improved planarization, techniques in accordance with this disclosure include a CMP station that utilizes localized planarization on a wafer. This localized planarization, which is often carried out in a localized planarization station downstream of a CMP station, applies localized planarization to less than the entire face of the wafer to correct localized non-planar features. Other systems and methods are also disclosed.
    Type: Application
    Filed: November 14, 2011
    Publication date: May 16, 2013
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Chen Wang, Feng-Inn Wu
  • Publication number: 20130044004
    Abstract: Methods and apparatus for detecting errors in real time in CMP processing. A method includes disposing a semiconductor wafer onto a wafer carrier in a tool for chemical mechanical polishing (“CMP”); positioning the wafer carrier so that a surface of the semiconductor wafer contacts a polishing pad mounted on a rotating platen; dispensing an abrasive slurry onto the rotating polishing pad while maintaining the surface of the semiconductor wafer in contact with the polishing pad to perform a CMP process on the semiconductor wafer; in real time, receiving signals from the CMP tool into a signal analyzer, the signals corresponding to vibration, acoustics, temperature, or pressure; and comparing the received signals from the CMP tool to expected received signals for normal processing by the CMP tool; outputting a result of the comparing. A CMP tool apparatus is disclosed.
    Type: Application
    Filed: August 17, 2011
    Publication date: February 21, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: James Jeng-Jyi Hwang, Bo-I Lee, Chi-Ming Yang, Chin-Hsiang Lin
  • Patent number: 8350393
    Abstract: The present invention relates generally to assembly techniques. According to the present invention, the alignment and probing techniques to improve the accuracy of component placement in assembly are described. More particularly, the invention includes methods and structures to detect and improve the component placement accuracy on a target platform by incorporating alignment marks on component and reference marks on target platform under various probing techniques. A set of sensors grouped in any array to form a multiple-sensor probe can detect the deviation of displaced components in assembly.
    Type: Grant
    Filed: May 13, 2010
    Date of Patent: January 8, 2013
    Assignee: Wintec Industries, Inc.
    Inventor: Kong-Chen Chen
  • Publication number: 20120315708
    Abstract: A method for manufacturing a semiconductor device includes forming a source electrode and a drain electrode on a front face of a semiconductor substrate which is transparent to visible light, forming a front-side gate electrode between the source electrode and the drain electrode on the front face of the semiconductor substrate; forming an aligning mark on a region of the front face of the semiconductor substrate other than a region between the source electrode and the drain electrode, aligning the semiconductor substrate based on the aligning mark that is seen through the semiconductor substrate, and forming a back-side gate electrode on a back face of the semiconductor substrate in a location opposite the front-side gate electrode.
    Type: Application
    Filed: January 23, 2012
    Publication date: December 13, 2012
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Yoshitaka KAMO
  • Patent number: 8288174
    Abstract: An Electrostatic Post Exposure Bake (EPEB) subsystem comprising an Electrostatic Bake Plate (EBP) configured in a processing chamber in an EPEB subsystem, wherein the EPEB wafer comprises an exposed masking layer having unexposed regions and exposed regions therein and the EPEB wafer is developed using the EBP.
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: October 16, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Benjamen M. Rathsack, Brian Head, Steven Scheer
  • Publication number: 20120208300
    Abstract: A substrate etching method and apparatus are disclosed. In one embodiment, a method for etching is provided that includes, in a plasma processing chamber, etching a feature in a silicon layer using an etch recipe that includes cyclical etching and deposition substeps until an end point is reached, wherein an aspect ratio of the feature increases with a number of cyclical etching and deposition substeps performed over time until the end point is reached; and adjusting a recipe variable of the etch recipe in response to the current aspect ratio of the feature during etching to manage thickness of sidewall polymers when the feature becomes deeper to avoid closing the feature and preventing subsequent etching.
    Type: Application
    Filed: April 25, 2012
    Publication date: August 16, 2012
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Alan Cheshire, Stanley Detmar
  • Patent number: 8216933
    Abstract: A method of depositing a bilayer of tungsten over tungsten nitride by a plasma sputtering process in which krypton is used as the sputter working gas during the tungsten deposition. Argon may be used as the sputtering working gas during the reactive sputtering deposition of tungsten nitride. The beneficial effect of reduction of tungsten resistivity is increased when the thickness of the tungsten layer is less than 50 nm and further increased when less than 35 nm. The method may be used in forming a gate stack including a polysilicon layer over a gate oxide layer over a silicon gate region of a MOS transistor in which the tungsten nitride acts as a barrier. A plasma sputter chamber in which the invention may be practiced includes gas sources of krypton, argon, and nitrogen.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: July 10, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Wei D. Wang, Srinivas Gandikota, Kishore Lavu
  • Patent number: 8198627
    Abstract: A semiconductor device includes at least one first type of pad and at least one second type of pad having a different area from the first type of pad. A pad connection unit electrically couples the at least one second type of pad to an integrated circuit of the semiconductor device during a test mode, and disconnects the at least one second type of pad from the integrated circuit during a normal operating mode.
    Type: Grant
    Filed: October 18, 2010
    Date of Patent: June 12, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Woo-seop Jeong
  • Patent number: 8193006
    Abstract: A method for repairing a chip with a stacked structure of chips is provided. First, a first chip is provided, which includes a first circuit block with a first function, a second circuit block with a second function, and a signal path electrically connected to the first and the second circuit blocks. A second chip is provided, which includes a third circuit block with the first function. The functions of the first and the second chips are verified. The first circuit block is disabled if the first circuit block is defective. The third circuit block is electrically connected to the signal path to replace the first circuit block and provide the first function if the second circuit block is functional and the third circuit block is functional.
    Type: Grant
    Filed: August 6, 2009
    Date of Patent: June 5, 2012
    Assignee: Industrial Technology Research Institute
    Inventors: Yung-Fa Chou, Ding-Ming Kwai
  • Patent number: 8124429
    Abstract: The present invention is directed to a system that programmably interconnects integrated circuit chips and other components at near-intra-chip density. The system's contact structure allows it to adapt to components with a wide variety of contact spacings and interconnection requirements, the use of releasable attachment means allows component placement to be modified as needed, the system identifies the contacts and the components to facilitate specifying the inter-component connections, and the system provides signal conditioning and retiming to minimize issues with signal integrity and signal skew.
    Type: Grant
    Filed: December 15, 2006
    Date of Patent: February 28, 2012
    Inventor: Richard Norman
  • Patent number: 8093103
    Abstract: Stacking techniques are illustrated in example embodiments of the present invention wherein semiconductor dies are mounted in a module to become a MCM which serves as the basic building block. A combination of these modules and dies in a substrate creates a package with specific function or a range of memory capacity. Several example system configurations are provided using BGA and PGA to illustrate the stacking technique. Several pin assignment and signal routing techniques are illustrated wherein internal and external signals are routed from main board to various stacked modules. Expansion can be done both on the vertical and horizontal orientations.
    Type: Grant
    Filed: October 18, 2010
    Date of Patent: January 10, 2012
    Assignee: BiTMICRO Networks, Inc.
    Inventors: Rey H. Bruce, Ricardo H. Bruce, Patrick Digamon Bugayong, Joel Alonzo Baylon
  • Patent number: 8026523
    Abstract: A nitride semiconductor free-standing substrate includes a surface inclined in a range of 0.03° to 1.0° from a C-plane, and an off-orientation that an angle defined between a C-axis and a tangent at each point on a whole surface of the substrate becomes maximum is displaced in a range of 0.5° to 16° from a particular M-axis orientation of six-fold symmetry M-axis orientations. The substrate does not include a region of ?0.5°<?<+0.5° on the surface, where ? represents a displacement angle of the off-orientation on a surface of the substrate from the particular M-axis orientation.
    Type: Grant
    Filed: October 14, 2008
    Date of Patent: September 27, 2011
    Assignee: Hitachi Cable, Ltd.
    Inventor: Hajime Fujikura
  • Patent number: 7977159
    Abstract: In a wafer, a plurality of basic chips F is arranged therein. The basic chip F has a memory capacity of i-mega bytes. By dicing, a memory chip including four basic chips F is cut out of the wafer. The memory chip has a memory capacity of 4×i-mega bytes. A dicing line is interposed between four basic chips F configuring the memory chip, Four basic chips F can change word organization by a control signal individually.
    Type: Grant
    Filed: March 8, 2006
    Date of Patent: July 12, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yukihiro Urakawa
  • Publication number: 20110127536
    Abstract: An active matrix substrate (2) is provided with first connecting wirings (641, 643, 645, 647) connected to gate terminals (51) to which extraction wirings (611, 613, 615, 617) are connected, second connecting wirings (642, 644, 646) connected to gate terminals (51) to which extraction wirings (612, 614, 616) are connected, bundled wirings (651 to 654) each composed of a mutually adjacent first connecting wiring and second connecting wiring bunched together, a first inspection wiring (66) capable of inputting an inspection signal to bunched wirings (652, 654) that are not adjacent to each other among the bundled wirings, and a second inspection wiring (67) capable of inputting an inspection signal to bundled wirings (651, 653) that are not adjacent to each other and not connected to the first inspection wiring (66) among the bundled wirings.
    Type: Application
    Filed: May 11, 2009
    Publication date: June 2, 2011
    Inventors: Masahiro Yoshida, Takehiko Kawamura, Katsuhiro Okada
  • Patent number: 7947514
    Abstract: A semiconductor device production process includes forming, on a prepared SOI wafer, semiconductor functional devices and substrate contacts. The substrate contacts connect to a support substrate of the SOI wafer. The semiconductor device production process also includes forming a pattern that connects the substrate contacts to external connection pads formed on the semiconductor functional devices such that the external connection pads are not connected to each other. The semiconductor device production process also includes measuring conductivity between the external connection pads.
    Type: Grant
    Filed: March 14, 2008
    Date of Patent: May 24, 2011
    Assignee: Oki Semiconductor Co., Ltd.
    Inventors: Koichi Kishiro, Kouji Nasu
  • Publication number: 20110117681
    Abstract: Methods and apparatus are presented for monitoring the deposition and/or post-deposition processing of semiconductor thin films using photoluminescence imaging. The photoluminescence images are analysed to determine one or more properties of the semiconductor film, and variations thereof across the film. These properties are used to infer information about the deposition process, which can then be used to adjust the deposition process conditions and the conditions of subsequent processing steps. The methods and apparatus have particular application to thin film-based solar cells.
    Type: Application
    Filed: July 9, 2009
    Publication date: May 19, 2011
    Applicant: BT IMAGING PTY LTD
    Inventors: Robert Andrew Bardos, Thorsten Trupke, Ian Andrew Maxwell
  • Patent number: 7932105
    Abstract: Systems and methods for detecting and monitoring Nickel-silicide process and induced failures. In a first method embodiment, a method of characterizing a Nickel-silicide semiconductor manufacturing process includes accessing a test chip including a parallel coupled chain of transistors, wherein the transistors are designed for inducing stress into Nickel-silicide features of the transistors, and for increasing a probability of a manufacturing failure of the Nickel-silicide features. A biasing voltage is applied to one terminal of the parallel coupled chain, all other terminals of the parallel coupled chain and grounded, and current is measured at each of the all other terminals of the parallel coupled chain. This process is repeated for each terminal of the parallel coupled chain. The measured currents from all possible conduction paths are compared to determine a manufacturing defect in the parallel coupled chain of transistors.
    Type: Grant
    Filed: October 14, 2008
    Date of Patent: April 26, 2011
    Assignee: PDF Solutions
    Inventors: Sharad Saxena, Jae-Yong Park, Benjamin Shieh, Mark Spinelli, Shiying Xiong, Hossein Karbasi
  • Patent number: 7892962
    Abstract: A wafer-level chip-scale packaging feature for a semiconductor device is disclosed which has a substrate, a plurality of nail-shaped conducting posts extending from a surface of the substrate, and a plurality of solder balls, where each of the solder balls is connected to one of the nail-shaped conducting posts. When a different-sized solder ball is desired for use, the device can be re-processed by only removing and replacing the cross-members of the nail-shaped conducting posts, which cuts down on the re-processing expense.
    Type: Grant
    Filed: September 5, 2007
    Date of Patent: February 22, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Chao-Yuan Su
  • Publication number: 20110014725
    Abstract: Disclosed is a method for manufacturing a solar cell module in which a wiring substrate having a base material and a wiring formed on the base material, and a plurality of solar cells electrically connected by being placed on the wiring of the wiring substrate are sealed with a sealant, including a first step of placing at least one of the solar cells on the wiring of the wiring substrate, and a second step of sealing the wiring substrate and the solar cells with the sealant, the method including the step of conducting an inspection of the solar cells after the first step and before the second step.
    Type: Application
    Filed: December 18, 2008
    Publication date: January 20, 2011
    Inventors: Yoshiya Abiko, Yasushi Funakoshi, Kyotaro Nakamura
  • Patent number: 7856804
    Abstract: A MEMS device comprising a flexible membrane that is free to move in response to pressure differences generated by sound waves. A first electrode mechanically coupled to the flexible membrane, and together form a first capacitive plate. A second electrode mechanically coupled to a generally rigid structural layer or back-plate, which together form a second capacitive plate. A back-volume is provided below the membrane. A first cavity located directly below the membrane. Interposed between the first and second electrodes is a second cavity. A plurality of bleed holes connected the first cavity and the second cavity. Acoustic holes are arranged in the back-plate so as to allow free movement of air molecules, such that the sound waves can enter the second cavity. The first and second cavities in association with the back-volume allow the membrane to move in response to the sound waves entering via the acoustic holes in the back-plate.
    Type: Grant
    Filed: March 9, 2010
    Date of Patent: December 28, 2010
    Assignee: Wolfson Microelectronics plc
    Inventors: Richard I. Laming, Mark Begbie, Anthony Traynor
  • Patent number: 7851898
    Abstract: Disclosed is a multichip package or system-in package which the logic chip includes a selector circuit which, by transmitting a test mode select signal or a test mode select command to the logic chip, enables access from a logic signal pin connected to the logic chip, to a memory control signal to each of the “m” number of memory chips; and the memory control signal, when viewed from the logic chip, is connected using a one-for-one wiring scheme or a one-for-up-to-m branch wiring scheme, between the selector circuit and each of the “m” number of memory chips. This multichip package or system-in package is low in noise and high in operational reliability.
    Type: Grant
    Filed: March 21, 2006
    Date of Patent: December 14, 2010
    Assignees: Hitachi, Ltd., Elpida Memory, Inc.
    Inventors: Satoshi Nakamura, Takashi Suga, Mitsuaki Katagiri, Yukitoshi Hirose
  • Patent number: 7842953
    Abstract: A pixel structure disposed on a substrate and including a common line, a reserved line, a dielectric layer, two repair lines, an active device, and a pixel electrode is provided. The reserved line and the common line are disposed on the substrate and are covered by the dielectric layer. The repair lines are disposed on the dielectric layer, and each repair line has a first repairing region overlapped with the common line and a second repairing region overlapped with the reserved line. When the common line is open, the repair lines in the first and second repairing regions are connected with the common line and the reserved line, such that the common line, the repair lines, and the reserved line are electrically connected. After the common line, the repair lines, and the reserved line are connected, the above-mentioned pixel structure is effectively repaired.
    Type: Grant
    Filed: March 11, 2008
    Date of Patent: November 30, 2010
    Assignee: Au Optronics Corporation
    Inventor: Hui-Ling Ku
  • Patent number: 7834350
    Abstract: A semiconductor device includes at least one first type of pad and at least one second type of pad having a different area from the first type of pad. A pad connection unit electrically couples the at least one second type of pad to an integrated circuit of the semiconductor device during a test mode, and disconnects the at least one second type of pad from the integrated circuit during a normal operating mode.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: November 16, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Woo-Seop Jeong
  • Patent number: 7795045
    Abstract: A method of manufacturing a semiconductor wafer having at least one device trench extending to a first depth position includes providing a semiconductor substrate having first and second main surfaces and a semiconductor material layer having first and second main surfaces disposed on the first main surface of the semiconductor substrate and determining an etch ratio. The least one device trench and at least one monitor trench are simultaneously formed in the first main surface of the semiconductor material layer. The at least one monitor trench is monitored to detect when it extends to a second depth position. A ratio of the first depth position to the second depth position is generally equal to the etch ratio.
    Type: Grant
    Filed: February 13, 2009
    Date of Patent: September 14, 2010
    Assignee: Icemos Technology Ltd.
    Inventors: Hugh J. Griffin, Takeshi Ishiguro, Kenji Sugiura
  • Patent number: 7785906
    Abstract: A test structure which can be used to detect residual conductive material such as polysilicon which can result from an under etch comprises a PMOS transistor and an OTP EPROM floating gate device. By testing the devices using different testing parameters, it can be determined whether residual conductive material remains subsequent to an etch, and where the residual conductive material is located on the device. A method for testing a semiconductor device using the test structure is also described.
    Type: Grant
    Filed: December 12, 2007
    Date of Patent: August 31, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Xiaoju Wu, Jozef Czeslaw Mitros
  • Patent number: 7779311
    Abstract: Disclosed are systems and methods of producing electronic devices including an auxiliary circuit mounted on another, underlying, circuit at the wafer level. The auxiliary circuit is electrically connected to the underlying circuit via micro-scale interconnects. The systems are capable of testing the auxiliary circuit and/or interconnects using an interface within the underlying circuit. For example, the auxiliary circuit may be tested although it is mounted such that the interconnects are hidden, i.e., inaccessible for testing purposes after assembly using conventional testing systems and methods. The systems and methods further allow for including excess circuits and/or excess interconnects that can be reconfigured to replace parts of the auxiliary circuit and/or micro-scale interconnects found defective during testing.
    Type: Grant
    Filed: October 4, 2006
    Date of Patent: August 17, 2010
    Assignee: Rambus Inc.
    Inventor: Adrian E. Ong
  • Patent number: 7754532
    Abstract: Methods and devices for multi-chip stacks are shown. A method is shown that assembles multiple chips into stacks by stacking wafers prior to dicing into individual chips. Methods shown provide removal of defective chips and their replacement during the assembly process to improve manufacturing yield.
    Type: Grant
    Filed: October 19, 2006
    Date of Patent: July 13, 2010
    Assignee: Micron Technology, Inc.
    Inventor: Paul A. Farrar
  • Patent number: 7749779
    Abstract: A landing pad for use as a contact to a conductive spacer adjacent a structure in a semiconductor device comprises two islands, each of which is substantially rectangularly shaped and is spaced apart from one another and from the structure. Conductive spacers are adjacent to each island and overlapping each other and overlapping with the conductive spacer adjacent to the structure. The contact to the landing pad is on the conductive spacers adjacent to the islands and spaced apart from the structure.
    Type: Grant
    Filed: November 6, 2008
    Date of Patent: July 6, 2010
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Dana Lee, Wen-Juei Lu, Felix Ying-Kit Tsui
  • Patent number: 7719114
    Abstract: An edit structure is disclosed that allows the input of a logic gate to be changed by modifying any one of the metal and via masks that are used to form the metal interconnect structure. As a result, a first permanent logic state provided by a tie-in circuit can be changed to a second permanent logic state by modifying any one of the metal and via masks that are used to form the metal interconnect structure.
    Type: Grant
    Filed: October 17, 2007
    Date of Patent: May 18, 2010
    Assignee: National Semiconductor Corporation
    Inventor: Richard J. Doyon, Jr.
  • Publication number: 20090289363
    Abstract: In one aspect, a method for configuring a ball grid array is disclosed. The method may include identifying a number of balls for use in a ball grid array, determining a number of rows and a number of columns for the ball grid array, and populating the ball grid array at least in part with a plurality of ball-space groupings. The method may also include allocating an unpopulated portion of an area bounded by the at least one first outside row, the at least one second outside row, the at least one first outside column, and the at least one second outside column, to be free of balls. The method may also include routing a signal line from a ball of at least one ball-space grouping to a space of the at least one ball-space grouping and routing the signal line to a substrate layer through a via.
    Type: Application
    Filed: May 23, 2008
    Publication date: November 26, 2009
    Applicant: Texas Instruments Incorporated
    Inventors: Keven Dale Coates, Thomas William Krauskopf
  • Patent number: 7579268
    Abstract: A method of manufacturing an integrated circuit including a first isolated chip electrically and mechanically connected via wafer bonding to a second isolated chip, wherein the active faces of the chips face one another, includes: forming metallic contact zones on active faces of first and second wafers, positioning and fixing the wafers one above another at a predetermined distance such that the active faces of the wafers face one another and the contact zones are aligned, placing the fixed wafers in a bath for electroless metal deposition onto the contact zones; and removing the fixed wafers in the event that the metal layers growing on the aligned contact zones of the first and second wafers have grown together.
    Type: Grant
    Filed: June 4, 2007
    Date of Patent: August 25, 2009
    Assignee: Infineon Technologies AG
    Inventor: Horst Theuss
  • Patent number: 7547560
    Abstract: A method for improving semiconductor yield by in-line repair of defects during manufacturing comprises inspecting dies on a wafer after a selected layer is formed on the dies, identifying defects in each of the dies, classifying the identified defects as killer or non-critical, for each killer defect determining an action to correct the defect, repairing the defect and returning the wafer to a next process step. Also disclosed is a method for determining an efficient repair process by dividing the die into a grid and using analysis of the grid to find a least invasive repair.
    Type: Grant
    Filed: September 12, 2006
    Date of Patent: June 16, 2009
    Assignee: Agere Systems Inc.
    Inventors: Oliver Desmond Patterson, David M. Shuttleworth, Bradley J. Albers, Werner Weck, Gregory Brown
  • Patent number: 7541279
    Abstract: A method for manufacturing a semiconductor device is provided. The method includes the steps of forming an interlayer insulating layer on a semiconductor substrate, selectively patterning the interlayer insulating layer to form a contact hole, depositing a first metal on an inner surface of the contact hole, submerging the semiconductor substrate on which the first metal is deposited into an electrochemical plating (ECP) solution bath in which a second metal is dissolved, dissolving the first metal in the ECP solution bath, plating the first and second metals dissolved in the ECP solution bath at the same time to gap-fill an alloy of the first and second metals in the contact hole, and removing the alloy using the interlayer insulating layer as an end point in a CMP process to form an alloy interconnection.
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: June 2, 2009
    Assignee: Dongbu Electronics Co., Ltd
    Inventors: Sang Chul Kim, Jae Won Han
  • Publication number: 20090114912
    Abstract: An integrated circuit (IC) includes a substrate having a device layer and a plurality of metal layers formed thereon. The plurality of metal layers include patterned upper metal layers and lower metal layers, a multi-level metal interconnect structure formed using the plurality of metal layers, where the interconnect structure is in electrical contact with a first portion and second portion of the device layer. At least one circuit editing structure including a first and second columns are formed using at least a portion of the plurality of metal layers, the first column being in electrical contact with the first portion of the device layer and the second column being in electrical contact with second portion of the device layer, where a portion of the first and second columns define a circuit editing feature operable to electrically couple or decouple the columns using focused ion beam (FIB) processing.
    Type: Application
    Filed: November 1, 2007
    Publication date: May 7, 2009
    Applicant: Texas Instruments Incorporated
    Inventors: Jeffrey Lee Large, Henry Litzmann Edwards, Ayman A. Fayed, Patrick Cruise, Kah Mun Low, Neeraj Nayak, Oguz Altun, Chris Barr