Abstract: Embodiments of the present disclosure provide a control method and apparatus for hybrid process recipes, and a device and a medium. The control method includes: acquiring hybrid process recipe operation groups associated with process recipes operated by etching chambers of an etching machine, where different process recipes correspond to different hybrid process recipe operation groups; acquiring a switching rule of different hybrid process recipe operation groups; and controlling, based on a reserved process recipe for a real-time reserved demand of a target etching chamber and a requirement of the switching rule, the etching machine to automatically switch to a target hybrid process recipe operation group associated with the reserved process recipe.

Abstract: Computerized systems and methods are provided for visualizing data in a virtual environment. A three-dimensional virtual display framework is provided within a three-dimensional virtual space, the virtual display framework defined by a three-dimensional volumetric display zone bound by a plurality of surfaces. Data is visualized in 3D within the volumetric display zone of the virtual display framework. Select information is also displayed on at least one of the surfaces of the virtual display framework, where the select information is relevant to the data visualized. In addition, one or more display parameters can be altered in response to hand motions of the user captured to customize display of the virtual display framework. Altering the display parameters is adapted to adjust at least one of the three-dimensional visualization of the data within the volumetric display zone or the display of the select information on the at least one surface.

Abstract: A method for evaluating a Hot Carrier Injection (HCI) effect of a device is provided. The method includes, a ratio of a substrate current to a drain current of a first device at different gate-source voltages is acquired, and recorded as a first current ratio; a ratio of a substrate current to a drain current of a second device at different gate-source voltages is acquired, and recorded as a second current ratio, the second device is subjected to process parameter adjustment or device parameter adjustment relative to the first device; and an influence of the process parameter adjustment or the device parameter adjustment on an HCI effect of the device is determined based on the second current ratio and the first current ratio.

Abstract: Apparatuses and methods including a test circuit in a scribe region between chips are described. An example apparatus includes: a first semiconductor chip and a second semiconductor chip, adjacent to one another; a scribe region between the first and second semiconductor chips; test address pads in the scribe region; and an address decoder circuit in the scribe region. The test address pads receive address signals. The address decoder provides first signals responsive to the address signals from the test address pads.

Abstract: A semiconductor device includes a substrate and a metallization layer. The substrate has an active region that includes opposite first and second edges. The metallization layer is disposed above the substrate, and includes a pair of metal lines and a metal plate. The metal lines extend from an outer periphery of the active region into the active region and toward the second edge of the active region. The metal plate interconnects the metal lines and at least a portion of which is disposed at the outer periphery of the active region.

Abstract: The present invention relates to a method for manufacturing an electrostatic chuck comprising: a base member of a metal material; and a dielectric layer, formed on an upper surface of the base member, including an electrode layer to the inside of which a DC power is applied. According to the present invention, the dielectric layer is formed of a ceramic material by using at least one selected from among a plasma spraying method and a sol-gel method, and thus can be provided with low porosity to increase in lifespan, and with high permittivity to increase in adhesion force to a substrate.

Abstract: In a control method for overlay accuracy, whether a similar layer of a present layer exists is determined first, where both the present layer and the similar layer are aligned relative to a same reference layer, and overlay accuracy requirements of both the present layer and the similar layer are relative to the reference layer; if so, an overlay error compensation value of a present batch of wafers at the present layer is determined according to an overlay error value of the present batch of wafers at the similar layer and/or an overlay error value of a previous batch of wafers at the similar layer; and a photoetching process is performed on the present layer of the present batch of wafers by means of the overlay error compensation value of the present batch of wafers at the present layer.

Abstract: A method and a system for processing optical lenses in which the lenses are conveyed to individual processing apparatuses or processing lines corresponding to an assignment. The assignment takes into consideration maintenance that is due.

Abstract: The present disclosure provides a system for monitoring unstructured environments. A predetermined path can be determined according to an assignment of geolocations to one or more agronomically anomalous target areas, where the one or more agronomically anomalous target areas are determined according to an analysis of a plurality of first images that automatically identifies a target area that deviates from a determination of an average of the plurality of first images that represents an anomalous place within a predetermined area, where the plurality of first images of the predetermined area are captured by a camera during a flight over the predetermined area. A camera of an unmanned vehicle can capture at least one second image of the one or more agronomically anomalous target areas as the unmanned vehicle travels along the predetermined path.

Abstract: Processing methods may be performed to form a fan-out interconnect structure. The methods may include forming a semiconductor active device structure overlying a first substrate. The semiconductor active device structure may include first conductive contacts. The methods may include forming an interconnect structure overlying a second substrate. The interconnect structure may include second conductive contacts. The methods may also include joining the first substrate with the second substrate. The joining may include coupling the first conductive contacts with the second conductive contacts. The interconnect structure may extend beyond the lateral dimensions of the semiconductor active device structure.

Abstract: In a workpiece production method a plurality of nominally similar workpieces are produced in a production process on one production machine. The order or time of production of some of the workpieces on the production machine is recorded. Some of the workpieces recorded are measured at two or more inspection stations. Dimensions or points of one workpiece are measured at one of the inspection stations, and corresponding dimensions or points of another of the workpieces are measured at another of the inspection stations. The results of the measurements of corresponding dimensions or points made at the two or more inspection stations are analysed together, taking account of the order or time of production of the workpieces. An output signal is produced based on the analysing of the results together. The output signal indicates performance of the production machine or of one or more of the inspection stations.

Abstract: Systems and methods are provided for identifying relationships between defects. The system may obtain defect items and associated information. Defect items may be compared to one another based on their attributes to determine how related they are. According to the comparisons, defect items may be grouped together into issue items for further analysis by a user. The system may further update a defect comparison model according to user interaction with defect items.

Abstract: A server for knowledge recommendation for defect review. The server includes a processor electronically coupled to an electronic storage device storing a plurality of knowledge files related to wafer defects. The processor is configured to execute a set of instruction to cause the server to: receive a request for knowledge recommendation for inspecting an inspection image from a defect classification server; search for a knowledge file in the electronic storage device that matches the inspection image; and transmit the search result to the defect classification server.

Abstract: A method for recommending a route includes obtaining a first start point and a first end point relating to a road network. The method also includes obtaining a route recommendation model. The method further includes determining a recommendation route from the first start point to the first end point based on the route recommendation model.

Abstract: A method for ascertaining an explanation map of an image, in which all those pixels of the image are changed which are significant for a classification of the image ascertained with the aid of a deep neural network. The explanation map is selected in such a way that a smallest possible subset of the pixels of the image are changed, and the explanation map preferably does not lead to the same classification result as the image when it is supplied to the deep neural network for classification. The explanation map is selected in such a way that an activation caused by the explanation map does not essentially exceed an activation caused by the image in feature maps of the deep neural network.

Abstract: Methods of determining information about a patterning process. In a method, measurement data from a metrology process applied to each of a plurality of metrology targets on a substrate is obtained. The measurement data for each metrology target includes at least a first contribution and a second contribution. The first contribution is from a parameter of interest of a patterning process used to form the metrology target. The second contribution is from an error in the metrology process. The method further includes using the obtained measurement data from all of the plurality of metrology targets to obtain information about an error in the metrology process, and using the obtained information about the error in the metrology process to extract a value of the parameter of interest for each metrology target.

Abstract: Methods and apparatus for determining a subset of a plurality of relationships between a plurality of parameters describing operation of a lithographic apparatus, the method comprising: determining a first set of data describing first relationships between a plurality of parameters of a reference apparatus; based on one or more measurements, determining a second set of data describing second relationships between the plurality of parameters of the reference or a further apparatus; comparing the first set of data and the second set of data; and selecting from the second set of data a subset of the second relationships based on differences between the first set of data and the second set of data.

Abstract: A substrate working machine including: a conveyance device configured to convey a substrate; a holding device configured to hold the substrate conveyed to a work position by the conveyance device; and a control device configured to control operation of the conveyance device, wherein the control device is configured to control the operation of the conveyance device such that the substrate is conveyed at a conveyance speed calculated based on a preset setting time and a conveyance distance of the substrate from the work position by the conveyance device or a conveyance distance of the substrate to the work position by the conveyance device.

Abstract: A vapor deposition mask includes a mask main body and a support joined to the mask main body. The mask main body has a first alignment mark whereas the support has a second alignment mark. The first alignment mark and the second alignment are provided at such positions as to overlap with each other in plan view, and either one of the alignment marks is larger than the other of the alignment marks.

Abstract: The described technology relates to scheduling jobs of a plurality of types in an enterprise web application. A processing system configures a job database having a plurality of job entries, and concurrently executes a plurality of job schedulers independently of each other. Each job scheduler is configured to schedule for execution jobs in the jobs database that are of a type different from types of jobs others of the plurality of job schedulers are configured to schedule. The processing system also causes performance of jobs scheduled for execution by any of the plurality of schedulers. Method and computer readable medium embodiments are also provided.

Abstract: A method and computer program product for monitoring one or more processes occurring during a first portion of a multi-portion recipe being executed on a processing device to obtain data concerning at least of portion of the one or more processes. At least a portion of the data is stored. The availability of the at least a portion of the data is enabled to one or more processes occurring during a second portion of the multi-portion recipe.

Abstract: A method of handling integrated circuit dies with defects is provided. After forming a plurality of dies on one or more silicon wafers, test equipment may be used to identify defects on the dies and to create corresponding defect maps. The defect maps can be combined to form an aggregate defect map. Circuit design tools may create keep-out zones from the aggregate defect map and run learning experiments on each die, while respecting the keep-out zones, to compute design metrics. The circuit design tools may further create larger keep-out zones and run additional learning experiments on each die while respecting the larger keep-out zones to compute additional design metrics. The dies can be binned into different Stock Keeping Units (SKUs) based on one or more of the computed design metrics. Circuit design tools automatically respect the keep-out regions for these dies to program them correctly in the field.

Abstract: A method includes receiving, into a measurement tool, a substrate having a material feature, wherein the material feature is formed on the substrate according to a design feature. The method further includes applying a source signal on the material feature, collecting a response signal from the material feature by using the measurement tool, and with a computer connected to the measurement tool, calculating a simulated response signal from the design feature. The method further includes, with the computer, in response to determining that a difference between the collected response signal and the simulated response signal exceeds a predetermined value, causing the measurement tool to re-measure the material feature.

Abstract: A yield-rate assessment apparatus for a manufacture system including a plurality of machines, each machine participating in one or more manufacture steps of a batch of products in the manufacture system, performs for each machine: calculating a bad-piece expectation value and a quantity of potential bad pieces at each corresponding manufacture step based on a quantity of bad pieces detected after the last one of the manufacture steps is finished and an initial yield rate of the current machine; calculating a good-piece expectation value based on a quantity of good pieces detected after the last one of the manufacture steps is finished and a summation of all quantities of potential bad pieces calculated for the current machine; and assessing a yield rate according to the good-piece expectation value calculated for the current machine and a summation of the bad-piece expectation value calculated for the current machine at each corresponding step.

Abstract: The present application provides a method for inspecting a display panel and an inspection apparatus. Wherein the method for inspecting the display panel including the following steps: setting substrate random sampling parameters in a manufacturing process by a manufacturing execution module, and transmitting the random sampling parameters to a production line control module; receiving and storing the random sampling parameters by the production line control module; generating a random sampling control signal and transmitting to a detector according to the random sampling parameters by the production line control module; and performing a random sampling to a substrate by the detector in accordance with the random sampling control signal.

Abstract: One or more blocks at the memory device are programed. The one or more blocks are associated with a block family and with one or more dice of a die group. A voltage offset bin associated with the die group and the block family is determined based on a subset of dice of the die group. Metadata associated with the memory device is appended to include a record associating the die group and the block family with the voltage offset bin.

Abstract: Defects on a substrate comprising electronic components can be classified with a computational defect analysis system that may be implemented in multiple stages. For example, a first stage classification engine may process metrology data to produce an initial classification of defects. A second stage classification engine may use the initial classification, along with manufacturing information and/or prior defect knowledge to output probabilities that the defects are caused by one or more potential sources.

Abstract: A data processing method includes a step of obtaining scores of time-series data by comparing the time-series data with reference data in order to process time-series data acquired in a substrate processing apparatus having one or more processing units, a step of classifying the scores into a plurality of levels, and a step of displaying an evaluation result screen including a graph showing an occurrence rate of each level of the scores, the number of occurrences of each level, and a graph showing temporal change in the number of occurrences of a worst level of the scores when substrates have been processed through a predetermined method with respect to the processing units. Accordingly, a data processing method through which a state of the substrate processing apparatus can be easily ascertained is provided.

Abstract: Wafer inspection with stable nuisance rates and defect of interest capture rates are disclosed. This technique can be used for discovery of newly appearing defects that occur during the manufacturing process. Based on a first wafer, defects of interest are identified based on the classified filtered inspection results. For each remaining wafer, the defect classifier is updated and defects of interest in the next wafer are identified based on the classified filtered inspection results.

Abstract: The present disclosure provides a system for monitoring unstructured environments. A predetermined path can be determined according to an assignment of geolocations to one or more agronomically anomalous target areas, where the one or more agronomically anomalous target areas are determined according to an analysis of a plurality of first images that automatically identifies a target area that deviates from a determination of an average of the plurality of first images that represents an anomalous place within a predetermined area, where the plurality of first images of the predetermined area are captured by a camera during a flight over the predetermined area. A camera of an unmanned vehicle can capture at least one second image of the one or more agronomically anomalous target areas as the unmanned vehicle travels along the predetermined path.

Abstract: A method including: obtaining a device design pattern layout having a plurality of design pattern polygons; automatically identifying, by a computer, a unit cell of polygons in the device design pattern layout; identifying a plurality of occurrences of the unit cell within the device design pattern layout to build a hierarchy; and performing, by the computer, an optical proximity correction on the device design pattern layout by repeatedly applying an optical proximity correction designed for the unit cell to the occurrences of the unit cell in the hierarchy.

Abstract: Apparatus and method to facilitate automatic detection of a device state are disclosed herein. Selectively constraining a sensor based data set associated with one or more states of a device, wherein selectively constraining the sensor based data set includes analyzing a distribution of the sensor based data set to determine whether to constrain the sensor based data set, the sensor based data set including a first class and a second class of data values. Determining a threshold associated with the sensor based data set by selecting the threshold based on a variance between the first and second classes of the sensor based data set, wherein selecting the threshold includes using a constrained sensor based data set when the sensor based data set is determined to be constrained, and wherein the threshold indicates the data values associated with the first and second classes.

Abstract: A technique which determines an optimum die layout on a semiconductor wafer is disclosed. The technique determines the optimum die layout with a significantly reduced number of calculations compared to conventional brute force techniques. This enables the generation of the optimum die layout in a much shorter period of time, reducing design turn-around time. The optimum layout is used to process a wafer which produces the optimum number of dies.

Abstract: An electrical box comprising an adjustable voltage divider may include a housing comprising an inner surface and ribs or threads integrally formed on the inner surface of the rectangular housing. A voltage divider plate may be disposed within the housing with vertical edges of the voltage divider plate extending along and held in place between the ribs or threads integrally formed on the inner surface of the housing, the voltage divider plate dividing the housing into a high voltage area and a low voltage area. The voltage divider plate area may comprise a plurality of horizontal guide lines vertically offset from each other, and a plurality of vertical guide lines horizontally offset from each other and intersecting the plurality of horizontal score lines. Upper outer corners of the voltage divider plate may be inwardly disposed from the vertical edges of the voltage divider plate.

Abstract: A method for predicting characteristics of semiconductor devices includes collecting first data for a plurality of first characteristics from first semiconductor devices already in mass production, and collecting second data for the first characteristics and third data for a plurality of second characteristics from at least one second semiconductor device manufactured as an experimental sample before beginning the mass production. A covariance matrix is then obtained based on the first, second, and third data, and a mean vector for third semiconductor devices to be in the mass production is determined. Prediction data for third semiconductor devices is then generated based on the covariance matrix and the mean vector.

Abstract: A method of configuring a parameter determination process, the method including: obtaining a mathematical model of a structure, the mathematical model configured to predict an optical response when illuminating the structure with a radiation beam and the structure having geometric symmetry at a nominal physical configuration; using, by a hardware computer system, the mathematical model to simulate a perturbation in the physical configuration of the structure of a certain amount to determine a corresponding change of the optical response in each of a plurality of pixels to obtain a plurality of pixel sensitivities; and based on the pixel sensitivities, determining a plurality of weights for combination with measured pixel optical characteristic values of the structure on a substrate to yield a value of a parameter associated with change in the physical configuration, each weight corresponding to a pixel.

Abstract: A component testing plan considers both distinguishable components and undistinguishable components for each of the distinguishable components. In addition to distinguishable and undistinguishable components, inputs to the system include a level of customer demand, using component-based demand forecasting, and what test types are to be performed. The system then determines a set of combinatorial test options for each of the test types and a cycle time for each combinatorial test option. The system then cognitively develops a component testing plan including a listing of combinatorial test(s) of the set of combinatorial test options for each test type to be performed and how many times to perform each combinatorial test(s) on a testing machine with a known capacity in order to minimize a total cycle time for all of the test types and a number of the testing machine needed; and implementing the component testing plan on a set of test components on a production line.

Abstract: A method and associated computer program for predicting an electrical characteristic of a substrate subject to a process. The method includes determining a sensitivity of the electrical characteristic to a process characteristic, based on analysis of electrical metrology data including electrical characteristic measurements from previously processed substrates and of process metrology data including measurements of at least one parameter related to the process characteristic measured from the previously processed substrates; obtaining process metrology data related to the substrate describing the at least one parameter; and predicting the electrical characteristic of the substrate based on the sensitivity and the process metrology data.

Abstract: An IC that includes a contiguous standard cell area with a 4×3 e-beam pad that is compatible with advanced manufacturing processes and an associated e-beam testable structure.

Abstract: An IC that includes a contiguous standard cell area with a 4×3 e-beam pad that is compatible with advanced manufacturing processes and an associated e-beam testable structure.

Abstract: An IC that includes a contiguous standard cell area with a 4×3 e-beam pad that is compatible with advanced manufacturing processes and an associated e-beam testable structure.

Abstract: A technique for fine-granularity speed binning for a processing device is provided. The processing device includes a plurality of clock domains, each of which may be clocked with independent clock signals. The clock frequency at which a particular clock domain may operate is determined based on the longest propagation delay between clocked elements in that particular clock domain. The processing device includes measurement circuits for each clock domain that measure such propagation delay. The measurement circuits are replica propagation delay paths of actual circuit elements within each particular clock domain. A speed bin for each clock domain is determined based on the propagation delay measured for the measurement circuits for a particular clock domain. Specifically, a speed bin is chosen that is associated with the fastest clock speed whose clock period is longer than the slowest propagation delay measured for the measurement circuit for the clock domain.

Abstract: Techniques are provided for classifying runs of a recipe within a manufacturing environment. Embodiments monitor a plurality of runs of a recipe to collect runtime data from a plurality of sensors within a manufacturing environment. Qualitative data describing each semiconductor devices produced by the plurality of runs is determined. Embodiments characterize each run into a respective group, based on an analysis of the qualitative data, and generate a data model based on the collected runtime data. A multivariate analysis of additional runtime data collected during at least one subsequent run of the recipe is performed to classify the at least one subsequent run into a first group. Upon classifying the at least one subsequent run, embodiments output for display an interface depicting a ranking sensor types based on the additional runtime data and the description of relative importance of each sensor type for the first group within the data model.

Abstract: Method and system for secure access from a security device at a local network location to a remote network location are disclosed. At the security device having a unique identifier (UID), processor, and memory, a security software is obtained from a remote network location, the security software obtaining a personal identification number (PIN) of a user, and the UID of the security device. The PIN, the UID and the private security software are forwarded to the remote network location for generating a credential code, including encrypting the credential code. At the security device, the credential code is obtained from the remote network location, and authenticity of the PIN and the UID is verified, without communicating over a network, including decrypting the credential code. Upon verifying the authenticity of the PIN and the UID, access credentials to the remote network location are retrieved.

Abstract: The present application relates to a node task data display method. The method comprises: receiving a query instruction for node task data, the query instruction carrying a user identifier and a node identifier; querying node task data associated with the user identifier from a node task data table associated with the node identifier according to the query instruction; querying variable configuration information associated with the user identifier from a variable configuration information table associated with the node identifier; extracting a variable value corresponding to the variable configuration information from each piece of queried node task data; and displaying in order each piece of queried node task data according to the extracted variable value of each piece of node task data.

Abstract: A smart defect calibration, diagnosis, sampling system and the method thereof for manufacturing fab is provided. The intelligent defect diagnosis method includes: receiving pluralities of defect data, design layout data, analyzing the defect data, design layouts, by a Critical Area Analysis (CAA) system, selecting defect samples based on the defect classification data, selecting alarm defect and filtering false defect with pattern match with defect pattern library and frequent failure defect library, performing coordinate conversion and pattern match between defect image contour, defect image pattern, and design layout for coordinate correction, creating a CAA accuracy correction system and defect size calibration system by analyzing original defect size data and defect contour size from image analysis, evaluating the defect size using measurement uncertainty analysis with statistical analysis methods to reach the purposes of increasing CAA accuracy and Killer Defect identification rate.

Abstract: A multiple-tool parameter set configuration and misregistration measurement system and method useful in the manufacture of semiconductor devices including using a first misregistration metrology tool using a first set of measurement parameters to measure misregistration between at least two layers at multiple sites on a wafer, including a plurality of semiconductor devices, the wafer being selected from a batch of wafers including a plurality of semiconductor devices intended to be identical to corresponding semiconductor devices on all other wafers in the batch of wafers, thereby generating a plurality of first misregistration data sets, using a second misregistration metrology tool using a second set of measurement parameters to measure misregistration between the at least two layers at multiple sites on a wafer selected from the batch of wafers, thereby generating a plurality of second misregistration data sets, selecting an adjusted first set of modeled measurement parameters associated with the first mis

Abstract: A {111} plane of a substrate having a silicon crystal structure meets a top surface of the substrate to form an interconnection line on the top surface. A first stacked structure and a second stacked structure is formed on the substrate. Each of the first and the second stacked structures includes gate electrodes stacked on the substrate. A transistor is disposed on the substrate and positioned between the first stacked structure and the second stacked structure. The transistor includes a gate electrode extending in a first direction, a source region and a drain region. The source and the drain regions are disposed at both sides of the gate electrode in a second direction crossing the first direction. The interconnection line is extended at an angle with respect to the second direction.

Abstract: An IC that includes a contiguous standard cell area with a 4×3 e-beam pad that is compatible with advanced manufacturing processes and an associated e-beam testable structure.

Abstract: Systems and methods are provide herein for enabling a computing system to search and interact with service records containing natural language text to aid in the analysis of those records by: clustering terms in natural language service records of a corpus of natural language service records related to a complex system based on term definitions in a knowledgebase; associating, based on a definition for the complex system that includes a coordinate system that describes the complex system, the clustered terms with the coordinate system for the complex system; generating an issue map for a given natural language service record of the corpus, wherein the issue map identifies the clustered terms in the given natural language service record and associated locations for the clustered terms according to the coordinate system for the complex system; and associating the issue map to the given natural language service record of the corpus.