Abstract: Chalcogenide containing semiconductor devices may be formed with a gradient film between a chalcogenide film and another film. The gradient film may have its chalcogenide concentration decrease as it extends away from the chalcogenide film, while the concentration of the other film material increases across the thickness of the gradient film moving away from the chalcogenide film.

Abstract: A method and apparatus for making analog and digital electronics which includes a composite including a squishable material doped with conductive particles. A microelectromechanical systems (MEMS) device has a channel made from the composite, where the channel forms a primary conduction path for the device. Upon applied voltage, capacitive actuators squeeze the composite, causing it to become conductive. The squishable device includes a control electrode, and a composite electrically and mechanically connected to two terminal electrodes. By applying a voltage to the control electrode relative to a first terminal electrode, an electric field is developed between the control electrode and the first terminal electrode. This electric field results in an attractive force between the control electrode and the first terminal electrode, which compresses the composite and enables electric control of the electron conduction from the first terminal electrode through the channel to the second terminal electrode.

Abstract: According to one embodiment, a memory device includes a nanomaterial assembly layer, a first electrode layer and a second electrode layer. The nanomaterial assembly layer is formed of an assembly of a plurality of micro conductors via gaps between the micro conductors. The first electrode layer is provided on the nanomaterial assembly layer. The second electrode layer is provided on the first electrode layer.

Abstract: A nonvolatile memory device group includes: (A) a first insulating layer; (B) a second insulating layer that has a first concavity and a second concavity communicating with the first concavity and having a width larger than that of the first concavity and that is disposed on the first insulating layer; (C) a plurality of electrodes that are disposed in the first insulating layer and the top surface of which is exposed from the bottom surface of the first concavity; (D) an information storage layer that is formed on the side walls and the bottom surfaces of the first concavity and the second concavity; and (E) a conductive material layer that is filled in a space surrounded with the information storage layer in the second concavity.

Abstract: Methods of manufacturing non-volatile memory devices may include separating first phase-change material groups and second phase-change material groups, which have different sizes, from a target including phase-change materials and faulting a phase-change material layer on an object by using the first phase-change material groups and the second phase-change material groups.

Abstract: This invention relates to MRAM technology and new variations on MRAM array architecture to incorporate certain advantages from both cross-point and 1T-1MTJ architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor 16 is used to read the multiple MRAM cells in a segment of a column, which can be stacked vertically above one another in a plurality of MRAM array layers arranged in a “Z” axis direction.

Abstract: A resistive memory device includes a first conductive line on a substrate, a vertical selection diode comprising a nanowire or a nanotube and being arranged over the first conductive line, a resistive element including a resistive layer arranged over the vertical selection diode; and a second conductive line arranged over the resistive element.

Abstract: A method for forming a through via in a semiconductor element includes providing a semiconductor element having electronic circuitry integrated on the main side thereof. The semiconductor element further includes an etch stop layer and a conductive region, wherein the conductive region is arranged between the etch stop layer and the main side of the semiconductor element. The method also includes selectively etching a through via from a backside of the semiconductor element, opposite to the main side of the semiconductor element, to the etch stop layer and removing at least partly the etch stop layer, so that the conductive region is exposed to the backside and filling at least partly the through via with a conductive material, wherein the conductive material is electrically isolated from the semiconductor element.

Abstract: The invention is related to methods and apparatus for providing a resistance variable memory element with improved data retention and switching characteristics. According to an embodiment of the invention a resistance variable memory element is provided having at least one silver-selenide layer in between glass layers, wherein at least one of the glass layers is a chalcogenide glass, preferably having a GexSe100-x composition.

Abstract: The present invention generally relates to MEMS devices and methods for their manufacture. The cantilever of the MEMS device may have a waffle-type microstructure. The waffle-type microstructure utilizes the support beams to impart stiffness to the microstructure while permitting the support beam to flex. The waffle-type microstructure permits design of rigid structures in combination with flexible supports. Additionally, compound springs may be used to create very stiff springs to improve hot-switch performance of MEMS devices. To permit the MEMS devices to utilize higher RF voltages, a pull up electrode may be positioned above the cantilever to help pull the cantilever away from the contact electrode.

Abstract: Methods, devices, and systems associated with phase change material memory are described herein. In one or more embodiments, a method of forming a phase change material memory cell includes forming a number of memory structure regions, wherein the memory structure regions include a bottom electrode material and a sacrificial material, forming a number of insulator regions between the number of memory structure regions, forming a number of openings between the number of insulator regions and forming a contoured surface on the number of insulator regions by removing the sacrificial material and a portion of the number of insulator regions, forming a number of dielectric spacers on the number of insulator regions, forming a contoured opening between the number of insulator regions and exposing the bottom electrode material by removing a portion of the number of dielectric spacers, and forming a phase change material in the opening between the number of insulator regions.

Abstract: A multi-layer thin-film device includes thin film memory and thin film logic. The thin film memory may be programmable resistance memory, such as phase change memory, for example. The thin film logic may be complementary logic.

Abstract: A MEMS device is described that has a body with a component bonded to the body. The body has a main surface and a side surface adjacent to the main surface and smaller than the main surface. The body is formed of a material and the side surface is formed of the material and the body is in a crystalline structure different from the side surface. The body includes an outlet in the side surface and the component includes an aperture in fluid connection with the outlet.

Abstract: A nanoscale switching device exhibits multiple desired properties including a low switching current level, being electroforming-free, and cycling endurance. The switching device has an active region disposed between two electrodes. The active region contains a switching material capable of transporting dopants under an electric field. The switching material is in an amorphous state and formed by deposition at or below room temperature.

Abstract: A method of a phase-change random access memory (PCRAM) device is provided. The method includes forming a heat pad on a substrate, forming a phase-change material layer by injecting a deposition gas for a phase-change material and a reaction gas on the heat pad, where the phase-change material includes tellurium (Te), forming an upper electrode electrically connected to the phase-change material layer, where the tellurium (Te) is added at a ratio smaller than a normal chemical stoichiometric ratio of materials constituting the phase-change material layer.

Abstract: An electrically actuated device includes a first electrode and a second electrode crossing the first electrode at a non-zero angle, thereby forming a junction therebetween. A material is established on the first electrode and at the junction. At least a portion of the material is a matrix region. A current conduction channel extends substantially vertically between the first and second electrodes, and is defined in at least a portion of the material positioned at the junction. The current conduction channel has a controlled profile of dopants therein.

Abstract: A resistive memory structure, for example, phase change memory structure, includes one access device and two or more resistive memory cells. Each memory cell is coupled to a rectifying device to prevent parallel leak current from flowing through non-selected memory cells. In an array of resistive memory bit structures, resistive memory cells from different memory bit structures are stacked and share rectifying devices.

Abstract: Embodiments of the invention include methods and devices for producing light by injecting electrons from field emission cathode across a gap into nanostructured semiconductor materials, electrons issue from a separate field emitter cathode and are accelerated by a voltage across a gap towards the surface of the nanostructured material that forms part of the anode. At the nanostructure material, the electrons undergo electron-hole (e-h) recombination resulting in electroluminescent (EL) emission. In a preferred embodiment lighting device, a vacuum enclosure houses a field emitter cathode. The vacuum enclosure also houses an anode that is separated by a gap from said cathode and disposed to receive electrons emitted from the cathode. The anode includes semiconductor light emitting nano structures that accept injection of electrons from the cathode and generate photons in response to the injection of electrons.

Abstract: A micro structure includes a base member; a supporting unit disposed on a surface of the base member; a graphene unit which covers at least a portion of the supporting unit and at least a portion of an empty space adjacent to the supporting unit; and a structure unit disposed on at least a portion of the graphene unit over the supporting unit.

Abstract: A method of fabricating a programmable memory microelectronic device includes depositing onto a first electrode an intermediate layer of a material having a chalcogenide; depositing an ionizable metallic layer on the intermediate layer; irradiating with ultraviolet radiation the ionizable metallic layer so that metallic ions from the ionizable metallic layer diffuse into the intermediate layer to form a chalcogenide material containing metallic ions, and depositing a second electrode on the layer of chalcogenide material containing metallic ions obtained in the prior step. The second and third steps are repeated at least n times, where n is an integer greater than or equal to 1. The ionizable metallic layer deposited during the second step has a sufficiently small thickness that the metallic ions may be diffused totally during the irradiation (third) step.

Abstract: Disclosed herein is a resistive switching device having an amorphous layer comprised of an insulating silicon-containing material and a conducting material. The amorphous layer may be disposed between two or more electrodes and be capable of switching between at least two resistance states. Circuits and memory devices including resistive switching devices are also disclosed, and a composition of matter involving an insulating silicon-containing material and a conducting material comprising between 5 and 40 percent by molar percentage of the composition is disclosed herein as well. Also disclosed herein are methods for switching the resistance of an amorphous material.

Abstract: A phase changeable memory device is manufactured by forming at least one insulating layer on a substrate. A preliminary first electrode is formed on the insulating layer. The preliminary first electrode is partially etched to form a first electrode electrically connected to the substrate. After the preliminary first electrode is formed, both sidewalls of the preliminary first electrode are partially etched isotropically to form a first electrode having a uniform width and height. A phase changeable material layer pattern and a second electrode are subsequently formed on the first electrode. Related devices also are described.

Abstract: A phase change memory formed by a plurality of phase change memory devices having a chalcogenide memory region extending over an own heater. The heaters have all a relatively uniform height. The height uniformity is achieved by forming the heaters within pores in an insulator that includes an etch stop layer and a sacrificial layer. The sacrificial layer is removed through an etching process such as chemical mechanical planarization. Since the etch stop layer may be formed in a repeatable way and is common across all the devices on a wafer, considerable uniformity is achieved in heater height. Heater height uniformity results in more uniformity in programmed memory characteristics.

Abstract: A memristor having an active region includes a first electrode. The first electrode comprises a nanostructure formed of at least one metallic single walled nanotube. The memristor also includes a second electrode formed of at least one metallic single walled nanotube. The second electrode is positioned in a crossed relationship with respect to the first electrode. The memristor further includes a switching material positioned between the first electrode and the second electrode, in which the active region is configured to form in the switching material at a cross point of the first electrode and the second electrode.

Abstract: A memristor having an active region having a first electrode, a second electrode, and a nanostructure connecting the first electrode with the second electrode. The nanostructure includes a generally insulating material configured to have an electrically conductive channel formed in the material. The nanostructure forms the active region and has a length and a thickness, where the length is substantially equivalent to a distance extending from the first electrode to the second electrode along the nanostructure and the thickness is a distance across the nanostructure substantially perpendicular to the length of the nanostructure. The length of the nanostructure is substantially greater than the thickness of the nanostructure.

Abstract: Small phase change memory cells may be formed by forming a segmented heater over a substrate. A stop layer may be formed over the heater layer and segmented with the heater layer. Then, sidewall spacers may be formed over the segmented heater to define an aperture between the sidewall spacers that may act as a mask for etching the stop layer over the segmented heater. As a result of the etching using the sidewall spacers as a mask, sublithographic pore may be formed over the heater. Phase change material may be formed within the pore.

Abstract: A method for fabricating a phase change memory pore cell that includes forming a bottom electrode, forming a dielectric layer on the bottom electrode, and forming a sacrificial layer on the dielectric layer. The method further includes selectively etching portions of the sacrificial layer and the dielectric layer to define a pore extending through the sacrificial layer and the dielectric layer, depositing phase change material on the sacrificial layer and into the pore and removing the phase change material formed outside the pore, removing the sacrificial layer to expose the pore, the pore being vertically aligned, and forming a top electrode over the pore.

Abstract: A phase change memory element and method of forming the same. The memory element includes first and second electrodes. A first layer of phase change material is between the first and second electrodes. A second layer including a metal-chalcogenide material is also between the first and second electrodes and is one of a phase change material and a conductive material. An insulating layer is between the first and second layers. There is at least one opening in the insulating layer providing contact between the first and second layers.

Abstract: Microelectromechanical systems (MEMS) microphone devices and methods for packaging the same include a package housing, an interior lid, and an integrated MEMS microphone die. The package housing includes a sound port therethrough for communicating sound from outside the package housing to an interior of the package housing. The interior lid is mounted to an interior surface of the package housing to define an interior lid cavity, and includes a back volume port therethrough. The MEMS microphone die is mounted on the interior lid over the back volume port, and includes a movable membrane. The back volume port is configured to allow the interior lid cavity and the MEMS movable membrane to communicate, thereby increasing the back volume of the MEMS microphone die and enhancing the sound performance of the packaged MEMS microphone device.

Abstract: According to one embodiment, a semiconductor memory device comprises a substrate, a lower electrode, a variable resistance film, and an upper electrode. The lower electrode is on the substrate. The variable resistance film is on the lower electrode and stores data. The upper electrode is on the variable resistance film. The variable resistance film comprises a first film, and a second film. The first film is on a side of at least one of the upper electrode and the lower electrode and contains a metal. The second film is between the first film and the other electrode and contains the metal and oxygen. A composition ratio [O]/[Me] of oxygen to the metal in the second film is lower than a stoichiometric ratio and higher than the composition ratio [O]/[Me] in the first film. The composition ratio [0]/[Me] changes between the first film and the second film.

Abstract: The present invention discloses a micrometer-scale grid structure based on single crystal silicon consists of periphery frame 1 and grid zone 2. The periphery frame 1 is rectangle, and grid zone 2 has a plurality of mesh-holes 3 distributing in the plane of grid zone 2. The present invention also provides a method for manufacturing a micrometer-scale grid structure based on single crystal silicon. According to the present invention thereof, the contradiction between demand of broad deformation space for sensor and actuator and the limit of the thickness of sacrifice layer is solved. Furthermore, the special requirement of double-side transparence for some optical sensor is met.

Abstract: Phase transitions (such as metal-insulator transitions) are induced in oxide structures (such as vanadium oxide thin films) by applying an electric field. The electric field-induced phase transitions are achieved in VO2 structures that scale down to nanometer range. In some embodiments, the optical and/or dielectric properties of the oxide structures are actively tuned by controllably varying the applied electric field. Applying a voltage to a single-phase oxide material spontaneously leads to the formation of insulating and conducting regions within the active oxide material. The dimensions and distributions of such regions can be dynamically tuned by varying the applied electric field and/or the temperature. In this way, oxide materials with dynamically tunable optical and/or dielectric properties are created.

Abstract: An inductor includes an inductor wiring made of a metal layer and having a spiral planar shape. In a cross-sectional shape in a width direction of the inductor wiring, the inductor wiring has a larger film thickness at least in its inner side end than in its middle part.

Abstract: A phase change memory device capable of increasing a sensing margin and a method for manufacturing the same. The phase change memory device includes a semiconductor substrate formed with a device isolation structure which defines active regions; first conductivity type impurity regions formed in surfaces of the active regions and having the shape of a line; a second conductivity type well formed in the semiconductor substrate at a position lower than the device isolation structure; a second conductivity type ion-implantation layer formed in the semiconductor substrate at a boundary between a lower end of the device isolation structure and the semiconductor substrate; a plurality of vertical PN diodes formed on the first conductivity type impurity regions; and phase change memory cells formed on the vertical PN diodes.

Abstract: A method is disclosed for manufacturing a sealed cavity in a microelectronic device, comprising forming a sacrificial layer at least at locations where the cavity is to be provided, depositing a membrane layer over the top of the sacrificial layer, patterning the membrane layer in at least two separate membrane layer blocks, removing the sacrificial layer through the membrane layer, and sealing the cavity by sealing the membrane layer, wherein patterning the membrane layer is performed after removal of the sacrificial layer.

Abstract: A resistive memory device includes a plurality of resistive units, each resistive unit including: a lower electrode formed over a substrate; a resistive layer formed over the lower electrode; and an upper electrode formed over the resistive layer, wherein edge parts of the lower and upper electrodes, which come in contact with the resistive layer, is formed with a rounding shape.

Abstract: The disclosure relates to a fabrication process of a biosensor on a semiconductor wafer, comprising steps of: making a central photosensitive zone comprising at least one pixel-type biological analysis device comprising a photosensitive layer, and a first peripheral zone surrounding the central photosensitive zone, comprising electronic circuits. The first peripheral zone is covered by a hydrophilic coating, and the central photosensitive zone is covered with a hydrophobic coating. A barrier of a bio-compatible resin is formed on the second peripheral zone.

Abstract: A micro-electro-mechanical transducer (such as a cMUT) is disclosed. The transducer has a base, a spring layer placed over the base, and a mass layer connected to the spring layer through a spring-mass connector. The base includes a first electrode. The spring layer or the mass layer includes a second electrode. The base and the spring layer form a gap therebetween and are connected through a spring anchor. The mass layer provides a substantially independent spring mass contribution to the spring model without affecting the equivalent spring constant. The mass layer also functions as a surface plate interfacing with the medium to improve transducing performance. Fabrication methods to make the same are also disclosed.

Abstract: By means of an RIE etch process for silicon (3), a pin-type structure (4,4a) without crystal defects is formed with high aspect ratio and with nano dimensions on the surface of silicon wafers without any additional patterning measures (e-beam, interference lithography, and the like) by selecting the gas components of the etch plasma in self-organization wherein, among others, a broadband antireflective behaviour is obtained that may be applicable in many fields.

Abstract: A micro-electro-mechanical system (MEMS) device includes a substrate, having a first side and second side, the second side has a cavity and a plurality of venting holes in the substrate at the second side with connection to the cavity. However, the cavity is included in option without absolute need. A structural dielectric layer has a dielectric structure and a conductive structure in the dielectric structure. The structural dielectric layer has a chamber in connection to the cavity by the venting holes. A suspension structure layer is formed above the chamber. An end portion is formed in the structural dielectric layer in fix position. A diaphragm has a first portion of the diaphragm fixed on the suspension structure layer while a second portion of the diaphragm is free without being fixed.

Abstract: This p-type silicon wafer was subjected to heat treatment to have a resistivity of 10 ?·cm or more, a BMD density of 5×107 defects/cm3 or more, and an n-type impurity concentration of 1×1014 atoms/cm3 or less at a depth of within 5 ?m from a surface of the wafer. This method for heat-treating p-type silicon wafers, the method includes the steps of: loading p-type silicon wafers onto a wafer boat, inserting into a vertical furnace, and holding in an argon gas ambient atmosphere at a temperature of 1100 to 1300° C. for one hour; moving the wafer boat to a transfer chamber and discharging the silicon wafers; and transferring to the wafer boat silicon wafers to be heat treated next, wherein after the discharge of the heat-treated silicon wafers, the silicon wafers to be heat-treated next are transferred to the wafer boat within a waiting time of less than two hours.

Abstract: A deposition apparatus includes: a first electrode for placing a processing object; a second electrode for generating plasma with the first electrode, the second electrode being opposed to the first electrode; and a heat flow control heat transfer part for drawing heat from the processing object to generate a heat flow from a central area to a peripheral area of the processing object.

Abstract: Systems and methods for detecting and monitoring Nickel-silicide process and induced failures. In a first method embodiment, a method of characterizing a Nickel-silicide semiconductor manufacturing process includes accessing a test chip including a parallel coupled chain of transistors, wherein the transistors are designed for inducing stress into Nickel-silicide features of the transistors, and for increasing a probability of a manufacturing failure of the Nickel-silicide features. A biasing voltage is applied to one terminal of the parallel coupled chain, all other terminals of the parallel coupled chain and grounded, and current is measured at each of the all other terminals of the parallel coupled chain. This process is repeated for each terminal of the parallel coupled chain. The measured currents from all possible conduction paths are compared to determine a manufacturing defect in the parallel coupled chain of transistors.

Abstract: A method of forming an integrated circuit structure includes forming an opening in a substrate, with the opening extending from a top surface of the substrate into the substrate. The opening is filled with a filling material until a top surface of the filling material is substantially level with the top surface of the substrate. A device is formed over the top surface of the substrate, wherein the device includes a storage opening adjoining the filling material. A backside of the substrate is grinded until the filling material is exposed. The filling material is removed from the channel until the storage opening of the device is exposed.

Abstract: The information recording medium of the present invention includes a recording layer whose phase can be changed by application of electrical energy. The recording layer contains, as a main component, a material consisting of Ge, Te, and Sb. The material has a composition within a region defined by point (a) (35, 35, 30), point (b) (32.5, 27.5, 40), point (c) (25, 25, 50), and point (d) (27.5, 32.5, 40) and including lines from point (a) to point (b), from point (b) to point (c), from point (c) to point (d), and from point (d) to point (a), respectively, when coordinates (Ge, Te, Sb)=(x, y, z) are plotted on a triangular coordinate system shown in FIG. 1.

Abstract: An apparatus, system, and method are provided for a vertical two-terminal nanotube device configured to capture and generate energy, to store electrical energy, and to integrate these functions with power management circuitry. The vertical nanotube device can include a column disposed in an anodic oxide material extending from a first distal end of the anodic oxide material to a second distal end of the anodic oxide material. Further, the vertical nanotube device can include a first material disposed within the column, a second material disposed within the column, and a third material disposed between the first material and the second material. The first material fills the first distal end of the column and extends to the second distal end of the column along inner walls of the column. The second material fills the first distal end of the column and extends to the second distal end of the column within the first material.

Abstract: An interconnect for transmitting an electric signal between electronic devices includes a first coupling element electromagnetically coupled to, and immediately juxtaposed to, a second coupling element. The first coupling element is mounted on and is electrically connected to a first electronic device having a first integrated circuit. The second coupling element may be mounted on and electrically connected to the first electronic device, and electrically connected to an interconnect on a second electronic device, or the second coupling element may be mounted on and electrically connected to the second electronic device.

Abstract: A phase change memory device includes a semiconductor substrate having an impurity region and an interlayer dielectric applying a tensile stress formed on the semiconductor substrate and having contact holes exposing the impurity region. Switching elements are formed in the contact holes; and sidewall spacers interposed between the switching elements and the interlayer dielectric and formed as a dielectric layer applying a compressive stress.

Abstract: A magnetic memory device includes a common line; a first write-in diode, a readout diode and a second write-in diode being connected to the common line in parallel. The magnetic memory device further includes a magnetic tunnel junction structure connected to the readout diode, first and second write-in conductors disposed at both sides of the magnetic tunnel junction structure and connected to the first and second write-in diodes, respectively and a first write-in line, a readout line and a second write-in line, which are connected to the first write-in conductor, the magnetic tunnel injection structure, and the second write-in conductor, respectively.

Abstract: A phase-change memory element includes a perovskite layer formed by a material having a perovskite structure, and a phase-change recording material layer which is formed on the perovskite layer, and changes the phase to a crystal state or amorphous state when supplied with an electric current via the perovskite layer.