Abstract: A discrete trap memory, comprising a silicon substrate layer, a bottom oxide layer on the silicon substrate layer, a Fullerene layer on the bottom oxide layer, a top oxide layer on the Fullerene layer, and a gate layer on the top oxide layer; wherein the Fullerene layer comprises spherical, elliptical or endohedral Fullerenes that act as charge traps.

Abstract: The present invention is directed to structures and methods of fabricating electromechanical memory cells having nanotube crossbar elements. Such memory cells include a substrate having transistor with a contact that electrically contacts with the transistor. A first support layer is formed over the substrate with an opening that defines a lower chamber above the electrical contact. A nanotube crossbar element is arranged to span the lower chamber. A second support layer is formed with an opening that defines a top chamber above the lower chamber, the top chamber including an extension region that extends beyond an edge of the lower chamber to expose a portion of the top surface of the first support layer. A roof layer covers the top of the top chamber and includes an aperture that exposes a portion of the extension region of the top chamber and includes a plug that extends into the aperture in the roof layer to seal the top and bottom chambers.

Abstract: Provided are a method of manufacturing nanoelectrode lines. The method includes the steps of: sequentially forming an insulating layer, a first photoresist layer, and a drop-shaped second photoresist on a substrate; disposing an imprint mold having a plurality of molding patterns over the second photoresist; applying pressure to the mold to allow the second photoresist to flow into the mold patterns; irradiating ultraviolet (UV) light onto the mold to cure the second photoresist; removing the mold from the cured second photoresist and patterning the second photoresist; patterning the first photoresist layer using the patterned second photoresist as a mask; patterning the insulating layer; and forming a metal layer between the patterned insulating layers. In this method, metal electrode lines are formed between insulating layers using an imprint lithography process, so that nanoelectronic devices can be freed from crosstalk between the metal electrode lines.

Abstract: Light-emitting device methods are disclosed.

Abstract: A method of forming an electrical interconnect, which includes a first electrode, an interlayer of a programmable material disposed over at least a portion of the first electrode, and a second electrode disposed over the programmable material at a non-zero angle relative to the first electrode. The interlayer includes a modified region having differing electrical properties than the rest of the interlayer, sandwiched at the junction of the first electrode and the second electrode. The interlayer may be exposed to a focused beam to form the modified region.

Abstract: An integrated circuit, design structures and methods of forming the integrated circuit which includes a signal pad ESD coupled to an I/O signal pad and a power supply ESD coupled to a source VDD. The signal pad ESD and the power supply ESD are integrated in a single ESD structure.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a through silicon via die having an interconnect through a silicon substrate; depositing a re-distribution layer on the through silicon via die and connected to the interconnects; mounting a structure over the through silicon via die; connecting the structure to the interconnect of the through silicon via die with a direct interconnect; and encapsulating the through silicon via die and partially encapsulating the structure with an encapsulation.

Abstract: A top-side cooled compact semiconductor package with integrated bypass capacitor is disclosed. The top-side cooled compact semiconductor package includes a circuit substrate with terminal leads, numerous semiconductor dies bonded atop the circuit substrate, numerous elevation-adaptive interconnection plates for bonding and interconnecting top contact areas of the semiconductor dies with the circuit substrate, a first member of the elevation-adaptive interconnection plates has a first flat-top area and a second member of the elevation-adaptive interconnection plates has a second flat-top area in level with the first flat-top area, a bypass capacitor, having two capacitor terminals located at its ends, stacked atop the two interconnection plate members while being bonded thereto via the first flat-top area and the second flat-top area for a reduced interconnection parasitic impedance.

Abstract: Provided is a micro-mechanical structure and method for manufacturing the same, including a hydrophilic surface on at least a part of a surface of the micro-mechanical structure, so as to prevent generation of an adhesion phenomenon in the process of removing a sacrificial layer to release the micro-mechanical, wherein the sacrificial layer comes into contact with the surface of the micro-mechanical structure.

Abstract: A method of positioning a catalyst nanoparticle that facilitates nanowire growth for nanowire-based device fabrication employs a structure having a vertical sidewall formed on a substrate. The methods include forming the structure, forming a targeted region in a surface of either the structure or the substrate, and forming a catalyst nanoparticle in the targeted region using one of a variety of techniques. The techniques control the position of the catalyst nanoparticle for subsequent nanowire growth. A resonant sensor system includes a nanowire-based resonant sensor and means for accessing the nanowire. The sensor includes an electrode and a nanowire resonator. The electrode is electrically isolated from the substrate. One or more of the substrate is electrically conductive, the nanowire resonator is electrically conductive, and the sensor further comprises another electrode. The nanowire resonator responds to an environmental change by displaying a change in oscillatory behavior.

Abstract: There is provided a distributed Bragg's reflector (DBR) comprising a substrate and an unit distributed Bragg's reflector (DBR) layer, wherein a multi-layer is laminated on the substrate. The unit DBR layer is composed of a multi-layer laminated structure of unit digital-alloy multinary compound semiconductor layer/multinary compound semiconductor layer or unit digital-alloy multinary compound semiconductor layer/unit digital-alloy multinary compound semiconductor layer. The unit digital-alloy multinary compound semiconductor layer is composed of the multi-layer laminated structure of the first layer of multinary compound semiconductor and the second layer of a different multinary compound semiconductor on said first layer. The digital-alloy distributed Bragg's reflector of the present invention has a uniform quality on the substance area and the filter and reflector having uniformly high quality can be mass produced by using the reflector.

Abstract: The present invention is directed to structures and methods of fabricating electromechanical memory cells having nanotube crossbar elements. Such memory cells include a substrate having transistor with a contact that electrically contacts with the transistor. A first support layer is formed over the substrate with an opening that defines a lower chamber above the electrical contact. A nanotube crossbar element is arranged to span the lower chamber. A second support layer is formed with an opening that defines a top chamber above the lower chamber, the top chamber including an extension region that extends beyond an edge of the lower chamber to expose a portion of the top surface of the first support layer. A roof layer covers the top of the top chamber and includes an aperture that exposes a portion of the extension region of the top chamber and includes a plug that extends into the aperture in the roof layer to seal the top and bottom chambers.

Abstract: The fabrication of integrated circuits comprising resistors having the same structure but different sheet resistances is disclosed herein. In one embodiment, a method of fabricating an integrated circuit comprises: concurrently forming a first resistor laterally spaced from a second resistor above or within a semiconductor substrate, the first and second resistors comprising a doped semiconductive material; depositing a dopant receiving material across the first and second resistors and the semiconductor substrate; removing the dopant receiving material from upon the first resistor while retaining the dopant receiving material upon the second resistor; and annealing the first and second resistors to cause a first sheet resistance of the first resistor to be different from a second sheet resistance of the second resistor.

Abstract: A method for fabricating semiconductor components with lens structures and lens support structures includes the steps of providing semiconductor substrates on a substrate, attaching a carrier to the substrate configured to support the substrate during various processes, thinning the carrier to form lens support structures having desired geometrical characteristics, singulating the substrate and the carrier such that each semiconductor substrate includes a lens support structure, and then attaching the lens structures to the support structures. Each semiconductor component includes a thinned semiconductor substrate, a support structure attached to the semiconductor substrate, and a lens structure attached to the support structure. A system for fabricating the semiconductor components includes the substrate containing the semiconductor substrates, and the carrier configured to support the wafer, to protect the semiconductor substrates and to provide the lens support structures.

Abstract: A method of making a carbon nanotube structure includes forming a plurality of carbon nanotubes and contacting the carbon nanotubes with a polymer. A solid composition is formed from the carbon nanotubes and polymer and then shaped. For example, the solid composition can be shaped into an elongated structure such as a filament, wire, rope, cable, and the like. In at least some instances, at least some, or all, of the polymer is removed from the solid composition after it is shaped.

Abstract: One embodiment of the present invention relates to method for the concurrent deposition of multiple different crystalline structures on a semiconductor body utilizing in-situ differential epitaxy. In one embodiment of the present invention a preparation surface is formed, resulting in two distinct crystalline regions, a monocrystalline silicon substrate region and an isolating layer region. A monocrystalline silicon layer and an amorphous silicon layer are concurrently formed directly onto the preparation surface in the monocrystalline silicon substrate region and the isolating layer region, respectively. Deposition comprises the formation of two or more sub-layers. The process parameters can be varied for each individual sub-layer to optimize deposition characteristics.

Abstract: A method for making the thermal electron emitter includes following steps. Providing a carbon nanotube film including a plurality of carbon nanotubes. Treating the carbon nanotube film with a solution comprising of a solvent and compound or a precursor of a compound, wherein the compound and the compound that is the basis of the precursor of a compound has a work function that is lower than the carbon nanotubes. Twisting the treated carbon nanotube film to form a carbon nanotube twisted wire. Drying the carbon nanotube twisted wire. Activating the carbon nanotube twisted wire.

Abstract: In a plasma immersion ion implantation process, the thickness of a pre-implant chamber seasoning layer is increased (to permit implantation of a succession of wafers without replacing the seasoning layer) without loss of wafer clamping electrostatic force due to increased seasoning layer thickness. This is accomplished by first plasma-discharging residual electrostatic charge from the thick seasoning layer. The number of wafers which can be processed using the same seasoning layer is further increased by fractionally supplementing the seasoning layer after each wafer is processed, which may be followed by a brief plasma discharging of the supplemented seasoning before processing the next wafer.

Abstract: An inductor includes an inductor wiring made of a metal layer and having a spiral planar shape. In a cross-sectional shape in a width direction of the inductor wiring, the inductor wiring has a larger film thickness at least in its inner side end than in its middle part.

Abstract: A capacitor includes a first lower metal layer and an insulating layer on a lower interlayer dielectric layer of a semiconductor substrate; a first upper metal layer aligned on the insulating layer to partially expose it; a first capping layer and an upper interlayer dielectric layer on the insulating layer including the first upper metal layer; a second lower metal layer connected to the first upper metal layer through the upper interlayer dielectric layer and the first capping layer; a second capping layer aligned on the upper interlayer dielectric layer including the second lower metal layer and formed with a hole for partially exposing the second lower metal layer; a pad aligned on the second capping layer and connected to the second lower metal layer; a protective layer on the second capping layer; and a second upper metal layer aligned on the second capping layer.

Abstract: In a semiconductor device having a first region formed with the inductor and a second region formed with transistors, the inductor includes a deep well region formed in the silicon substrate beneath the first and second regions, a well region formed on the deep well region in the second region, N type shield regions formed to have the same depth as the well region, and P type shield regions arranged to alternate with the N type shield regions, the transistors formed on the silicon substrate in the second region, an insulating film formed over an entire surface of the silicon substrate such that the insulating film covers the transistors, and a metal line formed on the insulating film in the first region such that the metal line corresponds to the N and P type shield regions.

Abstract: A deposition apparatus includes: a first electrode for placing a processing object; a second electrode for generating plasma with the first electrode, the second electrode being opposed to the first electrode; and a heat flow control heat transfer part for drawing heat from the processing object to generate a heat flow from a central area to a peripheral area of the processing object.

Abstract: Disclosed are embodiments of a flip-chip assembly and method using lead-free solder. This assembly incorporates mushroom-plated metal layers that fill and overflow solder resist openings on an organic laminate substrate. The lower portion of metal layer provides structural support to its corresponding solder resist opening. The upper portion (i.e., cap) of each metal layer provides a landing spot for a solder joint between an integrated circuit device and the substrate and, thereby, allows for enhanced solder volume control. The additional structural support, in combination with the enhanced solder volume control, minimizes strain on the resulting solder joints. Additionally, the cap further allows the minimum diameter of the solder joint on the substrate-side of the assembly to be larger than the diameter of the solder resist opening. Thus, the invention decouples C4 reliability concerns from laminate design concerns and, thereby, allows for greater design flexibility.

Abstract: Light-emitting device methods are disclosed.

Abstract: An embodiment generally relates a method of processing semiconductor devices. The method includes forming a semiconductor device and exposing the semiconductor device to a temperature substantially between 1175 to 1375 degrees Celsius after the formation of a gate dielectric layer. The method also includes annealing the semiconductor device for a period of time.

Abstract: The invention relates to a MEMS resonator comprising a first electrode, a movable element (48) comprising a second electrode, the movable element (48) at least being movable towards the first electrode, the first electrode and the movable element (48) being separated by a gap (46, 47) having sidewalls. According to the invention, the MEMS resonator is characterized in that the gap (46, 47) has been provided with a dielectric layer (60) on at least one of the sidewalls.

Abstract: A non-volatile passive memory element comprising on a single surface a first electrode system and a second electrode system together with an insulating system, unless the insulating system is the surface, wherein the first electrode system is insulated from the second electrode system, the first and the second electrode systems are pattern systems and at least one conductive or semi-conducting bridge is present between the first and second electrode systems, and wherein the non-volatile passive memory device is exclusive of metallic silicon and the systems and the conductive or semiconducting bridges are printable using conventional printing processes with the optional exception of the insulating system if the insulating system is the surface. A non-volatile passive memory device comprising a support and on at least one side of the support the above-mentioned non-volatile passive memory element.

Abstract: To provide a high-performance semiconductor device using an SOI substrate in which a substrate having low heat resistance is used as a base substrate, to provide a high-performance semiconductor device without performing mechanical polishing, and to provide an electronic device using the semiconductor device, planarity of a semiconductor layer is improved and defects in the semiconductor layer are reduced by laser beam irradiation. Accordingly, a high-performance semiconductor device can be provided without performing mechanical polishing. In addition, a semiconductor device is manufactured using a region having the most excellent characteristics in a region irradiated with the laser beam. Specifically, instead of the semiconductor layer in a region which is irradiated with the edge portion of the laser beam, the semiconductor layer in a region which is irradiated with portions of the laser beam except the edge portion is used as a semiconductor element.

Abstract: A catalyst particle on a substrate is exposed to reactants containing a semiconductor material in a reactor. An intrinsic semiconductor nanowire having constant lateral dimensions is grown at a low enough temperature so that pyrolysis of the reactant is suppressed on the sidewalls of the intrinsic semiconductor nanowire. Once the intrinsic semiconductor nanowire grows to a desired length, the temperature of the reactor is raised to enable pyrolysis on the sidewalls of the semiconductor nanowire, and thereafter dopants are supplied into the reactor with the reactant. A composite semiconductor nanowire having an intrinsic inner semiconductor nanowire and a doped semiconductor shell is formed. The catalyst particle is removed, followed by an anneal that distributes the dopants uniformly within the volume of the composite semiconductor nanowire, forming a semiconductor nanowire having constant lateral dimensions and a substantially uniform doping.

Abstract: A process for producing high performance organic thin film transistors in which the molecules in the organic thin film are highly ordered and oriented to maximize the mobility of current charge carriers. The uniform monolayer surface over various substrate materials so formed, result in a more reproducible and readily manufacturable process for higher performance organic field effect transistors that can be used to create large area circuits using a range of materials.

Abstract: A semiconductor substrate is shaped to have a curved surface profile by anodization. Prior to being anodized, the substrate is finished with an anode pattern on its bottom surface so as to be consolidated into a unitary structure in which the anode pattern is precisely reproduced on the substrate. The anodization utilizes an electrolytic solution which etches out oxidized portion as soon as it is formed as a result of the anodization, to thereby develop a porous layer in a pattern in match with the anode pattern. The anode pattern brings about an in-plane distribution of varying electric field intensity by which the porous layer develops into a shape complementary to a desired surface profile. Upon completion of the anodization, the curves surface is revealed on the surface of the substrate by etching out the porous layer and the anode pattern from the substrate.

Abstract: An optical device includes a base and an optical element. The base has a through hole in a center and includes leads and a resin. Each lead has an L-shaped cross-section and is formed by an inner lead extending from the center toward a peripheral edge and an outer lead connected to the inner lead and extending downward. The optical element is provided under the base so as to correspond to the through hole. Electrode pads of the optical element are connected to the leads of the base through bumps, respectively. The resin is formed so as to cover respective inner ends of the leads and respective front surfaces of the inner leads and to fill a gap between adjacent leads, and respective outer ends of the leads and respective front surfaces of the outer leads are exposed.

Abstract: A novel silicon micromirror structure for improving image fidelity in laser pattern generators is presented. In some embodiments, the micromirror is formed from monocrystalline silicon. Analytical—and finite element analysis of the structure as well as an outline of a fabrication scheme to realize the structure are given. The spring constant of the micromirror structure can be designed independently of the stiffness of the mirror-surface. This makes it possible to design a mirror with very good planarity, resistance to sagging during actuation, and it reduces influence from stress in reflectivity-increasing multilayer coatings.

Abstract: A combinatorial processing chamber and method are provided. In the method a fluid volume flows over a surface of a substrate with differing portions of the fluid volume having different constituent components to concurrently expose segregated regions of the substrate to a mixture of the constituent components that differ from constituent components to which adjacent regions are exposed. Differently processed segregated regions are generated through the multiple flowings.

Abstract: A method for manufacturing a semiconductor wafer with a strained Si layer having sufficient tensile strain and few crystal defects, while achieving a relatively simple layered structure, is provided.

Abstract: A method of forming a thin multifunction solar cell in which an electroplating process is used to form a thick metal layer to give strength and support to the solar cell. The strain of the plated thick metal layer is adjusted during the process by parameter control to compensate for the strain in the other device layers, so that the curvature of the thin device can be eliminated or otherwise controlled.

Abstract: A media for an information storage device comprises a substrate of single-crystal silicon, a buffer layer of an epitaxial single crystal insulator formed over the substrate, a bottom electrode layer of an epitaxial single crystal conductor formed over the buffer layer, a ferroelectric layer of an epitaxial single crystal ferroelectric material formed over the bottom electrode layer, and an overlayer of an epitaxial single crystal material formed over the ferroelectric layer. Dipole charges generally having a first orientation exist at an interface between the bottom electrode layer and the ferroelectric layer includes, while dipole charges generally having a second orientation opposite the first orientation exist at an interface between the ferroelectric layer and the overlayer includes.

Abstract: A liquid crystal cell article includes a layer of liquid crystal material disposed between a first polymeric substrate and a second polymeric substrate. The first polymeric substrate includes a plurality of first parallel conductive traces extending in a first direction and disposed between the layer of liquid crystal material and the first substrate, and a first release liner disposed on the first polymeric substrate. The second polymeric substrate includes a plurality of second parallel conductive traces extending in a second direction orthogonal to the first direction and disposed between the layer of liquid crystal material and the second substrate. The first polymeric substrate further includes a removable portion that is separable from the first polymeric substrate with the first release liner to expose a portion of the layer of liquid crystal material or second parallel conductive traces.

Abstract: An integrated circuit includes a first electrode, a second electrode, and resistivity changing material between the first electrode and the second electrode. The integrated circuit includes a contact contacting a bottom and a first sidewall portion of the first electrode.

Abstract: Methods of making MIM structures and the resultant MIM structures are provided. The method involves forming a top electrode layer over a bottom electrode and an insulator on a substrate and forming a top electrode by removing portions of the top electrode layer. The bottom electrode, insulator, or combination thereof is isolated from the top electrode forming process, thereby mitigating damage to the resultant metal-insulator-metal structure. The resultant MIM structure can be a portion of a resistive memory cell.

Abstract: A method and system for multi-point (e.g., double-point) GOI test that can efficiently judge failure modes by testing only two points. We can measure leakage currents at only two voltages, which are the cut points of mode A-B and B-C, instead of the whole ramped voltages to save time and cost with the same test effectiveness according to a specific embodiment. By correlating leakage current at extrinsic field to the breakdown voltage, we can also evaluate the intrinsic reliability even if the samples are not subjected to actual breakdown according to a specific embodiment.

Abstract: A two-step thermal treatment method consists of performing ion implantation in a silicon substrate of the semiconductor device. A first thermal treatment procedure is performed on the semiconductor device. A second thermal treatment procedure is consecutively performed on the semiconductor device to reduce damage produced by the ion implantation.

Abstract: A method for fabricating a trench dielectric layer in a semiconductor device is provided. A trench is formed in a semiconductor substrate and a liner nitride layer is then formed on an inner wall of the trench. A liner oxide layer formed on the liner nitride layer is nitrified in order to protect the liner nitride layer from being exposed. Subsequently, the trench is filled with one or more dielectric layers.

Abstract: The present invention relates to a method for manufacturing a polycrystalline semiconductor film that can be used for a semiconductor device. In the method, an amorphous semiconductor film is irradiated with a femtosecond laser to be crystallized. By laser irradiation using a femtosecond laser, when an amorphous semiconductor film over which a cap film is formed is crystallized with a laser, it becomes possible to perform crystallization of the semiconductor film and removal of the cap film at the same time. Therefore, a step of removing the cap film in a later step can be omitted.

Abstract: A method for selectively forming an electric conductor, the method including disposing a processing target and a metal compound in an atmosphere including a supercritical fluid, the processing target having formed thereon at least one recess for providing an electric conductor, the metal compound including a metal serving as a main component of the electric conductor, and dissolving at least part of the metal compound in the supercritical fluid, selectively introducing the metal compound dissolved in the supercritical fluid into the recess in contact with a surface of the processing target, and coagulating in the recess the metal compound introduced into the recess to precipitate the metal from the metal compound, and coagulating the metal precipitated in the recess, thereby providing the electric conductor in the recess.

Abstract: A method of manufacturing an enhancement type semiconductor probe and an information storage device having the enhancement type semiconductor probe are provided. The method involves using an anisotropic wet etching and a side-wall in which influence of process parameters upon the performance of a device is reduced to improve reliability of the device in mass-production, and factors of degrading measuring sensitivity is removed to improve the performance of the device.

Abstract: An inductor embedded in a substrate, including a substrate, a coil electrode formed by filling a metal in a spiral hole formed on the substrate, an insulation layer formed on the substrate, and an external connection pad formed on the insulation layer to be connected to the coil electrode. The inductor-embedded substrate can be used as a cap for a micro device package by forming a cavity on its bottom surface.

Abstract: The present invention relates to a method of forming an isolation layer of a semiconductor memory device. After a trench is formed by etching a semiconductor substrate, a liner insulating film is formed from a DCS-HTO material having a similar wet etch rate to that of a PSZ film that gap fills an isolation layer, and the trench is gap filled with the PSZ film. Accordingly, in a subsequent etch process for EFH control of the isolation layer, residues do not remain on sidewalls of a conductive film for a floating gate, thereby improving electrical properties of devices.

Abstract: Example embodiments may provide resistive random access memory devices and/or methods of manufacturing resistive random access memory devices. Example embodiment resistive random access memory devices may include a switching device and/or a storage node connected to the switching device. The storage node may include a stack structure including a plurality of resistance change layers separated from one another and first and second electrodes each on a side wall of the stack structure. The resistance change layers may be connected to the first and the second electrodes in parallel and/or may have different switching voltages from each other.

Abstract: A microelectronic device, a method of fabricating the device, and a system including the device. The method includes: providing a substrate including an underlying conductive layer and a polymer build-up layer overlying the underlying conductive layer; providing a passive microelectronic structure; embedding the passive structure in the polymer build-up layer of the substrate; and patterning the passive structure after embedding, patterning including over-etching the bottom electrode layer. The passive microelectronic structure being embedded includes an unpatterned bottom electrode layer; an unpatterned capacitor dielectric layer overlying the bottom electrode layer; and an unpatterned top electrode layer overlying the capacitor dielectric layer.