Abstract: A method for fabricating semiconductor components with lens structures and lens support structures includes the steps of providing semiconductor substrates on a substrate, attaching a carrier to the substrate configured to support the substrate during various processes, thinning the carrier to form lens support structures having desired geometrical characteristics, singulating the substrate and the carrier such that each semiconductor substrate includes a lens support structure, and then attaching the lens structures to the support structures. Each semiconductor component includes a thinned semiconductor substrate, a support structure attached to the semiconductor substrate, and a lens structure attached to the support structure. A system for fabricating the semiconductor components includes the substrate containing the semiconductor substrates, and the carrier configured to support the wafer, to protect the semiconductor substrates and to provide the lens support structures.

Abstract: A semiconductor device having a metal/insulator/metal (MIM) structure and a method for fabricating the same are provided. The semiconductor device includes a lower structure layer including a metal wiring; and an MIM stack on the lower structure layer; wherein the MIM stack includes a lower metal electrode film formed on a substrate including the lower structure layer, a multi-layer dielectric film including a first insulating film and a second insulating film formed on the lower metal electrode film, and an upper metal electrode film formed on the multi-layer dielectric film.

Abstract: Various semiconductor devices and method of manufacturing the same are provided. In one aspect, a method of manufacturing is provided that includes forming an insulating layer on a backside of a semiconductor chip and forming a metallic thermal interface material on the insulating layer. In another aspect, an integrated circuit is provided that includes a semiconductor chip that has a front side and a backside. An insulating layer is on the backside and a metallic thermal interface material is on the insulating layer.

Abstract: A method of fabricating an electrode of a capacitor is provided. A substrate is provided and a dielectric layer is then formed thereon. After that, one multilayer mask is formed on the dielectric layer to expose a portion of the dielectric layer, wherein the multilayer mask consists of at least two layers of materials having different etching rates respectively. The exposed dielectric layer is removed to form a trench, and then the dielectric layer is over-etched, so as to widen the inside diameter of the trench. Thereafter, a conductive layer is formed on the substrate, and thus the multilayer mask and a surface of the trench are covered with the conductive layer. The conductive layer except that in the trench is then removed so as to form the electrode of the capacitor. Therefore, it can prevent the conductive layer from generating more loss.

Abstract: An inductor formed on a semiconductor substrate is provided in the present invention. The inductor comprises a metal layer and an insulator layer. The metal layer constitutes the coil of the inductor. The insulator layer comprises at least one insulator slot, and each insulator slot is encompassed in the metal layer.

Abstract: A capacitor comprising: a metal plate a doped semiconductor plate; and a dielectric sandwiched therebetween.

Abstract: By determining at least one surface characteristic of a passivation layer stack used for forming a bump structure, the situation after the deposition and patterning of a terminal metal layer stack may be “simulated,” thereby providing the potential for using well-established bump manufacturing techniques while nevertheless significantly reducing process complexity by omitting the deposition and patterning of the terminal metal layer stack.

Abstract: A semiconductor probe having a wedge shape resistive tip and a method of fabricating the semiconductor probe is provided. The semiconductor probe includes a resistive tip that is doped with a first impurity, has a resistance region doped with a low concentration of a second impurity having an opposite polarity to the first impurity, and has first and second semiconductor electrode regions doped with a high concentration of the second impurity on both side slopes of the resistive tip.

Abstract: An image sensor formed using a method for manufacturing a planar layer in a process for forming microlenses may be used in a complementary metal oxide semiconductor (CMOS) image sensor. Embodiments provide a planar layer that can improve the operation performance of an image sensor, a manufacturing method thereof, and the image sensor including the planar layer. Embodiments relate to a planar layer located under microlenses, the planar layer including valleys of patterns having a predetermined size, which may eliminate optical cross talk between adjacent pixels.

Abstract: A semiconductor device including silicide layers with different thicknesses corresponding to diffusion layer junction depths, and a method of fabricating the same are provided. According to one aspect, there is provided a semiconductor device comprising a first semiconductor element device and a second semiconductor element device, wherein the first semiconductor element device includes a first gate electrode, first diffusion layers disposed to sandwich the first gate electrode, and having a first junction depth, and a first silicide layer disposed in the first diffusion layers and having a first thickness, and the second semiconductor element device includes a second gate electrode, second diffusion layers disposed to sandwich the second gate electrode, and having a second junction depth greater than the first junction depth, and a second silicide layer disposed in the second diffusion layers and having a second thickness greater than the first thickness.

Abstract: A chip package structure and a fabrication method thereof are disclosed herein. The fabrication method includes: providing a substrate, wherein at least a through hole penetrates through the substrate; forming a block element surrounding the through hole of the substrate; forming an adhesive element surrounding the block element; disposing a chip on the substrate to cover the through hole, wherein the chip is fixed on the substrate with the adhesive element, wherein an active surface of the chip faces toward to the through hole and a portion of the active surface exposes to the through hole; electrically connecting the active surface of the chip to the lower surface of the substrate with a electrically-connecting element; and forming an encapsulant covering the abovementioned elements.

Abstract: An image sensor and a method of manufacturing same is disclosed. The image sensor implements a reflecting film formed on a front surface of a substrate having a back-illuminated photodetector. The reflecting film operates to reflect wavelengths of light that were not received by the photodetector back to the photodetector to increase the overall sensitivity of the image detector. The reflective film is formed by layering different thicknesses of material with different indices of refraction, resulting in a high reflectance.

Abstract: A lenticular lens includes an upper plate including an upper transparent electrode and having a plurality of lens surfaces having a curved surface shape; an upper alignment film on the lens surfaces; a lower plate having a lower transparent electrode and a lower alignment film; and a liquid crystal layer between the upper plate and the lower plate to be driven by an electric field applied by the upper transparent electrode and the lower transparent electrode.

Abstract: By performing a wet chemical process after etching a via, contaminations may be removed and a thin passivation layer may be formed that may then be readily removed in a subsequent sputter etch process for forming a barrier/adhesion layer. In a particular embodiment, the wet chemical process may be performed on the basis of fluoric acid and triazole or a compound thereof.

Abstract: The present invention is directed to a structure comprised of alternating layers of metal and sacrificial material built up using standard CMOS processing techniques, a process for building such a structure, a process for fabricating devices from such a structure, and the devices fabricated from such a structure. In one embodiment, a first metal layer is carried by a substrate. A first sacrificial layer is carried by the first metal layer. A second metal layer is carried by the sacrificial layer. The second metal layer has a portion forming a micro-machined metal mesh. When the portion of the first sacrificial layer in the area of the micro-machined metal mesh is removed, the micro-machined metal mesh is released and suspended above the first metal layer a height determined by the thickness of the first sacrificial layer. The structure may be varied by providing a base layer of sacrificial material between the surface of the substrate and the first metal layer.

Abstract: A method for fabricating copper wiring of a semiconductor device comprises forming a deposition stop time detection pattern having two trench structures positioned with a predetermined distance from each other on a dielectric substrate; positioning a deposition stop time detection apparatus having a plurality of detection electrodes and a guide device above the deposition stop time detection pattern; depositing copper on the substrate; and stopping deposition of the copper by an electric signal being generated when the two detection electrodes are electrically connected by the copper deposited in the two trench structure.

Abstract: Improved methods and apparatus are provided for the handling and testing of semiconductor devices. One embodiment comprises a die carrier for one or more semiconductor dice having very fine pitch electrical I/O (input/output) elements. The semiconductor dice are temporarily attached to the die carrier in singulated form to enable testing the dice with conventional contact technology. The die carrier may include a flex circuit base substrate and a rigid support frame. Further embodiments comprise materials and methods for attaching the semiconductor dice to the die carrier and for providing a temporary electrical connection with the semiconductor dice during testing. Exemplary materials for providing the temporary electrical connection may comprise a conductive film or tape, a conductive or conductor-filled epoxy, resin or RTV adhesive-based materials, a water-soluble material impregnated with a conductive filler or non-reflowed solder paste.

Abstract: A method and an apparatus for sorting between actual and perceived errors related to processing of semiconductor wafers. A plurality of semiconductor wafers are processed. Fault data relating to the processed semiconductor wafers is acquired. A trend associated with the fault data is determined. A determination is made whether the fault data relates to an actual fault associated with the semiconductor wafers or to a calibration error, based upon the trend. A component is notified of the calibration error in response to the determination that the fault data relates to the calibration error.