Abstract: A substrate processing system includes an upper chamber and a gas delivery system to supply a gas mixture to the upper chamber. An RF generator generates plasma in the upper chamber. A lower chamber includes a substrate support. A dual ion filter is arranged between the upper chamber and the lower chamber. The dual ion filter includes an upper filter including a first plurality of through holes configured to filter ions. A lower filter includes a second plurality of through holes configured to control plasma uniformity.

Abstract: An apparatus for testing a package-on-package type semiconductor package includes an upper test socket on which an upper package is mounted, the upper test socket being mounted on a pusher and connected to the lower package; a lower test socket mounted on a tester and connected to the lower package; and an adsorption pad coupled to the pusher and configured to adsorb and pressurize the lower package using a vacuum pressure, wherein the adsorption pad comprises a body part having a vacuum pressure passage formed therein; and an adsorption part having an adsorption hole corresponding to the vacuum pressure passage, and the body part is attached on a central portion of an upper surface of the adsorption part and an outer oil overflow-preventing part configured to trap silicon oil eluted from the body part is formed at an outer periphery the adsorption part.

Abstract: In a lithographic process, product units such as semiconductor wafers are subjected to lithographic patterning operations and chemical and physical processing operations. Alignment data or other measurements are made at stages during the performance of the process to obtain object data representing positional deviation or other parameters measured at points spatially distributed across each unit. This object data is used to obtain diagnostic information by performing a multivariate analysis to decompose a set of vectors representing the units in the multidimensional space into one or more component vectors. Diagnostic information about the industrial process is extracted using the component vectors. The performance of the industrial process for subsequent product units can be controlled based on the extracted diagnostic information.

Abstract: The present application discloses a method for preparing a semiconductor device including an electronic fuse control circuit. The method includes providing a chip including an electronic fuse control circuit, wherein the electronic fuse control circuit includes a program voltage pad, a fuse element, a latch, a plurality of resistor selection pads, and a plurality of bonding option units. The method further includes providing a substrate including a first voltage bonding pad and a plurality of second voltage bonding pads, disposing the chip on the substrate, bonding the first voltage bonding pad to the program voltage pad, and bonding at least one of the plurality of second voltage bonding pads to at least one of the plurality of resistor selection pads.

Abstract: A semiconductor package includes a substrate, a first insulation layer, a conductive pad, a second insulation layer and a conductive trace. The first insulation layer is formed on the substrate and having a first through hole. The conductive pad is formed on the substrate through the first through hole. The second insulation layer has a first surface and a second through hole, wherein the second through hole extends to the conductive pad from the first surface. The conductive trace has a second surface and is connected to the conductive pad through the second through hole. The entire of the first surface is in the same level, and the entire of the second surface is in the same level.

Abstract: An etching method for manufacturing a substrate structure having a thick electrically conductive layer, and a substrate structure having a thick electrically conductive layer are provided.

Abstract: The present disclosure provides a semiconductor structure having a test structure. The semiconductor structure includes a wafer and a test structure disposed on the wafer. The test structure includes a first device having a first source/drain layer and a first gate layer disposed above the first source/drain layer; a second device, having a second source/drain layer and a second gate layer disposed above the second source/drain layer, the second gate layer connected to the first gate layer; a third device, disposed adjacent to the first device and having a third source/drain layer. The first gate layer is disposed above the third source/drain layer, and the first gate layer is disposed along a first direction and the second gate layer is disposed along a second direction orthogonal to the first direction.

Abstract: The present disclosure provides a manufacturing method of a package device, which includes providing a carrier substrate, a first conductive layer, and a release layer, where the carrier substrate has a device region and a peripheral region, and the first conductive layer and the release layer are disposed on the carrier substrate. The method further includes forming a second conductive layer on the release layer in the device region, where at least one of the first and second conductive layers includes a first pad in the peripheral region. The second conductive layer includes a second pad electrically connected to the first pad through the first conductive layer. The method also includes performing an inspection step to provide an input signal to one of the first and second pads, and to receive an output signal from another of the first and second pads.

Abstract: Disclosed is a method for testing a semiconductor element. The method comprises forming at least one redistribution layer on a chip, utilizing the at least one redistribution layer to test an array of semiconductor elements on the chip, and removing the at least one redistribution layer from the chip, wherein the length of each semiconductor element is between 2-150 ?m and the width of each semiconductor element is between 2-150 ?m.

Abstract: A method of manufacturing a photovoltaic product (1) with a plurality of serially interconnected photovoltaic cells (1A, 1B) is disclosed that comprises depositing a stack with a bottom electrode layer (12), a top electrode layer (16) and a photovoltaic layer (14) arranged between said first and said top electrode layer, the bottom electrode layer and the photovoltaic layer having an interface layer (13). The method further comprises partitioning said stack into respective lateral portions associated with respective photovoltaic cells (1A, 1B), with a boundary region (1AB) between each photovoltaic cell (1A) and a subsequent photovoltaic cell (1B), and serially interconnecting mutually subsequent photovoltaic cells in a boundary region. Partitioning includes forming one or more trenches (20; 22; 23) extending through the top electrode layer and the photovoltaic layer to expose the bottom electrode layer, with at least an irradiation sub-step and subsequent thereto a mechanical fragment removal sub-step.

Abstract: A method of selectively transferring micro devices from a donor substrate to contact pads on a receiver substrate. Micro devices being attached to a donor substrate with a donor force. The donor substrate and receiver substrate are aligned and brought together so that selected micro devices meet corresponding contact pads. A receiver force is generated to hold selected micro devices to the contact pads on the receiver substrate. The donor force is weakened and the substrates are moved apart leaving selected micro devices on the receiver substrate. Several methods of generating the receiver force are disclosed, including adhesive, mechanical and electrostatic techniques.

Abstract: The present application discloses a test structure, a substrate and a method for manufacturing the substrate. The substrate includes a stacked substratum, a metal layer and an insulating layer; first via holes and second via holes disposed in different areas and passing through the insulating layer, and first transparent electrodes and second transparent electrodes disposed in different via holes and connected with the metal layer. The first via holes and the second via holes are formed through the same manufacture procedure, and the first transparent electrodes and the second transparent electrodes are formed through the same manufacture procedure.

Abstract: An apparatus with micro devices includes a circuit substrate, at least one micro device, and at least one light guide structure. The micro device is disposed on the circuit substrate. The micro device has a top surface and a bottom surface opposite to each other, a peripheral surface connected with the top surface and the bottom surface, a first-type electrode, and a second-type electrode. The light guide structure is disposed on the circuit substrate and is not in direct contact with the first-type electrode and the second-type electrode. The light guide structure includes at least one connecting portion and at least one holding portion. The connecting portion is disposed on an edge of the top surface of the micro device. An orthographic projection area of the light guide structure on the top surface is smaller than an area of the top surface.

Abstract: A semiconductor device includes a bottom electrode, a top electrode, a sidewall spacer, and a data storage element. The sidewall spacer is disposed aside the top electrode. The data storage element is located between the bottom electrode and the top electrode, and includes a ferroelectric material. The data storage element has a peripheral region which is disposed beneath the sidewall spacer and which has at least 60% of ferroelectric phase. A method for manufacturing the semiconductor device and a method for transforming a non-ferroelectric phase of a ferroelectric material to a ferroelectric phase are also disclosed.

Abstract: The semiconductor inspecting method includes following steps. First, a first position of a probe needle from above is defined by adopting a vision system of a semiconductor inspecting system. Then, a first relative vertical movement between the probe needle and the pad is made by adopting a driving system of the semiconductor inspecting system. Thereafter, a minimum change in position of the probe needle corresponding to the first position is recognized by adopting the vision system of the semiconductor inspecting system. Next, the first relative vertical movement is stopped by adopting the driving system of the semiconductor inspecting system.

Abstract: The present invention provides a method for calculating the liquid-solid interface morphology during growth of the ingot. The method comprises providing a wafer, selecting plural sampling locations on the wafer and detecting electrical resistivity at the plural sampling locations, calculating height differences between the sampling locations based on the detected electrical resistivity, and illustrating the morphology of the liquid-solid interface based on the calculated height differences. The method of the invention has advantages including easy operation and low cost.

Abstract: Provided is a multi-layered anisotropic conductive adhesive including an upper conductive adhesive layer, a conductive fabric layer with two sides and a lower conductive adhesive layer, wherein one side of the conductive fabric layer is plated with metal. In the application of a flexible printed circuit, reinforced parts, formed by laminating multi-layered anisotropic conductive adhesive with steel or polyimide-type stiffener, can effectively prevent the deformation of installed parts due to warping, and ensure the good hole filling, good direct grounding effect, and good shielding performance. Therefore, the multi-layered anisotropic conductive adhesive has good electrical properties, good adhesive strength, better tin soldering, reliability and flame resistant. Also provided is a method of producing the multi-layered anisotropic conductive adhesive.

Abstract: A method for packaging chips includes: providing a filter wafer and a plurality of substrates to be packaged, each substrate to be packaged being provided with one or more first pads; flip-chip bonding the substrates to be packaged on the filter wafer; molding the substrates to be packaged to form a molded layer on the substrates to be packaged, the substrates to be packaged, the molded layer, and the filter wafer forming a molded structure, each substrate to be packaged, a portion of the molded layer formed on the substrate to be packaged, and the filter wafer together enclosing a cavity; exposing the first pads out of the molded layer; and cutting the molded structure into a plurality of particle chips.

Abstract: A single photon avalanche diode (SPAD) device comprises: a silicon layer; an active region in said silicon layer for detecting incident light; and a blocking structure overlapping said active region for blocking incident light having a wavelength at least in the range of 200 nm to 400 nm, so that light having said wavelength can only be detected by said SPAD device when incident upon a region of said silicon layer outside of said active region.

Abstract: Methods, computer program products and/or systems are provided that perform the following operations: obtaining digital replica models for equipment at an industrial location; receiving data feeds associated with the equipment; simulating operations of the equipment based on the digital replica models and the data feeds; predicting one or more events associated with areas within the industrial location based, at least in part, on the simulating of operations of the equipment; and determining one or more mitigation procedures based on the one or more predicted events.

Abstract: Method for fabricating a semiconductor structure is provided. First features are formed in a first product region of each die area and in a material layer through a first mask. Second features are formed in a second product region of each die area and in the material layer through a second mask. Third features are formed in a third product region of each die area and in the material layer through a third mask. Fourth features are formed in a fourth product region of each die area and in the material layer through a fourth mask. Fifth features are formed in an alignment region between the first, second, third and fourth product regions of each die area and in the material layer through the first, second, third and fourth masks. The first product region is free of the second, third, and fourth features.

Abstract: Passive semiconductor components and switches may be formed directly in, on, about, or across each of two or more semiconductor dies included in a stacked-die semiconductor package. At least some of the passive semiconductor components and/or switches may be formed in redistribution layers operably coupled to corresponding semiconductor dies included in the stacked-die semiconductor package. The switches may have multiple operating states and may be operably coupled to the passive semiconductor components such that one or more passive semiconductor components may be selectively included in one or more circuits or excluded from one or more circuits. The switches may be manually controlled or autonomously controlled using one or more control circuits. The one or more control circuits may receive one or more input signals containing host system information and/or data that is used to adjust or set the operating state of at least some of the switches.

Abstract: A current source circuit and an LED driving circuit applying the same. A current at an output terminal of an operational transconductance amplifier is shunted based on a first control signal that includes duty cycle information, or an input signal at at least one input terminal of the operational transconductance amplifier is controlled to be switched between different voltage signals based on the first control signal, so as to adjust an output current of a current adjustment circuit. A driving voltage for driving a current generation circuit is adjusted based on the output current. Thereby, a driving current generated by the current source circuit is correlated with the duty cycle information. An amplitude modulation circuit used, a low-pass filter and the like for processing the first control signal are not used, effectively simplifying circuit design and improving system efficiency.

Abstract: A semiconductor device inspection apparatus according to embodiments comprises: an action unit that generates an internal stress in a predetermined direction in a semiconductor device; a stress controller that controls a magnitude of the internal stress generated in the semiconductor device by the action unit; a probe electrically connected to the semiconductor device; a probe controller that supplies a current to the semiconductor device via the probe; and a controller that screens the semiconductor device based on a first current flowing through the semiconductor device via the probe while the internal stress is not generated in the semiconductor device and a second current flowing through the semiconductor device via the probe while the action unit generates the internal stress in the semiconductor device.

Abstract: An electrostatic chuck includes a plurality of electrodes configured to generate an electrostatic force for attracting and holding a substrate and a surface on which the substrate is to be mounted. The electrodes are arranged respectively in multiple regions radially and circumferentially defined in the electrostatic chuck. Further, a substrate processing apparatus includes an electrostatic chuck including a plurality of electrodes configured to generate an electrostatic force for attracting and holding a substrate and a surface on which the substrate is to be mounted; and a controller configured to control a timing of applying a DC voltage to each of the electrodes. Each of the electrodes generates an electrostatic force for attracting and holding the substrate by the DC voltage applied thereto, and the electrodes are arranged respectively in multiple regions radially and circumferentially defined in the electrostatic chuck.

Abstract: Disclosed herein is a method of drilling in a multilayer printed circuit board. The method includes drilling a one hole; directing electromagnetic radiation having at least one wavelength with higher energy than a work-function the metal layer toward the hole, and thus causing the metal layer to emit free electrons; and measuring the quantity or intensity of electrically charged particles derived from the emitted free electrons, to detect the extent of exposure or disappearance of the metal layer during drilling.

Abstract: Provided is an evaluation apparatus of a semiconductor device suppressing a discharge occurring in a part of a semiconductor device at a time of evaluating its electrical characteristics. The evaluation apparatus of a semiconductor device includes a stage to support a semiconductor device; a plurality of probes located above the stage; an insulating body having a frame shape to surround the plurality of probes and located above the stage; and an evaluation part injecting a current into the semiconductor device via the plurality of probes. The insulating body includes a tip portion having flexibility and facing the stage. The tip portion includes, in one side surface of the tip portion, a contact surface to come in contact with the semiconductor device by a deformation of the tip portion toward an inner side or an outer side of the frame shape.

Abstract: An electrostatic sensing device includes a sensor oxide semiconductor TFT, and a controller configured to control the sensor oxide semiconductor TFT. The sensor oxide semiconductor TFT includes an oxide semiconductor active layer, a source electrode connected with the oxide semiconductor active layer, a drain electrode connected with the oxide semiconductor active layer, a gate electrode behind the oxide semiconductor active layer, and a gate insulating layer between the gate electrode and the oxide semiconductor active layer The controller is configured to measure a difference from a reference current of a current flowing between the source electrode and the drain electrode, while applying a driving voltage to the gate electrode, and determine polarity of electrostatic charge of the measurement target based on direction of the difference from the reference current.

Abstract: A method of testing a semiconductor device includes respectively applying first to n-th voltages that change according to time to first to n-th semiconductor devices that are substantially same until the first to n-th semiconductor devices break down; calculating first to n-th stresses that define the total amount of stress respectively applied to the first to n-th semiconductor devices until a time when the first to n-th semiconductor devices break down, respectively, after the first to n-th voltages are applied; and calculating lifespan of the first to n-th semiconductor devices by using the first to n-th stresses.

Abstract: A testing method for the sheet resistance and contact resistance of connecting point of a sheet material, comprising: mounting at least four small electrodes on the surface of the sheet material; measuring the resistance between the electrodes; and calculating the sheet resistance and electrode contact resistance of the sheet material on the basis of a theoretical model from the resistance measured between the electrodes and the distances between the electrodes. As a main feature, the testing method is a convenient nondestructive testing method for the sheet resistance and electrode contact resistance of the sheet material, and has no strict requirement on the distribution of electrodes.

Abstract: A testing method for the sheet resistance of a sheet material, comprising: mounting two circular or annular electrodes on the surface of the sheet material; measuring the resistance between the electrodes; and calculating the sheet resistance of the sheet material on the basis of a theoretical model from the resistance measured between the electrodes, the diameters of the electrodes, and the distance between the electrodes. The method places no restriction on the diameters of the electrodes; also, the annular electrodes work as effectively as circular electrodes, and annular electrodes may improve the contact between the edges of the electrodes, and the sheet material.

Abstract: A scanning probe microscopy system for mapping nanostructures on a surface of a sample, comprises a metrology frame, a sensor head including a probe tip, and an actuator for scanning the probe tip relative to the sample surface. The system comprises a clamp for clamping of the sample, which clamp is fixed to the metrology frame and arranged underneath the sensor head. The clamp is arranged for locally clamping of the sample in a clamping area underneath the probe tip, the clamping area being smaller than a size of the sample such as to clamp only a portion of the sample. Moreover, a metrology frame for use in scanning probe microscopy system as described includes a clamp for clamping of a sample, wherein the clamp is fixed to the metrology frame such as to be arranged underneath the sensor head.

Abstract: To predict a temperature rise amount due to self-heating of a resistance value of a gate electrode with high accuracy in an HCI accelerated stress test. A gate electrode for gate resistance measurement (for temperature monitoring) that has contacts on its both sides, respectively, is disposed adjacent to the gate electrode. At the time of gate ON of the gate electrode, voltages that are substantially the same voltages as that of the gate electrode and have a minute potential difference between its contacts are applied between the contacts of the gate electrode for gate resistance measurement (for temperature monitoring), and a resistance value of the gate electrode for gate resistance measurement (for temperature monitoring) is measured.

Abstract: Implementations disclosed herein relate to methods for controlling substrate outgassing of hazardous gasses after an epitaxial process. In one implementation, the method includes providing a substrate comprising an epitaxial layer into a transfer chamber, wherein the transfer chamber has an ultraviolet (UV) lamp module disposed adjacent to a top ceiling of the transfer chamber, flowing an oxygen-containing gas into the transfer chamber through a gas line of the transfer chamber, flowing a non-reactive gas into the transfer chamber through the gas line of the transfer chamber, activating the UV lamp module to oxidize residues or species on a surface of the substrate to form an outgassing barrier layer on the surface of the substrate, ceasing the flow of the oxygen-containing gas and the nitrogen-containing gas into the transfer chamber, pumping the transfer chamber, and deactivating the UV lamp module.

Abstract: A substrate carrier adapted to use in a processing system includes an electrode assembly and a support base. The electrode assembly is configured to generate an electrostatic chucking force for securing a substrate to the substrate carrier. The support base has a heating/cooling reservoir formed therein. The electrode assembly and the support base form an unitary body configured for transport within a processing system. A quick disconnect is coupled to the body and configured to trap a heat regulating medium in the reservoir heating/cooling reservoir when the body is decoupled from a source of heat regulating medium.

Abstract: A method and apparatus for de-chucking a workpiece is described that uses a swing voltage sequence. One example pertains to a method that includes applying a mechanical force from an electrostatic chuck against the back side of a workpiece that is electrostatically clamped to the chuck, applying a sequence of voltage pulses with a same polarity to the electrodes, each pulse of the sequence having a lower voltage than the preceding pulse, each pulse of the sequence having a lower voltage than the preceding pulse, and determining whether the workpiece is released from the chuck after the sequence of additional voltage pulses and if the workpiece is not released then repeating applying the sequence of voltage pulses.

Abstract: A method for processing a semiconductor wafer uses non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-side short, chamfer short, and corner short test areas.

Abstract: A method for processing a semiconductor wafer uses non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one chamfer short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective tip-to-side short, chamfer short, and via open test areas.

Abstract: A process for making and using a semiconductor wafer includes instantiating first and second designs of experiments (DOES), each comprised of at least two fill cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The first DOE contains fill cells configured to enable non-contact (NC) detection of via opens, and the second DOE contains fill cells configured to enable NC detection of metal island opens. The process may further include obtaining NC measurements from the first and/or second DOE(s) and using such measurements, at least in part, to selectively perform additional processing, metrology or inspection steps on the wafer, and/or on other wafer(s) currently being manufactured.

Abstract: A process for making and using a semiconductor wafer includes instantiating first and second designs of experiments (DOES), each comprised of at least two fill cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The first DOE contains fill cells configured to enable non-contact (NC) detection of merged-via opens, and the second DOE contains fill cells configured to enable NC detection of stitch opens. The process may further include obtaining NC measurements from the first and/or second DOE(s) and using such measurements, at least in part, to selectively perform additional processing, metrology or inspection steps on the wafer, and/or on other wafer(s) currently being manufactured.

Abstract: A circuit and method for testing transistor(s) are provided. The circuit is used for testing a set of transistors including at least two transistors, and the circuit includes: a first power supply voltage terminal connected to first electrodes of the respective transistors; a first control signal terminal connected to control electrodes of the respective transistors; and a set of test terminals including at least two test terminals; the test terminals are connected to second electrodes of the corresponding transistors, respectively.

Abstract: An integrated circuit, in the form of a wafer, die, or chip, includes multiple standard cell-compatible fill cells, configured to enable non-contact electrical measurements. Such fill cells include mesh pads that contain at least three conductive stripes disposed between adjacent gate stripes. Such fill cells further include geometry to enable non-contact evaluation of side-to-side shorts and/or leakages.

Abstract: A test structure includes a terminal pattern, a first extending part, a second extending part and a measuring part. The terminal pattern includes a first terminal part, a second terminal part, a third terminal part and a fourth terminal part sequentially disposed and spaced apart from each other in a first direction. The first extending part is connected to the first terminal part and the second terminal part. The first extending part extends in a second direction crossing the first direction. The second extending part is connected to the third terminal part and the fourth terminal part. The second extending part extends in the second direction. The measuring part partially overlaps the first extending part and the second extending part.

Abstract: A process for making and using a semiconductor wafer includes instantiating first and second designs of experiments (DOES), each comprised of at least two fill cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The first DOE contains fill cells configured to enable non-contact (NC) detection of tip-to-side shorts, and the second DOE contains fill cells configured to enable NC detection of chamfer shorts. The process may further include obtaining NC measurements from the first and/or second DOE(s) and using such measurements, at least in part, to selectively perform additional processing, metrology or inspection steps on the wafer, and/or on other wafer(s) currently being manufactured.

Abstract: An integrated circuit, in the form of a wafer, die, or chip, includes multiple standard cell-compatible fill cells, configured to enable non-contact electrical measurements. Such fill cells include mesh pads that contain at least three conductive stripes disposed between adjacent gate stripes. Such fill cells further include geometry to enable non-contact evaluation of diagonal shorts and/or leakages.

Abstract: TFT device for measuring a contact resistance and measurement method for a contact resistance are disclosed. The TFT includes an active layer, a gate electrode and a gate insulation layer. The active layer includes a channel and at least three doping regions, wherein, two of the at least three doping regions is connected through a channel, when measuring the contact resistance, using two of the at least three doping regions as testing points for measuring. The gate electrode disposed correspondingly to the channel. The gate insulation layer for insulating the active layer from the gate electrode. The uniformity of the present invention is well, the manufacturing process, the film forming quality and the interface property are similar in a maximum degree. Accordingly, a measurement accuracy is increased, saving the distribution region at the same time, increasing the utilization of the experimental region.

Abstract: A memory module includes a module board extending in one direction, a plurality of electronic elements mounted on the module board, and at least one stress detection pattern in a position between the electronic elements or adjacent to one or more of the electronic elements on the module board and including a plurality of strips configured to indicate a stress level generated in the position by an external force applied to the module board.

Abstract: An integrated circuit, in the form of a wafer, die, or chip, includes multiple standard cell-compatible fill cells, configured to enable non-contact electrical measurements. Such fill cells include mesh pads that contain at least three conductive stripes disposed between adjacent gate stripes. Such fill cells further include geometry to enable non-contact evaluation of tip-to-tip shorts and/or leakages.

Abstract: A process for making and using a semiconductor wafer includes instantiating first and second designs of experiments (DOEs), each comprised of at least two fill cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The first DOE contains fill cells configured to enable non-contact (NC) detection of tip-to-tip shorts, and the second DOE contains fill cells configured to enable NC detection of chamfer shorts. The process may further include obtaining NC measurements from the first and/or second DOE(s) and using such measurements, at least in part, to selectively perform additional processing, metrology or inspection steps on the wafer, and/or on other wafer(s) currently being manufactured.

Abstract: A method for ensuring wafer level reliability is provided. The method involves: forming a gate oxide layer having a thickness of less than 50 ? on a semiconductor substrate; forming a PMOS element having a channel length of less than 0.13 ?m on the semiconductor substrate; and assessing hot carrier injection (HCl) for the PMOS element.