For Electrical Parameters, E.g., Resistance, Deep-levels, Cv, Diffusions By Electrical Means (epo) Patents (Class 257/E21.531)
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Patent number: 8741742Abstract: The disclosure relates to a method of fabricating an integrated circuit of CMOS technology in a semiconductor wafer comprising scribe lines. According to the disclosure, a ground contact pad of the integrated circuit is made in a scribe line of the wafer and is destroyed during a step of individualizing the integrated circuit by singulation of the wafer. A ground contact of the integrated circuit is made on the back side of the integrated circuit when it is assembled in an interconnection package.Type: GrantFiled: June 8, 2012Date of Patent: June 3, 2014Assignee: STMicroelectronics (Rousset) SASInventor: François Tailliet
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Patent number: 8729549Abstract: A plurality of peripheral test structure substrate (PTSS) through vias is formed within a peripheral test structure substrate. A peripheral test structure layer and at least one functional layer are formed on one side of the plurality of the PTSS through vias. The other side of the plurality of the PTSS through vias is exposed throughout fabrication of the peripheral test structure layer and the at least one functional layer to provide access points for testing functionality of the various layers throughout the manufacturing sequence. C4 bonding may be performed after manufacture of all of the at least one functional layer is completed. A 3D assembly carrier or a C4 carrier substrate is not required since the peripheral test structure substrate has sufficient mechanical strength to support the peripheral test structure layer and the at least one functional layer.Type: GrantFiled: June 26, 2012Date of Patent: May 20, 2014Assignee: International Business Machines CorporationInventors: Kerry Bernstein, Jerome L. Cann, Christopher M. Durham, Paul D. Kartschoke, Peter J. Klim, Donald L. Wheater
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Patent number: 8716038Abstract: Several embodiments of semiconductor systems and associated methods of color corrections are disclosed herein. In one embodiment, a method for producing a light emitting diode (LED) includes forming an (LED) on a substrate, measuring a base emission characteristic of the formed LED, and selecting a phosphor based on the measured base emission characteristic of the formed LED such that a combined emission from the LED and the phosphor at least approximates white light. The method further includes introducing the selected phosphor onto the LED via, for example, inkjet printing.Type: GrantFiled: March 2, 2010Date of Patent: May 6, 2014Assignee: Micron Technology, Inc.Inventors: Kevin Tetz, Charles M. Watkins
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Patent number: 8709834Abstract: A method of manufacturing a semiconductor device includes providing a wafer, forming a memory device which includes phase change material layer on the wafer, completing a wafer level process of manufacturing the semiconductor device, and performing a thermal treatment process on the wafer to densify the phase change material. To this end, the process temperature of the thermal treatment is higher than the crystallization temperature of the phase change material and lower than the melting point of the phase change material.Type: GrantFiled: March 5, 2012Date of Patent: April 29, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Hyun Hong, Jung-Hyuk Lee, Su-Jin Ahn, Dae-Won Ha
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Publication number: 20140110710Abstract: Disclosed is a stacked chip module incorporating a stack of integrated circuit (IC) chips having integratable and automatically reconfigurable built-in self-maintenance blocks (i.e., built-in self-test (BIST) circuits or built-in self-repair (BISR) circuits). Integration of the built-in self-maintenance blocks between the IC chips in the stack allows for servicing (e.g., self-testing or self-repairing) of functional blocks at the module-level. Automatic reconfiguration of the built-in self-maintenance blocks further allows for functional blocks on any of the IC chips in the stack to be serviced at the module-level even when one or more controllers associated with a given built-in self-maintenance block on a given IC chip has been determined to be defective (e.g., during previous wafer-level servicing). Also disclosed is a method of manufacturing and servicing such a stacked chip module.Type: ApplicationFiled: October 22, 2012Publication date: April 24, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kevin W. Gorman, Krishnendu Mondal, Saravanan Sethuraman
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Publication number: 20140110711Abstract: Disclosed is a stacked chip module and associated method with integrated circuit (IC) chips having integratable built-in self-maintenance blocks. The module comprises a stack of chips and each chip comprises a self-maintenance block with first and second controllers. The first controller controls wafer-level and module-level servicing (e.g., self-testing or self-repairing) of an on-chip functional block. The second controller provides an interface between an off-chip tester and the first controller during wafer-level servicing. Each chip further comprises a plurality of interconnect structures (e.g., multiplexers and through-substrate-vias) that integrate the self-maintenance blocks of adjacent chips in the stack so that, during module-level servicing, a single second controller on a single one of the chips in the stack (e.g., the bottom chip) provides the only interface between the off-chip tester and all of the first controllers.Type: ApplicationFiled: October 22, 2012Publication date: April 24, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kevin W. Gorman, Derek H. Leu, Krishnendu Mondal, Saravanan Sethuraman
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Patent number: 8698188Abstract: The object of the invention is to improve the visual inspection yield of a semiconductor light emitting device. To achieve the object, a semiconductor light emitting device includes a semiconductor layer, a pad electrode on the layer, and a protection film covering at least the layer. The device includes at least one stopper arranged on a peripheral part of the pad electrode surface away from the film. The stopper has a semicircular arc shape opening toward the center of the pad electrode. In electrical/optical property inspection, if sliding on the pad electrode, a probe needle can be guided into the concave surface of the semicircular arc shape. The stopper can reliably hold the needle. It is avoidable that the needle contacts the film. It is preferable that each of positive/negative electrodes have the pad electrode, and a pair of stoppers be arranged in positions on the electrodes facing each other.Type: GrantFiled: March 5, 2011Date of Patent: April 15, 2014Assignee: Nichia CorporationInventors: Yasutaka Hamaguchi, Yoshiki Inoue, Takahiko Sakamoto
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Patent number: 8698140Abstract: It has been difficult to carry out a test and an analysis with respect to combinational logic circuits mounted across plural chips, and therefore, there is provided a flip-flop (31b) by use of which either of a scan chain within a semiconductor chip (LSI_B), and a scan chain across plural semiconductor chips (LSI_A and LSI_B) can be made up.Type: GrantFiled: March 15, 2010Date of Patent: April 15, 2014Assignee: Hitachi, Ltd.Inventors: Kiyoto Ito, Takanobu Tsunoda, Makoto Saen
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Patent number: 8691597Abstract: An automatic analyzer detects voltage applied across electrodes, and judges whether voltage value falls within set voltage range. When the detected voltage value is lower than minimum value of set voltage range, the analyzer calculates the deficient amount of base solution based on the detected voltage value, controls a valve to supply the deficient amount of base solution, then, performs operation control of the valve so as to keep the prescribed amount of plating solution in plating solution tank, and discharges plating solution. When the detected voltage value is higher than maximum value of set voltage range, the analyzer calculates the excess amount of base solution based on the detected voltage value, controls a valve, and supplies pure water into the tank so that the base solution concentration falls within prescribed range to dilute plating solution, then controls a valve, and discharges plating solution so as to keep prescribed amount.Type: GrantFiled: July 12, 2012Date of Patent: April 8, 2014Assignee: Renesas Electronics CorporationInventor: Taku Kanaoka
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Patent number: 8691601Abstract: Disclosed herein is a semiconductor device, including: a semiconductor substrate; an integrated circuit formed on a first main surface of the semiconductor substrate; a penetrating electrode that penetrates the semiconductor substrate in the thickness direction and has its one end electrically connected to the integrated circuit; a bump electrode formed on a second main surface of the semiconductor substrate and electrically connected to another end of the penetrating electrode; and a test pad electrode formed on the second main surface of the semiconductor substrate and electrically connected to the bump electrode.Type: GrantFiled: December 15, 2010Date of Patent: April 8, 2014Assignee: Sony CorporationInventor: Mitsuaki Izuha
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Patent number: 8692246Abstract: A leakage measurement structure for through substrate vias which includes a semiconductor substrate; a plurality of through substrate vias in the semiconductor substrate extending substantially through the semiconductor substrate; and a leakage measurement structure located in the semiconductor substrate. The leakage measurement structure includes a plurality of substrate contacts extending into the semiconductor substrate; a plurality of sensing circuits connected to the plurality of through substrate vias and to the plurality of the substrate contacts, the plurality of sensing circuits providing a plurality of outputs indicative of current leakage from the plurality of through substrate vias; a built-in self test (BIST) engine to step through testing of the plurality of through substrate vias; and a memory coupled to the BIST engine to receive the outputs from the plurality of sensing circuits. Also included is a method of testing a semiconductor substrate.Type: GrantFiled: September 15, 2011Date of Patent: April 8, 2014Assignee: International Business Machines CorporationInventors: Bhavana Bhoovaraghan, Mukta G. Farooq, Emily R. Kinser, Sudesh Saroop
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Publication number: 20140091477Abstract: A method for forming a field-effect transistor with a raised drain structure is disclosed. The method includes depositing a low-k inter-metal layer over a semiconductor substrate, depositing a porogen-containing low-k layer over the low-k inter-metal layer, and etching a space for the via through the low-k inter-metal layer and the porogen-containing low-k layer. The method further includes depositing a metal layer, a portion of the metal layer filling the space for the via, another portion of the metal layer being over the porogen-containing low-layer, removing the portion of the metal layer over the porogen-containing layer by a CMP process, and curing the porogen-containing low-k layer to form a cured low-k layer.Type: ApplicationFiled: September 28, 2012Publication date: April 3, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yung-Hsu Wu, Shih-Kang Fu, Hsin-Chieh Yao, Chia-Min Lin, Hsiang-Huan Lee, Chung-Ju Lee, Hai-Ching Chen, Shau-Lin Shue
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Publication number: 20140080233Abstract: The embodiments describe methods and apparatuses for combinatorial optimization of interlayer parameters for capacitor stacks. The capacitor stacks may include a substrate, an insulating layer disposed on the substrate, a ruthenium disposed electrode on the insulating layer, and an interlayer disposed on the ruthenium electrode, where the interlayer is configured to prevent etching of the electrode when growing a high-k dielectric using an ozone-based precursor. The parameters for forming the interlayer may include interlayer thickness, precursor chemistry, oxidant strength, precursor purge times, oxidant purge times, and other suitable parameters. Each of these parameters may be evaluated through deposition of the capacitor stacks through a combinatorial optimization process. Thus, a plurality of different parameters may be evaluated with a single substrate to ascertain associated properties of Ruthenium electrode etching in a combinatorial manner.Type: ApplicationFiled: September 19, 2012Publication date: March 20, 2014Applicant: Intermolecular, Inc.Inventor: Venkat Ananthan
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Patent number: 8674355Abstract: A device includes a test unit in a die. The test unit includes a physical test region including an active region, and a plurality of conductive lines over the active region and parallel to each other. The plurality of conductive lines has substantially a uniform spacing, wherein no contact plugs are directly over and connected to the plurality of conductive lines. The test unit further includes an electrical test region including a transistor having a gate formed of a same material, and at a same level, as the plurality of conductive lines; and contact plugs connected to a source, a drain, and the gate of the transistor. The test unit further includes an alignment mark adjacent the physical test region and the electrical test region.Type: GrantFiled: December 29, 2010Date of Patent: March 18, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Huan-Chi Tseng, Heng-Hsin Liu, Shu-Cheng Kuo, Chien-Chang Lee, Chun-Hung Lin
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Publication number: 20140070366Abstract: A semiconductor structure is provided. The semiconductor structure includes a floating substrate; and a capacitor grounded and connected to the floating substrate. A method of manufacturing a semiconductor structure is also provided.Type: ApplicationFiled: September 13, 2012Publication date: March 13, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: HSIAO-TSUNG YEN, YU-LING LIN, CHIN-WEI KUO, HO-HSIANG CHEN, CHEWN-PU JOU, MIN-CHIE JENG
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Patent number: 8664014Abstract: Electrical testing of metal oxide semiconductor (MOS) high-k capacitor structures is used to evaluate photoresist strip or cleaning chemicals using a combinatorial workflow. The electrical testing can be able to identify the damages on the high-k dielectrics, permitting a selection of photoresist strip chemicals to optimize the process conditions in the fabrication of semiconductor devices. The high productivity combinatorial technique can provide a compatibility evaluation of photoresist strip chemicals with high-k devices.Type: GrantFiled: November 17, 2011Date of Patent: March 4, 2014Assignee: Intermolecular, Inc.Inventors: Bei Li, Sean Barstow, Anh Duong, Zhendong Hong, Ashley Lacey
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Patent number: 8658436Abstract: [Problems] There are provided a chip separation method and a chip transfer method using features of dry etching. [Means for Solving the Problems] In the chip separation method, a multiple number of semiconductor devices or semiconductor integrated circuits are separated from a wafer 100 on which the multiple number of semiconductor devices or semiconductor integrated circuits are formed. The method includes forming, on a surface of the wafer 100, a mask layer through which a line-shaped pattern to be removed for separating the semiconductor devices or semiconductor integrated circuits is exposed; and etching the exposed pattern to a depth equal to or larger than about ? of a thickness of the wafer. One group of separated semiconductor devices or semiconductor integrated circuits has a distinguishable shape from another group of separated semiconductor devices or semiconductor integrated circuits.Type: GrantFiled: April 19, 2011Date of Patent: February 25, 2014Assignee: Tokyo Electron LimitedInventors: Masahiro Yamada, Kenya Iwasaki, Hiroshi Nishikawa
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Publication number: 20140051189Abstract: Disclosed is a method for wafer-level testing a plurality of diced multi-chip stacked packages. Each package includes a plurality of chips with vertically electrical connections such as TSVs. Next, according to a die-on-wafer array arrangement, the multi-chip stacked packages are fixed on a transparent reconstructed wafer by a photo-sensitive adhesive, and the packages are located within the component-bonding area of the wafer. Then, the transparent reconstructed wafer carrying the multi-chip stacked packages can be loaded into a wafer tester for probing. Accordingly, the wafer testing probers in the wafer tester can be utilized to probe the testing electrodes of the stacked packages so that it is easy to integrate this wafer-level testing method especially into TSV packaging processes.Type: ApplicationFiled: August 14, 2012Publication date: February 20, 2014Inventors: CHANG KAI-JUN, Liu Yu-Shin, Chen Shin-Kung, Chan Kun-Chih
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Publication number: 20140042442Abstract: The present disclosure relates to a secure device having a physical unclonable function and methods of manufacturing such a secure device. The device includes a substrate and at least one high-k/metal gate device formed on the substrate. The at least one high-k/metal gate device represents the physical unclonable function. In some cases, the at least one high-k/metal gate device may be subjected a variability enhancement. In some cases, the secure device may include a measurement circuit for measuring a property of the at least one high-k/metal gate device.Type: ApplicationFiled: August 10, 2012Publication date: February 13, 2014Applicant: International Business Machines CorporationInventors: JOHN BRULEY, Vijay Narayanan, Dirk Pfeiffer, Jean-Oliver Plouchart, Peilin Song
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Publication number: 20140038317Abstract: A method forms an electrical connection between a first metal layer and a second metal layer. The second metal layer is above the first metal layer. A first via is formed between the first metal layer and the second metal layer. A first measure of a number of vacancies expected to reach the first via is obtained. A second via in at least one of the first metal layer and the second metal layer is formed if the measure of vacancies exceeds a first predetermined number.Type: ApplicationFiled: July 31, 2012Publication date: February 6, 2014Inventors: Edward O. Travis, Douglas M. Reber, Mehul D. Shroff
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Publication number: 20140038319Abstract: A method includes forming a connection between a first metal layer and a second metal layer. The second metal layer is over the first metal layer. A via location for a first via between the first metal layer and the second metal layer is identified. Additional locations for first additional vias are determined. The first additional vias are determined to be necessary for stress migration issues. Additional locations necessary for second additional vias are determined. The second additional vias are determined to be necessary for electromigration issues. The first via and the one of the group consisting of (i) the first additional vias and second additional vias (ii) the first additional vias plus a number of vias sufficient for electromigration issues taking into account that the first additional vias, after taking into account the stress migration issues, still have an effective via number greater than zero.Type: ApplicationFiled: July 31, 2012Publication date: February 6, 2014Inventors: Douglas M. Reber, Mehul D. Shroff, Edward O. Travis
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Publication number: 20140027772Abstract: Wafers with chips thereon and corresponding chips are provided where test structures or parts thereof are provided in a peripheral chip area of the chip. Corresponding methods are also disclosed.Type: ApplicationFiled: July 27, 2012Publication date: January 30, 2014Applicant: Infineon Technologies AGInventors: Markus ZUNDEL, Uwe SCHMALZBAUER
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Publication number: 20140024145Abstract: Operating speeds of integrated circuit devices are tested to establish maximum and minimum frequency at maximum and minimum voltage. The devices are sorted into relatively-slow and relatively-fast devices to classify the devices into different voltage bins. A bin-specific voltage limit is established for each of the voltage bins needed for core performance at system use conditions. The bin-specific voltage limit is compared to core minimum chip-level functionality voltage at system maximum and minimum frequency specifications. The method correlates system design evaluation of design maximum and minimum frequency at design maximum and minimum voltage conditions with evaluation of tested maximum and minimum frequency at tested maximum and minimum voltage conditions. A chip-specific functionality voltage limit is established for the device.Type: ApplicationFiled: July 20, 2012Publication date: January 23, 2014Applicant: International Business Machines CorporationInventors: JEANNE P. BICKFORD, Vikram Iyengar, Rahul K. Nadkarni, Pascal A. Nsame
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Publication number: 20140024146Abstract: A semiconductor structure is provided and includes a substrate having an edge surface and a device surface with a central area, a crack stop structure disposed on the device surface and a circuit structure including components disposed on the device surface in the central area and interconnects electrically coupled to the components. The interconnects are configured to extend from the central area to the edge surface while bridging over the crack stop structure.Type: ApplicationFiled: August 3, 2012Publication date: January 23, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Diego Anzola, Evan G. Colgan, Kevin K. Dezfulian, Daniel C. Edelstein, Mark C. H. Lamorey, Sampath Purushothaman, Thomas M. Shaw, Roy R. Yu
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Publication number: 20140021469Abstract: An Integrated Circuit (IC) and a method of making the same. In one embodiment, an integrated circuit includes: a substrate; a first metal layer disposed on the substrate and including a sensor structure configured to indicate a crack in a portion of the integrated circuit; and a second metal layer disposed proximate the first metal layer, the second metal layer including a wire component disposed proximate the sensor structure.Type: ApplicationFiled: July 17, 2012Publication date: January 23, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Edward C. Cooney, III, Jeffrey P. Gambino, Zhong-Xiang He, Tom C. Lee
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Patent number: 8633037Abstract: A semiconductor device includes a substrate having a main surface and a rear surface, a transistor formed over a side of the main surface, an insulator layer formed over a side of the main surface, an inductor formed over the insulator layer and a side of the main surface, a tape overlapping the inductor and formed over a side of the main surface, and a bonding pad formed over the insulating layer and a side of the main surface. The tape is selectively formed over an area without the bonding pad.Type: GrantFiled: November 7, 2012Date of Patent: January 21, 2014Assignee: Renesas Electronics CorporationInventors: Masayuki Furumiya, Yasutaka Nakashiba
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Patent number: 8623673Abstract: A test structure and method for monitoring process uniformity. Embodiments of the invention include test structures having a first metallization layer, a second metallization layer formed above the first metallization layer, a defect-generating region in a first metallization layer, a defect-dispersing region in the second metallization layer above the defect-generating region; and a defect-detecting region in the second metallization layer adjacent to the defect-dispersing region. The defect-generating region of the exemplary embodiment may have zero pattern density, uniform non-zero pattern density, or non-uniform non-zero pattern density. The defect-detecting region may include a test pattern such as, a comb-serpentine structure. Embodiments may include more than one defect-generating region, more than one defect-dispersing region, or more than one defect-detecting region.Type: GrantFiled: August 13, 2012Date of Patent: January 7, 2014Assignee: International Business Machines CorporationInventors: Thomas W. Dyer, Tze-Man Ko, Yiheng Xu, Shaoning Yao
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Publication number: 20130330846Abstract: A mechanism to electrically evaluate signals within an encapsulated semiconductor device package without the need for redesigning the package substrate is provided. Test bond pads are provided on a top surface of a semiconductor device die being placed within the semiconductor device package. One or more wire bonds having an elevated loop height are formed on the test bond pads. After encapsulating the semiconductor device package, the package encapsulant is subject to a backgrind process to expose a portion of the test connection wire bonds. Only an amount of the package encapsulant sufficient to expose each test connection wire bond is removed, so that the remaining encapsulant will continue to have the same effect on the package as would be present in a production device. Test probes can then be applied to the exposed test connection wire bonds.Type: ApplicationFiled: June 12, 2012Publication date: December 12, 2013Inventors: Jinbang Tang, Daniel M. Boyne
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Publication number: 20130320340Abstract: A physical test integrated circuit has a plurality of repeating circuit portions corresponding to an integrated circuit design. A first of the portions is fabricated with a nominal block mask location, and additional ones of the portions are deliberately fabricated with predetermined progressive increased offset of the block mask location from the nominal block mask location. For each of the portions, the difference in threshold voltage between a first field effect transistor and a second field effect transistor is determined. The predetermined progressive increased offset of the block mask location is in a direction from the first field effect transistor to the second field effect transistor. The block mask overlay tolerance is determined at a value of the progressive increased offset corresponding to an inflection of the difference in threshold voltage from a zero difference. A method for on-chip monitoring, and corresponding circuits, are also disclosed.Type: ApplicationFiled: June 5, 2012Publication date: December 5, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Emrah Acar, Aditya Bansal, Dureseti Chidambarrao, Liang-Teck Pang, Amith Singhee
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Patent number: 8598579Abstract: In complex semiconductor devices, the contact characteristics may be efficiently determined on the basis of a test structure which includes a combination of interconnect chain structures and a comb structure including gate electrode structures. Consequently, an increased amount of measurement information may be obtained on the basis of a reduced overall floor space of the test structure. In this manner, the complex manufacturing sequence for forming a contact level of a semiconductor device may be quantitatively estimated and monitored.Type: GrantFiled: February 3, 2011Date of Patent: December 3, 2013Assignee: GLOBALFOUNDRIES Inc.Inventors: Dmytro Chumakov, Dirk Utess
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Publication number: 20130316472Abstract: Metal gate high-k capacitor structures with lithography patterning are used to extract gate work function using a combinatorial workflow. Oxide terracing, together with high productivity combinatorial process flow for metal deposition can provide optimum high-k gate dielectric and metal gate solutions for high performance logic transistors. The high productivity combinatorial technique can provide an evaluation of effective work function for given high-k dielectric metal gate stacks for PMOS and NMOS transistors, which is critical in identifying and selecting the right materials.Type: ApplicationFiled: May 24, 2012Publication date: November 28, 2013Applicant: Intermolecular, Inc.Inventors: Amol Joshi, John Foster, Zhendong Hong, Olov Karlsson, Bei Li, Usha Raghuram
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Publication number: 20130307142Abstract: A method for selective bump formation on a wafer includes performing a wafer test on the wafer. Known good dies (KGDs) on the wafer are identified based on the wafer test performed. Solder bumps are formed on the KGDs.Type: ApplicationFiled: May 21, 2012Publication date: November 21, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: Chin-Ming LIN
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Patent number: 8586981Abstract: According to one exemplary embodiment, a silicon-on-insulator (SOI) transistor test structure includes a gate situated over a semiconductor body and a doped halo under the gate. The SOI transistor test structure further includes at least two semiconductor body contacts situated on opposing sides of the doped halo, where one or more of the at least two semiconductor body contacts forms a direct electrical contact with the doped halo, thereby increasing current flow to the doped halo to facilitate measuring body-effect in the SOI transistor test structure.Type: GrantFiled: October 5, 2006Date of Patent: November 19, 2013Assignee: Advanced Micro Devices, Inc.Inventors: Qiang Chen, Jung-Suk Goo
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Publication number: 20130295699Abstract: A method for testing TSV structures includes providing a wafer having a front side and a back side, the wafer further comprising a plurality of TSV structures formed therein; thinning the wafer from the back side of the wafer; forming a first under bump metallization layer on the back side of the wafer blanketly; providing a probing card to the front side of the wafer to test the TSV structures; and patterning the first UBM layer.Type: ApplicationFiled: May 2, 2012Publication date: November 7, 2013Inventor: Hung-Ming Liu
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Publication number: 20130285694Abstract: A TSV structure, method of making the TSV structure and methods of testing the TSV structure. The structure including: a trench extending from a top surface of a semiconductor substrate to a bottom surface of the semiconductor substrate, the trench surrounding a core region of the semiconductor substrate; a dielectric liner on all sidewalls of the trench; and an electrical conductor filling all remaining space in the trench, the dielectric liner electrically isolating the electrical conductor from the semiconductor substrate and from the core region.Type: ApplicationFiled: April 27, 2012Publication date: October 31, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Troy L. Graves-Abe, Benjamin A. Himmel, Chandrasekharan Kothandaraman, Norman W. Robson
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Publication number: 20130277857Abstract: There are proposed a stack type semiconductor device and a method of fabricating and testing the same. A stack type semiconductor device according to an embodiment of the present invention includes a plurality of contact pads externally exposed, a via array electrically connected to the contact pads, a semiconductor substrate configured to have vias, forming the via array, electrically conductive with each other or insulated from each other, and a bias pad configured to supply a bias to the semiconductor substrate, wherein the semiconductor substrate may be subject to back-grinding.Type: ApplicationFiled: August 31, 2012Publication date: October 24, 2013Applicant: SK hynix lnc.Inventor: Sun Jong Yoo
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Publication number: 20130260485Abstract: Circuitry for measuring a propagation delay in a circuit path. The circuitry includes a one-shot edge triggered element that can be connected in a loop with the circuit path. An edge signal propagating through the circuit path triggers the one-shot element to output a pulse. The pulse propagates around the loop, again triggering the one-shot element to produce a pulse, creating a repeating series of pulses. The period between these pulses is influenced by propagation time of an edge through the loop such that a difference in the period with the circuit path connected and not connected in the loop indicates propagation delay in the circuit path. Such circuitry can be configured to independently measure, and therefore calibrate for, propagation delays associated with rising and falling edges. Calibration to separately equalize propagation delays for rising and falling edges can increase the timing accuracy of an automatic test system.Type: ApplicationFiled: April 18, 2012Publication date: October 3, 2013Applicant: Teradyne, Inc.Inventors: Jan Paul Anthonie van der Wagt, Ronald A. Sartschev, Gregory A. Kannall
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Publication number: 20130252355Abstract: A method includes performing a patterning step on a layer using a process gas. When the patterning step is performed, a signal strength is monitored, wherein the signal strength is from an emission spectrum of a compound generated from the patterning step. The compound includes an element in the patterned layer. At a time the signal strength is reduced to a pre-determined threshold value, the patterning step is stopped.Type: ApplicationFiled: March 23, 2012Publication date: September 26, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Keng-Ying Liao, Szu-Hung Yang, Chiung Wen Hsu
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Publication number: 20130248859Abstract: A semiconductor device has a substrate and conductive layer over the substrate. A resistive element is formed between first and second portions of the conductive layer. A plurality of semiconductor die each with first and second bumps is mounted to the substrate with the first and second bumps electrically connected to the first and second portions of the conductive layer. A test current is routed in sequence through the first portion of the conductive layer, through the first and second bumps, and through the second portion of the conductive layer until continuity failure of the second bump. The test current originates from a single power supply. The test current continues to flow through the resistive element after the continuity failure of the second bump. The continuity failure can be detected by sensing an increase in voltage across the second bump.Type: ApplicationFiled: March 21, 2012Publication date: September 26, 2013Applicant: STATS CHIPPAC, LTD.Inventors: Robert C. Frye, Kai Liu
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Publication number: 20130244348Abstract: Methods are provided for fine tuning substrate resistivity. The method includes measuring a resistivity of a substrate after an annealing process, and fine tuning a subsequent annealing process to achieve a target resistivity of the substrate. The fine tuning is based on the measured resistivity.Type: ApplicationFiled: March 15, 2012Publication date: September 19, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jeffrey P. GAMBINO, Derrick LIU, Dale W. MARTIN, Gerd PFEIFFER
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Publication number: 20130240882Abstract: A die in accordance with various embodiments may include a metallization area located proximate an edge of the die, and an electrical connection connected to the metallization area and running from the metallization area to the edge, wherein the electrical connection is free from metal. A wafer in accordance with various embodiments may include a die region having a metallization area, a kerf region having an electric or electronic device, and an electrical connection connecting the electric or electronic device with the metallization area, wherein the electrical connection is free from metal.Type: ApplicationFiled: March 15, 2012Publication date: September 19, 2013Applicant: INFINEON TECHNOLOGIES AGInventor: Dietrich Bonart
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Patent number: 8536650Abstract: A semiconductor structure is described. The structure includes a transistor formed in a semiconductor substrate, the semiconductor substrate having a semiconductor-on-insulator (SOI) layer; a channel associated with the transistor and formed on a first portion of the SOI layer; and a source/drain region associated with the transistor and formed in a second portion of the SOI layer and in a recess at each end of the channel, where the second portion of the SOI layer is substantially thicker than the first portion of the SOI layer. A method of fabricating the semiconductor structure is also described.Type: GrantFiled: February 3, 2011Date of Patent: September 17, 2013Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Junedong Lee
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Publication number: 20130210173Abstract: To provide improved planarization, techniques in accordance with this disclosure include a CMP station that includes a plurality of concentric temperature control elements arranged over a number of concentric to-be-polished wafer surfaces. During polishing, a wafer surface planarity sensor monitors relative heights of the concentric to-be-polished wafer surfaces, and adjusts the temperatures of the concentric temperature control elements to provide an extremely well planarized wafer surface. Other systems and methods are also disclosed.Type: ApplicationFiled: February 14, 2012Publication date: August 15, 2013Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jiann Lih Wu, Bo-I Lee, Soon Kang Huang, Chih-I Peng, Chi-Ming Yang, Chin-Hsiang Lin
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Publication number: 20130203190Abstract: A method of making redistributed electronic devices that includes providing a wafer having a plurality of electronic devices, each electronic device having a pattern of contact areas forming die pads. The method also includes forming redistribution layers on a temporary substrate having a pattern of contact areas forming wafer bonding pads matching the die pads and a pattern of contact areas forming redistributed pads different than the wafer bonding pads, the wafer bonding pads are coupled to the redistributed pads through a plurality of stacked conductive and insulating layers. The die pads are coupled to the wafer bonding pads, and the temporary substrate is removed. The wafer and redistribution layers are then divided into a plurality of redistributed electronic devices.Type: ApplicationFiled: February 2, 2012Publication date: August 8, 2013Applicant: Harris Corporation, Corporation of the State of DelawareInventors: THOMAS REED, DAVID HERNDON, SUZANNE DUNPHY
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Publication number: 20130187156Abstract: A three-dimensional integrated circuit (3DIC) including a top chip having at least one active device and an interposer having conductive routing layers and vias. The 3DIC further includes a plurality of conductive connectors configured to electrically connect the top chip and the interposer. The 3DIC further includes a conductive line over at least one of the top chip or the interposer. The conductive line traces a perimeter of top chip or interposer parallel to an outer edge of the top chip or interposer. The conductive line is configured to electrically connect the conductive connectors. The 3DIC further includes at least one testing element over at least one of the top chip or the interposer. The testing element is configured to electrically connect to the plurality of conductive connectors.Type: ApplicationFiled: January 23, 2012Publication date: July 25, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ching-Fang CHEN, Hsiang-Tai LU, Chih-Hsien LIN
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Patent number: 8492176Abstract: To provide a method of manufacturing a semiconductor device including a step of attaching a surface protective tape onto the surface of a wafer which has completed the wafer process, a step of subjecting the back surface of the wafer to back grinding, and a step of attaching a peeling assist tape onto the surface protective tape while vacuum-adsorbing the back surface of the wafer to apply a tension to the assist tape, thereby separating the surface protective tape from the wafer, wherein a vacuum suction system has a peripheral suction system for the peripheral part of the wafer and an internal suction system for the internal region of the wafer.Type: GrantFiled: September 11, 2012Date of Patent: July 23, 2013Assignee: Renesas Electronics CorporationInventor: Haruo Amada
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Publication number: 20130183774Abstract: A method for testing an integrated circuit includes determining performance data of the integrated circuit, wherein at least first and second derivatives of S parameters of the integrated circuit are taken into account when determining the expected performance data. The performance data can be determined by measuring S parameters of the integrated circuit. An equivalent non-linear model of the integrated circuit can be determined from the provided S parameters and first and second derivatives of the provided S parameters. The non-linear behavior of the integrated circuit can be quantified from the equivalent non-linear model.Type: ApplicationFiled: September 14, 2012Publication date: July 18, 2013Applicant: STMICROELECTRONICS SAInventors: Raphael Paulin, Patrice Garcia
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Publication number: 20130175599Abstract: Embodiments of structures and methods for determining operating characteristics of a non-volatile memory transistor comprising a charge-storage-layer and a tunneling-layer are described.Type: ApplicationFiled: March 26, 2012Publication date: July 11, 2013Applicant: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Yu Yang, Krishnaswamy Ramkumar
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Patent number: 8481346Abstract: An aspect of the present invention relates to a method of analyzing an iron concentration of a boron-doped p-type silicon wafer by a SPV method, which comprises subjecting the wafer to Fe—B pair separation processing by irradiation with light and determining the iron concentration based on a change in a minority carrier diffusion length following the separation processing. The iron concentration is calculated with a calculation equation comprising a minority carrier diffusion length LAF1 measured after the separation processing, a minority carrier diffusion length LAF2 measured after a prescribed time has elapsed following measurement of LAF1, and dependence on time of recombination of Fe—B pairs separated by the separation processing. The calculation equation is derived by assuming that the irradiation with light causes boron atoms and oxygen atoms in the wafer to form a bonded product, and by assuming that the bonded product has identical influences on LAF1 and LAF2.Type: GrantFiled: July 27, 2011Date of Patent: July 9, 2013Assignee: Sumco CorporationInventors: Ryuji Ohno, Fumio Iga
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Publication number: 20130168673Abstract: An apparatus comprising connecting IDVMON monitors with through silicon vias (TSV) to allow the monitors to be connected to probe pads located on the backside of the wafer. Because the backside of the wafer have significantly more space than the front side, the probe pads for IDVMON can be accommodated without sacrificing the silicon area.Type: ApplicationFiled: January 3, 2012Publication date: July 4, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Xiaojun Yu, Anda C. Mocuta, Toshiaki Kirihata