Measuring As Part Of Manufacturing Process (epo) Patents (Class 257/E21.529)
  • Patent number: 10276457
    Abstract: A method for measuring charge accumulation in a fabrication process of a semiconductor device includes at least the following steps. First, a substrate having a first conductivity type is provided. Subsequently, the substrate is doped with a second conductivity type dopant to form a first well region and a second well region in the substrate. The first conductivity type is different from the second conductivity type. An inverter is formed in the first well region. A control transistor and a reference transistor are formed in the second well region. The inverter is electrically connected to the control transistor. Thereafter, a wafer acceptance test (WAT) is performed to evaluate the charge accumulation.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Hao Liao, Chu-Fu Chen, Jui-Yean Chiu
  • Patent number: 9023668
    Abstract: A method for producing a substrate having an irregular concave and convex surface for scattering light includes: manufacturing a substrate having the irregular concave and convex surface; irradiating the concave and convex surface of the manufactured substrate with inspection light from a direction oblique to a normal direction and detecting returning light of the inspection light returned from the concave and convex surface by a light-receiving element provided in the normal direction of the concave and convex surface; and judging unevenness of luminance of the concave and convex surface by an image processing device based on light intensity of the returning light received. An organic EL element which includes a diffraction-grating substrate having an irregular concave and convex surface is produced with a high throughput.
    Type: Grant
    Filed: September 17, 2013
    Date of Patent: May 5, 2015
    Assignee: JX Nippon Oil & Energy Corporation
    Inventors: Yusuke Sato, Suzushi Nishimura
  • Patent number: 8993353
    Abstract: In resin coating, carrying a light-passing member test-coated with a resin on a light-passing member carrying unit; making a light source placed above the light-passing member carrying unit emit excitation light exciting the fluorescent substance; measuring light emission characteristics of the light by irradiating the excitation light emitted from the light source unit from above to the resin coated onto the light-passing member and receiving the light that the resin emits from below the light-passing member by a light emission characteristic measurement unit; obtaining a deviation between a measurement result of the light emission characteristic measurement unit and a prescribed light emission characteristic; and deriving the appropriate resin coating quantity of the resin to be coated onto the LED element as what is used for practical production based on the deviation.
    Type: Grant
    Filed: May 30, 2012
    Date of Patent: March 31, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventor: Masaru Nonomura
  • Patent number: 8994022
    Abstract: Embodiments of the disclosure relate to a method of evaluating a semiconductor wafer dicing process, comprising providing evaluation lines extending in at least one scribe line of the wafer, dicing the wafer in the scribe line, evaluating the length of the evaluation lines, providing an information about their length, and using the information to evaluate the dicing process.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: March 31, 2015
    Assignee: STMicroelectronics Rousset SAS
    Inventor: Francois Tailliet
  • Patent number: 8987148
    Abstract: With a stage kept in an as-heated state, a semiconductor wafer is placed over the stage. Then, with the elapse of a first time, a controller causes a pressure inside a vacuum chamber to rise to a second pressure higher than a first pressure (step S40). After the semiconductor wafer is placed over the stage, a pressure difference between a pressure inside the vacuum chamber and a pressure inside an adsorption port is set to a minimum value at which the semiconductor wafer is not allowed to slide over protrusions. Further, in step S40 as well, the pressure difference is kept at the minimum value at which the semiconductor wafer is not allowed to slide over the protrusions.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: March 24, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Misato Sakamoto, Yoshitake Katou, Youichi Yamamoto, Takashi Kyouno, Chikara Yamamoto, Terukazu Motosawa, Mitsuo Maeda, Hiroshi Itou
  • Patent number: 8987013
    Abstract: A method of inspecting misalignment of a polysilicon gate is disclosed, characterized in forming only NMOS devices in P-wells in a test wafer and utilizing an advanced electron beam inspection tool operating with a positive mode to carry out electrical defect inspection. The method can be applied in precisely figuring out the in-plane misalignment of the polysilicon gates of an in-process semiconductor product and identifying a misalignment tendency therebetween across a wafer by verifying all locations of interest thereon, thus providing a methodology for process window optimization and on-line monitoring and contributing to the manufacturing process and yield improvement.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: March 24, 2015
    Assignee: Shanghai Huali Microelectronics Corporation
    Inventors: Rongwei Fan, Hunglin Chen, Yin Long, Qiliang Ni
  • Patent number: 8975093
    Abstract: The instant disclosure relates to a device and method for recrystallising a silicon wafer or a wafer comprising at least one silicon layer. The silicon wafer or the at least one silicon layer of the wafer is totally molten.
    Type: Grant
    Filed: July 22, 2010
    Date of Patent: March 10, 2015
    Assignee: S'Tile
    Inventor: Alain Straboni
  • Patent number: 8962360
    Abstract: An organic layer deposition apparatus includes: a conveyer unit including a transfer unit, a first conveyer unit, and a second conveyer unit; a loading unit for fixing a substrate to the transfer unit; a deposition unit including a chamber and at least one organic layer deposition assembly; and a measuring unit located between the loading unit and the deposition unit to measure position information of the substrate before an organic layer is deposited onto the substrate; and an unloading unit for separating, from the transfer unit, the substrate onto which the deposition has been completed, wherein the transfer unit is configured to cyclically move between the first conveyer unit and the second conveyer unit, and wherein the substrate fixed to the transfer unit is configured to be spaced apart from the at least one organic layer deposition assembly while being transferred by the first conveyer unit.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: February 24, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yun-Ho Chang, Jong-Won Hong, Sang-Su Kim
  • Patent number: 8940555
    Abstract: The formation of overlap areas in sophisticated semiconductor devices is a critical aspect which may not be efficiently evaluated on the basis of conventional measurement and design strategies. For this reason, the present disclosure provides measurement techniques and systems in which overlying device patterns are transformed into the same material layer, thereby forming a combined pattern which is accessible by well-established defect inspection techniques. Upon geometrically modulating some of these combined patterns, a systematic evaluation of overlap process windows may be accomplished.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: January 27, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Lothar Bauch
  • Patent number: 8932954
    Abstract: According to one embodiment, an impurity analysis method comprises performing vapor-phase decomposition on a silicon-containing film formed on a substrate, heating the substrate at a first temperature after vapor phase decomposition, heating the substrate at a second temperature higher than the first temperature after heating at the first temperature, to remove a silicon compound deposited on the surface of the silicon-containing film, dropping a recovery solution onto the substrate surface after heating at the second temperature and moving the substrate surface, to recover metal into the recovery solution, and drying the recovery solution, to perform X-ray fluorescence spectrometry on a dried mark.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: January 13, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuji Yamada, Makiko Katano, Chikashi Takeuchi, Tomoyo Naito
  • Patent number: 8932884
    Abstract: Structures and methods are disclosed for evaluating the effect of a process environment variation. A structure and related method are disclosed including a plurality of electrical structures arranged in a non-collinear fashion for determining a magnitude and direction of a process environment variation in the vicinity of the plurality of electrical structures. The plurality of structures may include a first polarity FET coupled to a second polarity FET, each of the first polarity FET and the second polarity FET are coupled to a first pad and a second pad such that the structure allows independent measurement of the first polarity FET and the second polarity FET using only the first and second pads. Alternatively, the electrical structures may include resistors, diodes or ring oscillators. Appropriate measurements of each electrical structure allow a gradient field including a magnitude and direction of the effect of a process environment variation to be determined.
    Type: Grant
    Filed: August 27, 2010
    Date of Patent: January 13, 2015
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak, Noah D. Zamdmer
  • Patent number: 8912016
    Abstract: Provided is a test method by which a transistor whose reliability is low can be detected with low stress and high accuracy in a shorter period of time than a BT test. Provided is to detect a transistor whose reliability is high in a shorter period of time than a BT test and manufacture an electronic device with high reliability efficiently. Hysteresis characteristics revealed in the result of the Vg-Id measurement with light irradiation to the transistor correlate with the result of a BT test; whether the reliability of the transistor is Good or Not-Good can be judged. Accordingly, the test method by which a transistor whose reliability is low can be detected with low stress and high accuracy in a shorter period of time than a BT test can be provided.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: December 16, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiromichi Godo, Shuhei Yoshitomi
  • Patent number: 8900889
    Abstract: Methods and apparatus for rapid thermal processing of a planar substrate including axially aligning the substrate with a substrate support or with an empirically determined position are described. The methods and apparatus include a sensor system that determines the relative orientations of the substrate and the substrate support.
    Type: Grant
    Filed: October 19, 2012
    Date of Patent: December 2, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Khurshed Sorabji, Joseph M. Ranish, Wolfgang Aderhold, Aaron M. Hunter, Blake R. Koelmel, Alexander N. Lerner, Nir Merry
  • Patent number: 8872348
    Abstract: A stack type semiconductor device may include a first type well formed at a first height from a bottom of a semiconductor substrate; second type doping regions formed within the first type well at bottoms of regions where vias are expected to be formed; and a first type doping region formed within the first type well at a bottom of a region where bias contacts are expected to be formed. The stack type semiconductor device comprises the vias connected to the second type doping regions; the bias contacts connected to the first type doping region; contact pads electrically connected to the vias; and bias pads electrically connected to the bias contacts.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: October 28, 2014
    Assignee: SK Hynix Inc.
    Inventor: Sun Jong Yoo
  • Patent number: 8853847
    Abstract: Disclosed is a stacked chip module incorporating a stack of integrated circuit (IC) chips having integratable and automatically reconfigurable built-in self-maintenance blocks (i.e., built-in self-test (BIST) circuits or built-in self-repair (BISR) circuits). Integration of the built-in self-maintenance blocks between the IC chips in the stack allows for servicing (e.g., self-testing or self-repairing) of functional blocks at the module-level. Automatic reconfiguration of the built-in self-maintenance blocks further allows for functional blocks on any of the IC chips in the stack to be serviced at the module-level even when one or more controllers associated with a given built-in self-maintenance block on a given IC chip has been determined to be defective (e.g., during previous wafer-level servicing). Also disclosed is a method of manufacturing and servicing such a stacked chip module.
    Type: Grant
    Filed: October 22, 2012
    Date of Patent: October 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kevin W. Gorman, Krishnendu Mondal, Saravanan Sethuraman
  • Patent number: 8854614
    Abstract: A method of thermally treating a wafer includes loading a wafer into a process chamber having one or more regions of uniform temperature gradient and one or more regions of non-uniform temperature gradient. A defect is detected in the wafer. The wafer is aligned to position the defect within one of the one or more regions of uniform temperature gradient. A rapid thermal process is performed on the wafer in the process chamber while the defect is positioned within one of the one or more regions of uniform temperature gradient.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: October 7, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Hoon Kang, Taegon Kim, Hanmei Choi, Eunyoung Jo, Gonsu Kang, Sungho Kang, Sungho Heo
  • Patent number: 8847350
    Abstract: The embodiments of methods and structures disclosed herein provide mechanisms of forming and programming a metal-via fuse. The metal-via fuse and a programming transistor form a one-time programmable (OTP) memory cell. The metal-via fuse has a high resistance and can be programmed with a low programming voltage, which expands the programming window.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: September 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sung-Chieh Lin, Kuoyuan (Peter) Hsu, Wei-Li Liao, Yun-Han Chen, Chen-Ming Hung
  • Patent number: 8828841
    Abstract: A system and method for forming an isolation trench is provided. An embodiment comprises forming a trench and then lining the trench with a dielectric liner. Prior to etching the dielectric liner, an outgassing process is utilized to remove any residual precursor material that may be left over from the deposition of the dielectric liner. After the outgassing process, the dielectric liner may be etched, and the trench may be filled with a dielectric material.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: September 9, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Tang Peng, Bing-Hung Chen, Tze-Liang Lee, Hao-Ming Lien
  • Patent number: 8828745
    Abstract: A method for manufacturing TSVs, wherein the method comprises several steps as follows: A stack structure having a substrate and an ILD layer (inter layer dielectric layer) is provided, in which an opening penetrating through the ILD layer and further extending into the substrate is formed. After an insulator layer and a metal barrier layer are formed on the stack structure and the sidewalls of the opening, a top metal layer is then formed on the stack structure to fulfill the opening. A first planarization process stopping on the barrier layer is conducted to remove a portion of the top metal layer. A second planarization process stopping on the ILD layer is subsequently conducted to remove a portion of the metal barrier layer, a portion of the insulator layer and a portion of the top metal layer, wherein the second planarization process has a polishing endpoint determined by a light interferometry or a motor current.
    Type: Grant
    Filed: July 6, 2011
    Date of Patent: September 9, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Wei-Che Tsao, Chia-Lin Hsu, Jen-Chieh Lin, Teng-Chun Tsai, Hsin-Kuo Hsu, Ya-Hsueh Hsieh, Ren-Peng Huang, Chih-Hsien Chen, Wen-Chin Lin, Yung-Lun Hsieh
  • Patent number: 8822240
    Abstract: A temperature detecting apparatus is provided which is capable of suppressing disconnection of a thermocouple wire or positional deviation of a thermocouple junction portion caused by change over time. The temperature detecting apparatus includes: an insulation rod installed to extend in a vertical direction and including a through-hole in vertical direction; a thermocouple wire inserted in the through-hole of the insulation rod, the thermocouple wire including a thermocouple junction portion at an upper end thereof and an angled portion at a lower end of the insulation rod; and a buffer area installed below the insulation rod and configured to suppress a restriction of a horizontal portion of the angled portion upon heat expansion, wherein an upper portion of the thermocouple wire or a middle portion in the vertical direction are supported by the insulation rod.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: September 2, 2014
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Tetsuya Kosugi, Masaaki Ueno, Hideto Yamaguchi
  • Patent number: 8815615
    Abstract: A method of forming interconnects in integrated circuits includes providing a semiconductor substrate and forming a copper interconnect structure that is formed overlying a barrier layer within a thickness of an interlayer dielectric layer. The copper interconnect structure has a first stress characteristic. The method further loads the semiconductor substrate including the copper interconnect structure into a deposition chamber that contains an inert environment. The semiconductor substrate including the copper interconnect structure is annealed in the inert environment for a period of time to cause the copper interconnect structure to have a second stress characteristic. The semiconductor substrate is maintained in the deposition chamber while an etch stop layer is deposited thereon. The method further deposits an intermetal dielectric layer overlying the etch stop layer, wherein the annealing reduces copper hillock defects resulting from at least the first stress characteristic.
    Type: Grant
    Filed: November 2, 2010
    Date of Patent: August 26, 2014
    Assignees: Semiconductor Manufacturing International (Shanghai) Corp., Semiconductor Manufacturing International (Beijing) Corp.
    Inventors: Duo Hui Bei, Ming Yuan Liu, Chun Sheng Zheng
  • Patent number: 8785952
    Abstract: A light emitting device is disclosed. The light emitting device includes a first electrode and a second electrode, which have different areas, thereby achieving enhanced bonding reliability.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: July 22, 2014
    Assignee: LG Innotek Co., Ltd.
    Inventor: Dongwook Park
  • Patent number: 8716038
    Abstract: Several embodiments of semiconductor systems and associated methods of color corrections are disclosed herein. In one embodiment, a method for producing a light emitting diode (LED) includes forming an (LED) on a substrate, measuring a base emission characteristic of the formed LED, and selecting a phosphor based on the measured base emission characteristic of the formed LED such that a combined emission from the LED and the phosphor at least approximates white light. The method further includes introducing the selected phosphor onto the LED via, for example, inkjet printing.
    Type: Grant
    Filed: March 2, 2010
    Date of Patent: May 6, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Kevin Tetz, Charles M. Watkins
  • Patent number: 8716037
    Abstract: A direct measurement of lattice spacing by X-ray diffraction is performed on a periodic array of unit structures provided on a substrate including semiconductor devices. Each unit structure includes a single crystalline strained material region and at least one stress-generating material region. For example, the single crystalline strained material region may be a structure simulating a channel of a field effect transistor, and the at least one stress-generating material region may be a single crystalline semiconductor region in epitaxial alignment with the single crystalline strained material region. The direct measurement can be performed in-situ at various processing states to provide in-line monitoring of the strain in field effect transistors in actual semiconductor devices.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: May 6, 2014
    Assignee: International Business Machines Corporation
    Inventors: Thomas N. Adam, Stephen W. Bedell, Eric C. Harley, Judson R. Holt, Anita Madan, Conal E. Murray, Teresa L. Pinto
  • Patent number: 8709834
    Abstract: A method of manufacturing a semiconductor device includes providing a wafer, forming a memory device which includes phase change material layer on the wafer, completing a wafer level process of manufacturing the semiconductor device, and performing a thermal treatment process on the wafer to densify the phase change material. To this end, the process temperature of the thermal treatment is higher than the crystallization temperature of the phase change material and lower than the melting point of the phase change material.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: April 29, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Hyun Hong, Jung-Hyuk Lee, Su-Jin Ahn, Dae-Won Ha
  • Patent number: 8704384
    Abstract: A stacked die assembly for an IC includes a first interposer; a second interposer; a first integrated circuit die, a second integrated circuit die, and a plurality of components. The first integrated circuit die is interconnected to the first interposer and the second interposer, and the second integrated circuit die is interconnected to the second interposer. The plurality of components interconnect the first integrated circuit die to the first interposer and the second interposer. The plurality of components that interconnect the first integrated circuit die to the first interposer and the second interposer are located outside an interconnect restricted area of the first interposer and the second interposer, and signals are routed between the first integrated circuit die and the second integrated circuit die via the first integrated circuit die avoiding the interconnect restricted area of the first interposer and the second interposer.
    Type: Grant
    Filed: February 17, 2012
    Date of Patent: April 22, 2014
    Assignee: Xilinx, Inc.
    Inventors: Ephrem C. Wu, Raghunandan Chaware
  • Publication number: 20140087488
    Abstract: A showerhead electrode assembly for use in a capacitively coupled plasma processing apparatus comprising a heat transfer plate. The heat transfer plate having independently controllable gas volumes which may be pressurized to locally control thermal conductance between a heater member and a cooling member such that uniform temperatures may be established on a plasma exposed surface of the showerhead electrode assembly.
    Type: Application
    Filed: September 24, 2012
    Publication date: March 27, 2014
    Applicant: Lam Research Corporation
    Inventors: Sang Ki Nam, Rajinder Dhindsa, Ryan Bise
  • Patent number: 8674357
    Abstract: According to an embodiment, a method for measuring an impurity concentration profile uses a wafer including a semiconductor layer. The method includes measuring an impurity concentration profile in a depth direction from each surface of a plurality of first portions, each of the first portions being included in any one of a plurality of first regions provided in the semiconductor layer. Each of the first regions has a different size and is surrounded by a second region including a second portion having a different structure from the first portion. The method includes determining a change between the impurity concentration profiles measured in the first regions.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: March 18, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazuya Nishihori
  • Patent number: 8674355
    Abstract: A device includes a test unit in a die. The test unit includes a physical test region including an active region, and a plurality of conductive lines over the active region and parallel to each other. The plurality of conductive lines has substantially a uniform spacing, wherein no contact plugs are directly over and connected to the plurality of conductive lines. The test unit further includes an electrical test region including a transistor having a gate formed of a same material, and at a same level, as the plurality of conductive lines; and contact plugs connected to a source, a drain, and the gate of the transistor. The test unit further includes an alignment mark adjacent the physical test region and the electrical test region.
    Type: Grant
    Filed: December 29, 2010
    Date of Patent: March 18, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Huan-Chi Tseng, Heng-Hsin Liu, Shu-Cheng Kuo, Chien-Chang Lee, Chun-Hung Lin
  • Patent number: 8664105
    Abstract: A method for processing a wafer with a wafer bevel that surrounds a central region is provided. The wafer is placed in a bevel plasma processing chamber. A protective layer is deposited on the wafer bevel without depositing the protective layer over the central region. The wafer is removed from the bevel plasma processing chamber. The wafer is further processed.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: March 4, 2014
    Assignee: Lam Research Corporation
    Inventors: Andreas Fischer, William Scott Bass
  • Patent number: 8652858
    Abstract: A chip testing method includes cutting a wafer into chip packages, re-arranging the chip packages on a chip tray, and testing the re-arranged chip packages. The wafer includes a plurality of substrates vertically stacked thereon, and each of the plurality of substrates has a plurality of chips mounted thereon.
    Type: Grant
    Filed: April 12, 2012
    Date of Patent: February 18, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eon-Jo Byun, Yang-Gi Kim
  • Patent number: 8648451
    Abstract: Provided are a socket, a semiconductor package, a test device and a method of manufacturing a semiconductor package. A socket to test a semiconductor package comprising a housing, a trench receiving a semiconductor package in the housing, at least one probe connected to the semiconductor package at a bottom of the trench, and at least one connector electrically connecting a plurality of contact points exposed at a side of the semiconductor package when the semiconductor package is inserted into the trench. A semiconductor package with contacts exposed from a side of a package substrate, and a method of manufacturing such a semiconductor package are also disclosed.
    Type: Grant
    Filed: April 18, 2011
    Date of Patent: February 11, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Seok-Chan Lee
  • Publication number: 20140011301
    Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) fabrication method to form an IC structure having one or more through silicon via (TSV) features. The IC fabrication method includes performing a plurality of processing steps; collecting physical metrology data from the plurality of processing steps; collecting virtual metrology data from the plurality of processing steps based on the physical metrology data; generating a yield prediction to the IC structure based on the physical metrology data and the virtual metrology data; and identifying an action at an earlier processing step based on the yield prediction.
    Type: Application
    Filed: July 6, 2012
    Publication date: January 9, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien Rhone Wang, Kewei Zuo, Chen-Hua Yu, Jing-Cheng Lin, Yen-Hsin Liu
  • Publication number: 20140001601
    Abstract: A method of reducing current leakage in unused circuits performed during semiconductor fabrication and a semiconductor device or integrated circuit thereby formed. The method involves modifying a characteristic of at least one idle circuit that is unused in a product variant, to inhibit the circuit and reduce current leakage therefrom upon powering as well as during operation. The method can substantially increase the Vt (threshold voltage) of all transistors of a given type, such as all N-type transistors or all P-type transistors. The method is also suitable for controlling other transistor parameters, such as transistor channel length, as well as other active elements, such as N-type resistors or P-type resistors, in unused circuits which affect leakage current as well as for other unused circuits, such as a high Vt circuit, a standard Vt circuit, a low Vt circuit, and an SRAM cell Vt circuit.
    Type: Application
    Filed: June 28, 2012
    Publication date: January 2, 2014
    Applicant: PMC-SIERRA US, INC.
    Inventors: Bruce SCATCHARD, Chunfang XIE, Scott BARRICK, Kenneth D. WAGNER
  • Patent number: 8617908
    Abstract: A method for producing a substrate, the method including: forming a porous zone in an inner layer of the substrate; progressively thinning a thickness of the substrate towards the inner layer including the porous zone; completing the progressively thinning by polishing; and controlled stopping of the polishing by detecting the porous zone during the polishing, the detecting including measuring at least one measurable physical parameter admitting a significant variation during a transition between two layers.
    Type: Grant
    Filed: March 10, 2011
    Date of Patent: December 31, 2013
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Frederic-Xavier Gaillard, Fabrice Nemouchi
  • Patent number: 8609442
    Abstract: A coating film (90) is formed by causing vapor deposition particles (91) discharged from a vapor deposition source opening (61) of a vapor deposition source (60) to pass through a space between a plurality of control plates (81) of a control plate unit (80) and a mask opening (71) of a vapor deposition mask in this order and adhere to a substrate, while the substrate (10) is moved relative to the vapor deposition mask (70) in a state in which the substrate (10) and the vapor deposition mask (70) are spaced apart at a fixed interval. A difference in the amount of thermal expansion between the vapor deposition source and the control plate unit is detected and corrected. It is thereby possible to form, at a desired position on a large-sized substrate, the coating film in which edge blur and variations in the edge blur are suppressed.
    Type: Grant
    Filed: October 11, 2011
    Date of Patent: December 17, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Satoshi Inoue, Shinichi Kawato, Tohru Sonoda
  • Patent number: 8609473
    Abstract: A method for fabricating a stackable integrated circuit layer and a device made from the method are disclosed. A stud bump is defined on the contact pad of an integrated circuit die and the stud-bumped die encapsulated in a potting material to define a potted assembly. A predetermined portion of the potting material is removed whereby a portion of the stud bump is exposed. One or more electrically conductive traces are defined on the layer surface and in electrical connection with the stud bump to reroute the integrated circuit contacts to predetermined locations on the layer to provide a stackable neolayer.
    Type: Grant
    Filed: October 12, 2011
    Date of Patent: December 17, 2013
    Assignee: ISC8 Inc.
    Inventors: Peter Lieu, James Yamaguchi, Randy Bindrup, W. Eric Boyd
  • Patent number: 8609548
    Abstract: A method for etching features into an etch layer in a plasma processing chamber, comprising a plurality of cycles is provided. Each cycle comprises a deposition phase and an etching phase. The deposition phase comprises providing a flow of deposition gas, forming a plasma from the deposition gas in the plasma processing chamber, providing a first bias during the deposition phase to provide an anisotropic deposition, and stopping the flow of the deposition gas into the plasma processing chamber. The etching phase, comprises providing a flow of an etch gas, forming a plasma from the etch gas in the plasma processing chamber, providing a second bias during the etch phase, wherein the first bias is greater than the second bias, and stopping the flow of the etch gas into the plasma processing chamber.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: December 17, 2013
    Assignee: Lam Research Corporation
    Inventors: Qing Xu, Camelia Rusu, Jaroslaw W. Winniczek, Frank Y. Lin, Alan J. Miller
  • Patent number: 8603839
    Abstract: A metrology system for gauging and spatially mapping a semiconductor material on a substrate can be used in controlling deposition and thermal activation processes.
    Type: Grant
    Filed: July 25, 2011
    Date of Patent: December 10, 2013
    Assignee: First Solar, Inc.
    Inventors: Arnold Allenic, Stephan Paul George, II, Sreenivas Jayaraman, Oleh Karpenko, Chong Lim
  • Patent number: 8603908
    Abstract: A method for preventing formation of metal silicide material on a wafer bevel is provided, where the wafer bevel surrounds a central region of the wafer. The wafer is placed in bevel plasma processing chamber. A protective layer is deposited on the wafer bevel. The wafer is removed from the bevel plasma processing chamber. A metal layer is deposited over at least part of the central region of the wafer, wherein part of the metal layer is deposited over the protective layer. Semiconductor devices are formed while preventing metal silicide formation on the wafer bevel.
    Type: Grant
    Filed: May 6, 2011
    Date of Patent: December 10, 2013
    Assignee: Lam Research Corporation
    Inventors: Andreas Fischer, William Scott Bass
  • Publication number: 20130323860
    Abstract: A semiconductor substrate support for use in a plasma processing apparatus comprises a chuck body having a plenum and three radially extending bores extending between the plenum and an outer periphery of the chuck body, wherein the chuck body is sized to support a semiconductor substrate having a diameter of at least 450 mm. The semiconductor substrate support further comprises three tubular support arms which include a first section extending radially outward from the outer periphery of the chuck body, and a second section extending vertically from the first section. The tubular support arms provide a passage therethrough which communicates with a respective bore in the chuck body. The second section of each tubular support aim is configured to engage with a respective actuation mechanism outside the chamber operable to effect vertical translation and planarization of the chuck body in the interior of a plasma processing chamber.
    Type: Application
    Filed: May 31, 2012
    Publication date: December 5, 2013
    Applicant: Lam Research Corporation
    Inventors: Jerrel Kent Antolik, Yen-kun Victor Wang, John Holland
  • Patent number: 8592261
    Abstract: A semiconductor device may be designed in the following manner. A stacked layer of a silicon oxide film and an organic film is provided over a substrate, deuterated water is contained in the organic film, and then a conductive film is formed in contact with the organic film. Next, an inert conductive material that does not easily generate a deuterium ion or a deuterium molecule is selected by measuring the amount of deuterium that exists in the silicon oxide film.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: November 26, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kaoru Hatano, Satoshi Seo
  • Publication number: 20130277857
    Abstract: There are proposed a stack type semiconductor device and a method of fabricating and testing the same. A stack type semiconductor device according to an embodiment of the present invention includes a plurality of contact pads externally exposed, a via array electrically connected to the contact pads, a semiconductor substrate configured to have vias, forming the via array, electrically conductive with each other or insulated from each other, and a bias pad configured to supply a bias to the semiconductor substrate, wherein the semiconductor substrate may be subject to back-grinding.
    Type: Application
    Filed: August 31, 2012
    Publication date: October 24, 2013
    Applicant: SK hynix lnc.
    Inventor: Sun Jong Yoo
  • Publication number: 20130270558
    Abstract: A method of testing an integrated circuit (IC) chip and a related test structure are disclosed. A test structure includes a monitor chain proximate to at least one solder bump pad, the monitor chain including at least one metal via stack, each metal via stack extending from a lower metal layer in the IC chip to an upper metal layer in the IC chip, such that the monitor chain forms a continuous circuit proximate to the at least one solder bump pad, and where each metal via stack is positioned substantially under the solder bump. A method for testing to detect boundaries of safe effective modulus includes performing a stress test on an IC chip containing the test structure joined to a semiconductor package.
    Type: Application
    Filed: April 17, 2012
    Publication date: October 17, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James V. Crain, JR., Mark C. H. Lamorey, Christopher D. Muzzy, Thomas M. Shaw, David B. Stone
  • Patent number: 8557613
    Abstract: A method for designing, fabricating, and predicting a desired structure in and/or on a host material through defining etch masks and etching the host material is provided. The desired structure can be micro- or nanoscale structures, such as suspended nanowires and corresponding supporting pillars, and can be defined one layer at a time. Arbitrary desired structures can also be defined and obtained through etching. Further, given the desired structure, a starting structure can be predicted where etching of the starting structure yields the desired structure.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: October 15, 2013
    Assignee: California Institute of Technology
    Inventors: Michael Shearn, Michael David Henry, Axel Scherer
  • Patent number: 8557612
    Abstract: A method to determine minimum etch mask dosage or thickness as a function of etch depth or maximum etch depth as a function of etch mask implantation dosage or thickness, for fabricating structures in or on a substrate through etch masking via addition or removal of a masking material and subsequent etching.
    Type: Grant
    Filed: June 25, 2010
    Date of Patent: October 15, 2013
    Assignee: California Institute of Technology
    Inventors: Michael David Henry, Michael Shearn, Axel Scherer
  • Publication number: 20130248960
    Abstract: A semiconductor memory storage device includes first and second doped regions of a first type disposed in a semiconductor substrate. The first and second doped regions of the first type being laterally spaced from one another. A gate dielectric extends over the semiconductor substrate between the first and second doped regions, and a floating gate is disposed on the gate dielectric. An ultraviolet (UV) light blocking material is vertically disposed above the floating gate and has a size that covers the floating gate such that the floating gate remains electrically charged after the semiconductor memory storage device is exposed to UV light.
    Type: Application
    Filed: March 21, 2012
    Publication date: September 26, 2013
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsiang-Tai LU, Chih-Hsien LIN
  • Publication number: 20130244349
    Abstract: According to one embodiment, an impurity analysis method comprises performing vapor-phase decomposition on a silicon-containing film formed on a substrate, heating the substrate at a first temperature after vapor phase decomposition, heating the substrate at a second temperature higher than the first temperature after heating at the first temperature, to remove a silicon compound deposited on the surface of the silicon-containing film, dropping a recovery solution onto the substrate surface after heating at the second temperature and moving the substrate surface, to recover metal into the recovery solution, and drying the recovery solution, to perform X-ray fluorescence spectrometry on a dried mark.
    Type: Application
    Filed: August 24, 2012
    Publication date: September 19, 2013
    Inventors: Yuji Yamada, Makiko Katano, Chikashi Takeuchi, Tomoyo Naito
  • Publication number: 20130234213
    Abstract: The amount of Pt residues remaining after forming Pt-containing NiSi is reduced by performing a rework including applying SPM at a temperature of 130° C. in a SWC tool, if Pt residue is detected. Embodiments include depositing a layer of Ni/Pt on a semiconductor substrate, annealing the deposited Ni/Pt layer, removing unreacted Ni from the annealed Ni/Pt layer, annealing the Ni removed Ni/Pt layer, removing unreacted Pt from the annealed Ni removed Ni/Pt layer, analyzing the Pt removed Ni/Pt layer for unreacted Pt residue, and if unreacted Pt residue is detected, applying SPM to the Pt removed Ni/Pt layer in a SWC tool. The SPM may be applied to the Pt removed Ni'/Pt layer at a temperature of 130° C.
    Type: Application
    Filed: March 8, 2012
    Publication date: September 12, 2013
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Sivakumar KUMARASAMY, Clemens Fitz, Markus Lenski, Jochen Poth, Kristin Schupke
  • Publication number: 20130236989
    Abstract: A method for method for removing a hard mask is described. The method includes forming at least a portion of a trench-via structure in a low-k insulation layer on a substrate using one or more etching processes and a hard mask layer overlying the low-k insulation layer. Thereafter, the method includes depositing a SiOCl-containing layer on exposed surfaces of the trench-via structure to form an insulation protection layer, performing one or more etching processes to anisotropically remove at least a portion of the SiOCl-containing layer from at least one surface on the trench-via structure, and removing the hard mask layer using a mask removal etching process.
    Type: Application
    Filed: March 7, 2012
    Publication date: September 12, 2013
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Alok RANJAN, Kaushik Arun KUMAR