Of Thick- Or Thin-film Circuits Or Parts Thereof (epo) Patents (Class 257/E21.533)
  • Patent number: 10344385
    Abstract: Provided are a method for forming conductive pattern by direct radiation of an electromagnetic wave capable of forming fine conductive patterns on various kinds of polymer resin products or resin layers by a simplified process, and appropriately implementing the polymer resin products having white color or various colors, and the like, even without containing specific inorganic additives in the polymer resin itself, and a resin structure having the conductive pattern formed therefrom.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: July 9, 2019
    Assignee: LG CHEM, LTD.
    Inventors: Jae Hyun Kim, Shin Hee Jun, Jae Jin Kim, Chee-Sung Park, Eun Kyu Seong, Su Jeong Lee, Cheol-Hee Park, Han Nah Jeong, Sang Yun Jung
  • Patent number: 9578751
    Abstract: The purpose of the present invention is to provide a method for using a metal ion solution of low concentration to efficiently form a metal film pattern of excellent accuracy and reliable adhesion on a resin substrate. A resin substrate having a metal film pattern formed thereon is produced by a method that includes the following steps (a) to (e): (a) a step for pattern-printing of a latent image agent (2) onto the surface of a resin substrate (1) ; (b) a step for bringing the area imprinted with the latent image agent (2) into contact with a solution containing metal ions, and forming a metal salt (3); (c) a step for bringing the metal salt (3) into contact with an acidic treatment liquid containing a reducing agent, and reducing the metal salt; (d) a step for forming an electroless nickel plating film (5) on the area imprinted with the latent image agent; and (e) a step for precipitating an electroless copper plating (6) onto the surface of the nickel plating film (5).
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: February 21, 2017
    Assignee: SEIREN CO., LTD.
    Inventors: Akimitsu Bamba, Kazuhisa Tsujimoto, Hideyuki Yamada, Kouichi Kugimiya
  • Patent number: 8557618
    Abstract: A photo mask is disclosed. The photo mask includes a mask substrate, and a mask pattern formed to include a plurality of unit mask patterns which are arranged in a single line for a fine pattern formation. The unit mask pattern is configured to include a body portion positioned at a center and wing portions formed in a triangular shape at both sides of the body portion.
    Type: Grant
    Filed: December 18, 2009
    Date of Patent: October 15, 2013
    Assignee: LG Display Co., Ltd.
    Inventor: Tae Gyun Kim
  • Patent number: 8530273
    Abstract: Certain example embodiments relate to methods of making oxide thin film transistor arrays (e.g., IGZO, amorphous or polycrystalline ZnO, ZnSnO, InZnO, and/or the like), and devices incorporating the same. Blanket layers of an optional barrier layer, semiconductor, gate insulator, and/or gate metal are disposed on a substrate. These and/or other layers may be deposited on a soda lime or borosilicate substrate via low or room temperature sputtering. These layers may be later patterned and/or further processed in making a TFT array according to certain example embodiments. In certain example embodiments, all or substantially all TFT processing may take place at a low temperature, e.g., at or below 150 degrees C., until a post-annealing activation step, and the post-anneal step may take place at a relatively low temperature (e.g., 200-250 degrees C.).
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: September 10, 2013
    Assignee: Guardian Industries Corp.
    Inventor: Willem Den Boer
  • Patent number: 8460967
    Abstract: A semiconductor module comprises components in one wafer level package. The module comprises an integrated circuit (IC) chip embedded within a package molding compound. The package comprises a molding compound package layer coupled to an interface layer for integrating an antenna structure and a bonding interconnect structure to the IC chip. The bonding interconnect structure comprises three dimensional interconnects. The antenna structure and bonding interconnect structure are coupled to the IC chip and integrated within the interface layer in the same wafer fabrication process.
    Type: Grant
    Filed: September 18, 2012
    Date of Patent: June 11, 2013
    Assignee: Infineon Technologies AG
    Inventors: Rudolf Lachner, Linus Maurer, Maciej Wojnowski
  • Patent number: 8460961
    Abstract: A method for forming a transducer including the step of providing a semiconductor-on-insulator wafer including first and second semiconductor layers separated by an electrically insulating layer, wherein the first layer is formed or provided by hydrogen ion delamination of a starting wafer. The method further includes doping the first layer to form a piezoresistive film and etching the piezoresistive film to form at least one piezoresistor. The method also includes depositing or growing a metallization layer on the semiconductor-on-insulator wafer, the metallization layer including an electrical connection portion that is located on or is electrically coupled to the piezoresistor. The method includes removing at least part of the second semiconductor layer to form a diaphragm, with the at least part of the piezoresistor being located on the diaphragm, and joining the wafer to a package by melting a high temperature braze material or a glass frit material.
    Type: Grant
    Filed: April 8, 2011
    Date of Patent: June 11, 2013
    Assignee: Rosemount Aerospace Inc.
    Inventors: Shuwen Guo, Odd Harald Steen Eriksen, Kimiko J. Childress
  • Patent number: 8304779
    Abstract: The thin film transistor includes a gate insulating film formed over a gate electrode; a microcrystalline semiconductor film including an impurity element which serves as a donor, formed over the gate insulating film; a pair of buffer layers formed over the microcrystalline semiconductor film; a pair of semiconductor films to which an impurity element imparting one conductivity type is added, formed over the pair of buffer layers; and wirings formed over the pair of semiconductor films to which an impurity element imparting one conductivity type is added. The concentration of the impurity element which serves as a donor in the microcrystalline semiconductor film is decreased from the gate insulating film side toward the buffer layers, and the buffer layers do not include the impurity element which serves as a donor at a higher concentration than the detection limit of SIMS.
    Type: Grant
    Filed: October 27, 2008
    Date of Patent: November 6, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yasuhiro Jinbo
  • Patent number: 8294155
    Abstract: A thin film transistor with excellent electric characteristics, a display device having the thin film transistor, and a method for manufacturing the thin film transistor and the display device are proposed. The thin film transistor includes a gate insulating film formed over a gate electrode, a microcrystalline semiconductor film formed over the gate insulating film, a buffer layer formed over the microcrystalline semiconductor film, a pair of semiconductor films to which an impurity element imparting one conductivity type is added and which are formed over the buffer layer, and wirings formed over the pair of semiconductor films to which the impurity element imparting one conductivity type is added. A part of the gate insulating film or the entire gate insulating film, and/or a part of the microcrystalline semiconductor or the entire microcrystalline semiconductor includes an impurity element which serves as a donor.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: October 23, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yoshiyuki Kurokawa, Yasuhiro Jinbo, Satoshi Kobayashi, Daisuke Kawae
  • Patent number: 8198657
    Abstract: A thin film transistor array panel includes an insulating substrate. A gate line is formed on the insulating substrate and has a gate electrode. A gate insulating layer is formed on the gate line. A semiconductor layer is formed on the gate insulating layer and overlaps the gate electrode. Diffusion barriers are formed on the semiconductor layer and contain nitrogen. A data line crosses the gate line and has a source electrode partially contacting the diffusion barriers and a drain electrode partially contacting the diffusion barriers and facing the source electrode. The drain electrode is on the gate electrode. A pixel electrode is electrically connected to the drain electrode.
    Type: Grant
    Filed: January 5, 2010
    Date of Patent: June 12, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Hoon Lee, Do-Hyun Kim, Chang-Oh Jeong, O-Sung Seo, Xin-Xing Li
  • Patent number: 8183661
    Abstract: According to one exemplary embodiment, a power managing semiconductor die with reduced power consumption includes a power island including an event detection block and an event qualification block. The event detection block is configured to activate the event qualification block in response to an input signal initiated by an external event. The input signal is coupled to the event detection block, for example, via a bond pad situated in an I/O region of the power managing semiconductor die. The event qualification block is configured to determine if the external event is a valid external event. The event qualification block resides in a thin oxide region and the event detection block resides in a thick oxide region of the semiconductor die. The power managing semiconductor die further includes a power management unit configured to activate the event qualification block in response to power enable signal outputted by the event detection block.
    Type: Grant
    Filed: April 21, 2011
    Date of Patent: May 22, 2012
    Assignee: Broadcom Corporation
    Inventor: Wenkwei Lou
  • Patent number: 8102005
    Abstract: The present invention provides a method for forming a wiring having a minute shape on a large substrate with a small number of steps, and further a wiring substrate formed by the method. Moreover, the present invention provides a semiconductor device in which cost reduction and throughput improvement are possible due to the small number of steps and reduction of materials and which has a semiconductor element with a minute structure, and further a manufacturing method thereof. According to the present invention, a composition including metal particles and organic resin is irradiated with laser light and a part of the metal particles is baked to form a conductive layer typified by a wiring, an electrode or the like over a substrate. Further, a semiconductor device having the baked conductive layer as a wiring or an electrode is formed.
    Type: Grant
    Filed: February 13, 2009
    Date of Patent: January 24, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiroko Yamamoto, Osamu Nakamura
  • Patent number: 8093090
    Abstract: In the fabrication of an integrated circuit, a trench with a sidewall is formed along the periphery of the integrated circuit and the substrate is back-lapped to a thickness smaller than the trench depth to separate the integrated circuit from other integrated circuits on the same substrate. Increased protection against contaminant diffusion into the integrated circuit through the sidewall at the periphery is obtained with one or more protective layers. The substrate area useful for integrated circuit fabrication is also increased.
    Type: Grant
    Filed: October 12, 2009
    Date of Patent: January 10, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Federico Pio
  • Patent number: 8030104
    Abstract: A method for manufacturing a liquid crystal display device is disclosed.
    Type: Grant
    Filed: August 21, 2008
    Date of Patent: October 4, 2011
    Assignee: LG Display Co., Ltd.
    Inventors: Sung Il Park, Dae Lim Park
  • Patent number: 7994574
    Abstract: A double-structure silicon on insulator (SOI) substrate with a silicon layer, an insulation film (silicon oxide film), a silicon layer, and an insulation film in this order from the side of the surface. The upper-layer insulation film is formed so as to have a uniform distribution of depth while the lower-layer insulation film is formed so as to have a non-uniform distribution of depth so that a thick portion may be formed in the silicon layer along a predetermined path. The refractive index of Si is 3.5 and the refractive index of SiO2 is 1.5. The thick portion of the silicon layer provides a core and the insulation films corresponding to this thick portion provide clads, thereby forming an optical waveguide along the predetermined path. The silicon layer at the side of the surface has a uniform thickness, thereby enabling characteristics of MOS devices fabricated on various portions of the silicon layer to be met with each other easily and facilitating a design of the electrical device as a whole.
    Type: Grant
    Filed: November 17, 2006
    Date of Patent: August 9, 2011
    Assignee: Sony Corporation
    Inventor: Koichiro Kishima
  • Patent number: 7989332
    Abstract: A thin film transistor with excellent electric characteristics, a display device having the thin film transistor, and a method for manufacturing the thin film transistor and the display device are proposed. The thin film transistor includes a gate insulating film formed over a gate electrode, a microcrystalline semiconductor film formed over the gate insulating film, a buffer layer formed over the microcrystalline semiconductor film, a pair of semiconductor films to which an impurity element imparting one conductivity type is added and which are formed over the buffer layer, and wirings formed over the pair of semiconductor films to which the impurity element imparting one conductivity type is added. A part of the gate insulating film or the entire gate insulating film, and/or a part of the microcrystalline semiconductor or the entire microcrystalline semiconductor includes an impurity element which serves as a donor.
    Type: Grant
    Filed: July 20, 2010
    Date of Patent: August 2, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yoshiyuki Kurokawa, Yasuhiro Jinbo, Satoshi Kobayashi, Daisuke Kawae
  • Patent number: 7968386
    Abstract: Application form of and demand for an IC chip formed with a silicon wafer are expected to increase, and further reduction in cost is required. An object of the invention is to provide a structure of an IC chip and a process capable of producing at a lower cost. In view of the above described object, one feature of the invention is to provide the steps of forming a separation layer over an insulating substrate and forming a thin film integrated circuit having a semiconductor film as an active region over the separation layer, wherein the thin film integrated circuit is not separated. There is less limitation on the shape of a mother substrate in the case of using the insulating substrate, when compared with the case of taking a chip out of a circular silicon wafer. Accordingly, reduction in cost of an IC chip can be achieved.
    Type: Grant
    Filed: November 6, 2009
    Date of Patent: June 28, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Koji Dairiki
  • Patent number: 7960261
    Abstract: The present invention relates to a method for manufacturing a polycrystalline semiconductor film that can be used for a semiconductor device. In the method, an amorphous semiconductor film is irradiated with a femtosecond laser to be crystallized. By laser irradiation using a femtosecond laser, when an amorphous semiconductor film over which a cap film is formed is crystallized with a laser, it becomes possible to perform crystallization of the semiconductor film and removal of the cap film at the same time. Therefore, a step of removing the cap film in a later step can be omitted.
    Type: Grant
    Filed: March 7, 2008
    Date of Patent: June 14, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Takatsugu Omata
  • Patent number: 7944016
    Abstract: According to one exemplary embodiment, a power managing semiconductor die with reduced power consumption includes a power island including an event detection block and an event qualification block. The event detection block is configured to activate the event qualification block in response to an input signal initiated by an external event. The input signal is coupled to the event detection block, for example, via a bond pad situated in an I/O region of the power managing semiconductor die. The event qualification block is configured to determine if the external event is a valid external event. The event qualification block resides in a thin oxide region and the event detection block resides in a thick oxide region of the semiconductor die. The power managing semiconductor die further includes a power management unit configured to activate the event qualification block in response to power enable signal outputted by the event detection block.
    Type: Grant
    Filed: August 29, 2007
    Date of Patent: May 17, 2011
    Assignee: Broadcom Corporation
    Inventor: Wenkwei Lou
  • Patent number: 7910469
    Abstract: An electrical circuit containing a substrate having thereon a receptive layer, wherein the receptive layer has a conductive polymer impregnated in the receptive layer, and a method for forming the electrical circuit.
    Type: Grant
    Filed: September 24, 2003
    Date of Patent: March 22, 2011
    Assignee: Konica Minolta Holdings, Inc.
    Inventor: Katsura Hirai
  • Patent number: 7863615
    Abstract: A display unit includes, on an insulating substrate, a plurality of wirings formed to extend in different directions, a thin-film transistor, and a display element. At least one of the plurality of wirings is a divided wiring having a crossing portion formed at an intersection with the other of the plurality of wirings, and a main portion which is formed in a layer same as the other of the plurality of wirings with an insulating film in between and which is electrically connected to the crossing portion via an conductive connection provided in the insulating film. At least one of the main portion and the crossing portion includes a first layer and a second layer stacked in order from the insulating substrate side, the second layer being in direct contact with the first layer and made of a material of a higher melting point than the first layer.
    Type: Grant
    Filed: October 17, 2008
    Date of Patent: January 4, 2011
    Assignee: Sony Corporation
    Inventors: Naoki Hayashi, Atsuya Makita, Yasunobu Hiromasu
  • Publication number: 20100301444
    Abstract: Photoelectric conversion elements are arranged in a pixel area. A circuit area is arranged around the pixel area. An interconnect including copper is arranged in the pixel area and circuit area. A cap layer is arranged on the interconnect. Wherein the cap layer except a part on the interconnect is removed from the pixel area and circuit area.
    Type: Application
    Filed: March 17, 2010
    Publication date: December 2, 2010
    Inventor: Hidetoshi KOIKE
  • Patent number: 7808000
    Abstract: A thin film transistor with excellent electric characteristics, a display device having the thin film transistor, and a method for manufacturing the thin film transistor and the display device are proposed. The thin film transistor includes a gate insulating film formed over a gate electrode, a microcrystalline semiconductor film formed over the gate insulating film, a buffer layer formed over the microcrystalline semiconductor film, a pair of semiconductor films to which an impurity element imparting one conductivity type is added and which are formed over the buffer layer, and wirings formed over the pair of semiconductor films to which the impurity element imparting one conductivity type is added. A part of the gate insulating film or the entire gate insulating film, and/or a part of the microcrystalline semiconductor or the entire microcrystalline semiconductor includes an impurity element which serves as a donor.
    Type: Grant
    Filed: October 1, 2008
    Date of Patent: October 5, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yoshiyuki Kurokawa, Yasuhiro Jinbo, Satoshi Kobayashi, Daisuke Kawae
  • Publication number: 20100210053
    Abstract: A photo mask is disclosed. The photo mask includes a mask substrate, and a mask pattern formed to include a plurality of unit mask patterns which are arranged in a single line for a fine pattern formation. The unit mask pattern is configured to include a body portion positioned at a center and wing portions formed in a triangular shape at both sides of the body portion.
    Type: Application
    Filed: December 18, 2009
    Publication date: August 19, 2010
    Inventor: Tae Gyun Kim
  • Patent number: 7754542
    Abstract: An electronic device and/or component is manufactured using additive processing steps, including additive printing steps. A first layer is printed using additive printing techniques wherein a single first material is used to print the first layer in a single processing step. A second layer is printed in more than a single printing step where a first portion of the second layer is printed using a second material and a second portion of the second layer is printed using a third material, and the second and third materials are different from each other.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: July 13, 2010
    Assignee: Palo Alto Research Center Incorporated
    Inventor: Robert A. Street
  • Patent number: 7700417
    Abstract: A cascode amplifier (CA) (60) is described having a bottom transistor (T1new) with a relatively thin gate dielectric (67) and higher ratio (RB) of channel length (Lch1new) to width (W1new) and a series coupled top transistor (T2new) with a relatively thick gate dielectric (68) and a lower ratio (RT) of channel length (Lch2new) to width (W2new). An improved cascode current mirror (CCM) (74) is formed using a coupled pair of CAs (60, 60?), one (60) forming the reference current (RC) side (601) and the other (60?) forming the mirror current side (602) of the CCM (74). The gates (65, 65?) of the bottom transistors (T1new, T3new) are tied together and to the common node (21) between the series coupled bottom (T1new) and top (T2new) transistors of the RC side (601), and the gates (66?, 66?) of the top transistors (T2new, T4new) are coupled together and to the top drain node (64) of the RC side (601).
    Type: Grant
    Filed: March 15, 2007
    Date of Patent: April 20, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Hongning Yang, Geoffrey W. Perkins, Jiang-Kai Zuo
  • Patent number: 7632721
    Abstract: Application form of and demand for an IC chip formed with a silicon wafer are expected to increase, and further reduction in cost is required. An object of the invention is to provide a structure of an IC chip and a process capable of producing at a lower cost. In view of the above described object, one feature of the invention is to provide the steps of forming a separation layer over an insulating substrate and forming a thin film integrated circuit having a semiconductor film as an active region over the separation layer, wherein the thin film integrated circuit is not separated. There is less limitation on the shape of a mother substrate in the case of using the insulating substrate, when compared with the case of taking a chip out of a circular silicon wafer. Accordingly, reduction in cost of an IC chip can be achieved.
    Type: Grant
    Filed: January 27, 2005
    Date of Patent: December 15, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Koji Dairiki
  • Patent number: 7622359
    Abstract: A method for manufacturing a semiconductor device, includes: (a) forming a SiGe layer on a Si substrate; (b) forming a Si layer on the SiGe layer; (c) forming a dummy pattern made of SiGe in a dummy region of the Si substrate; and (d) wet-etching and removing the SiGe layer formed under the Si layer. In the step (d), an etchant is kept to contact the dummy pattern from before a complete remove of the SiGe layer to an end of the etching.
    Type: Grant
    Filed: February 4, 2008
    Date of Patent: November 24, 2009
    Assignee: Seiko Epson Corporation
    Inventors: Juri Kato, Kei Kanemoto
  • Publication number: 20090227051
    Abstract: A light-blocking layer is formed using a first resist mask, and a base film is formed over the light-blocking layer. A first conductive film, a first insulating film, a semiconductor film, an impurity semiconductor film, and a second conductive film are sequentially formed over the base film, and first etching is performed on the second conductive film, the impurity semiconductor film, the semiconductor film, and the first insulating film using a second resist mask over the second conductive film. Then, second etching in which side-etching is performed is performed on part of the first conductive film to form a gate electrode layer, and source and drain electrode layers, source and drain region layers, and a semiconductor layer are formed using a third resist mask. The first resist mask and the second resist mask are formed using the same photomask. Thus, a thin film transistor is manufactured.
    Type: Application
    Filed: March 3, 2009
    Publication date: September 10, 2009
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Hidekazu Miyairi, Takafumi Mizoguchi
  • Patent number: 7566904
    Abstract: A thin film transistor has a semiconductor thin film including zinc oxide, a protection film formed on entirely the upper surface of the semiconductor thin film, a gate insulating film formed on the protection film, a gate electrode formed on the gate insulating film above the semiconductor thin film, and a source electrode and drain electrode formed under the semiconductor thin film so as to be electrically connected to the semiconductor thin film.
    Type: Grant
    Filed: June 7, 2006
    Date of Patent: July 28, 2009
    Assignee: Casio Computer Co., Ltd.
    Inventor: Hiromitsu Ishii
  • Patent number: 7553689
    Abstract: A semiconductor device including a semiconductor substrate having a photosensor formed therein; a first layer overlying the substrate, the first layer includes a portion having a generally concave shaped surface being the negative shaped of a micro-lens to be formed there over; a second layer overlying the first layer, the second layer including a generally convex shaped portion vertically aligned with and mating with the generally concave shaped surface, the generally convex shaped portion being constructed and arranged to define a micro-lens positioned to cause parallel light passing through the micro-lens to converge on and strike the photosensor.
    Type: Grant
    Filed: July 13, 2005
    Date of Patent: June 30, 2009
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jeng-Shyan Lin, Chien-Hsien Tseng, Shou-Gwo Wuu, Ho-Ching Chien, Dun-Nian Yaung, Hung-Jen Hsu
  • Publication number: 20090152655
    Abstract: A method of fabricating a micro-electrical-mechanical system (MEMS) apparatus on a substrate (10) comprises the steps of processing the substrate (10) so as to fabricate an electronic circuit (11); depositing a first electrode (15) that is operably coupled with the electronic circuit (11); depositing a membrane (16) so that it is mechanically coupled to the first electrode (15); applying a sacrificial layer (50); depositing a structural layer (18) and a second electrode (17) that is operably coupled with the electronic circuit (11) so that the sacrificial layer (50) is disposed between the membrane (16) and the structural layer (18) so as to form a preliminary structure; singulating the substrate (10); and removing the sacrificial layer (50) so as to form a MEMS structure, in which the step of singulating the substrate (10) is carried out before the step of removing the sacrificial layer (50).
    Type: Application
    Filed: February 23, 2007
    Publication date: June 18, 2009
    Inventors: Richard Ian Laming, Anthony Traynor
  • Publication number: 20090140255
    Abstract: An island of a crystalline semiconductor according to the present invention has an upper surface and a sloped side surface, which are joined together with a curved surface. Crystal grains in a body portion of the island, including the upper surface, and crystal grains in an edge portion of the island, including the sloped side surface, both have average grain sizes that are greater than 0.2 ?m.
    Type: Application
    Filed: June 21, 2005
    Publication date: June 4, 2009
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Tomohiro Kimura, Takuto Yasumatsu
  • Publication number: 20090101905
    Abstract: A display unit includes, on an insulating substrate, a plurality of wirings formed to extend in different directions, a thin-film transistor, and a display element. At least one of the plurality of wirings is a divided wiring having a crossing portion formed at an intersection with the other of the plurality of wirings, and a main portion which is formed in a layer same as the other of the plurality of wirings with an insulating film in between and which is electrically connected to the crossing portion via an conductive connection provided in the insulating film. At least one of the main portion and the crossing portion includes a first layer and a second layer stacked in order from the insulating substrate side, the second layer being in direct contact with the first layer and made of a material of a higher melting point than the first layer.
    Type: Application
    Filed: October 17, 2008
    Publication date: April 23, 2009
    Applicant: SONY CORPORATION
    Inventors: Naoki Hayashi, Atsuya Makita, Yasunobu Hiromasu
  • Patent number: 7494923
    Abstract: The present invention provides a method for forming a wiring having a minute shape on a large substrate with a small number of steps, and further a wiring substrate formed by the method. Moreover, the present invention provides a semiconductor device in which cost reduction and throughput improvement are possible due to the small number of steps and reduction of materials and which has a semiconductor element with a minute structure, and further a manufacturing method thereof. According to the present invention, a composition including metal particles and organic resin is irradiated with laser light and a part of the metal particles is baked to form a conductive layer typified by a wiring, an electrode or the like over a substrate. Further, a semiconductor device having the baked conductive layer as a wiring or an electrode is formed.
    Type: Grant
    Filed: June 13, 2005
    Date of Patent: February 24, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiroko Yamamoto, Osamu Nakamura
  • Publication number: 20080164551
    Abstract: Embodiments relate to an image sensor, and for directly manufacturing microlenses on color filter layers without forming a separate planarization layer, by forming the color filter layers having a relatively even step. According to embodiments, a method may include forming an interlayer dielectric layer on a semiconductor substrate formed with a plurality of photo diodes, forming color filter layers on the interlayer dielectric layer, forming a sacrifice layer on the whole surface including the color filter layers, making the steps of the color filter layers even by etching the upper surfaces of the color filter layers and the sacrifice layer, and forming microlenses on the color filter layers.
    Type: Application
    Filed: December 26, 2007
    Publication date: July 10, 2008
    Inventor: Young-Je Yun
  • Publication number: 20080146011
    Abstract: Disclosed is a method of modifying the surface of an ITO (Indium Tin Oxide; In2O3—SnO2) film using new organic material to increase the properties of the ITO film. A method of forming a self-assembled monolayer on an ITO film to increase the work function of an ITO film for use in the transparent electrode of a display device and an ITO film having a self-assembled monolayer, manufactured using the above method, are provided. The ITO film having the self-assembled monolayer has an increased work function, and thus holes can be efficiently injected from the ITO to an organic layer. Thereby, ohmic contact between the organic layer and the electrode is realized, consequently improving the electrical properties of organic electronic devices.
    Type: Application
    Filed: April 6, 2007
    Publication date: June 19, 2008
    Applicant: Konkuk University Industrial Cooperation Corp.
    Inventors: Young Soo Yoon, Seung Hyun Jee, Soo Ho Kim, Jae Hwan Ko
  • Patent number: 7375039
    Abstract: A method and an apparatus for performing the method. The method includes: (a) providing an apparatus, wherein the apparatus comprises (i) a chamber, (ii) a plasma device being in and coupled to the chamber, (iii) a shower head being in and coupled to the chamber, and (iv) a chuck being in and coupled to the chamber; (b) placing the substrate on the chuck; (c) using the plasma device to receive a plasma device gas and generate a plasma; (d) directing the plasma at a pre-specified area on the substrate; and (e) using the shower head to receive and distribute a shower head gas in the chamber, wherein the plasma device gas and the shower head gas are selected such that the plasma and the shower head gas when mixed with each other result in a chemical reaction that forms a film at the pre-specified area on the substrate.
    Type: Grant
    Filed: May 24, 2005
    Date of Patent: May 20, 2008
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey P. Gambino, Thomas L. McDevitt, Anthony K. Stamper
  • Patent number: 7303929
    Abstract: A method of testing microelectronic dies is described. A respective set of dies is inserted into die carrier bodies releasably held within a set of sockets secured to a burn-in board. A set of die carrier covers is closed, each die carrier cover being secured to a respective die carrier body and closing over a respective die. The burn-in board is then inserted into a burn-in oven. Burn-in testing of the dies is then carried out while in the burn-in oven. The burn-in board is then removed from the oven. The die carrier covers are then opened. The dies are removed from the die carrier bodies without removing the die carrier bodies from the sockets. The process is then repeated with subsequent sets of dies.
    Type: Grant
    Filed: September 13, 2004
    Date of Patent: December 4, 2007
    Assignee: Aehr Test Systems
    Inventors: Martin A. Hemmerling, Seang P. Malathong
  • Publication number: 20070262476
    Abstract: A process for manufacturing an integrated circuit using shallow trench isolation (STI) includes a 2-step nitride removal process which, when combined with a nitride pull-back step provides, in a floating gate memory integrated circuit, a high coupling ratio and a reduction in thinning of the tunnel oxide layer in a floating gate memory integrated circuit.
    Type: Application
    Filed: May 9, 2006
    Publication date: November 15, 2007
    Inventors: Yi Ding, Jason Taylor, Chiliang Chen
  • Patent number: 7294902
    Abstract: The invention relates to a trench isolation with a self-aligning surface sealing and a fabrication method for said surface sealing. In this case, the surface sealing may have an overlap region of the substrate surface or a receded region into which extends an electrically conductive layer formed on the substrate surface.
    Type: Grant
    Filed: July 24, 2002
    Date of Patent: November 13, 2007
    Assignee: Infineon Technologies AG
    Inventors: Dietmar Temmler, Andreas Wich-Glasen