Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a multi-channel active pattern including germanium and an inner region and an outer region, the outer region formed along a profile of the inner region, and a germanium fraction of the outer region being smaller than a germanium fraction of the inner region. A gate electrode intersects the multi-channel active pattern.

Abstract: A method includes providing a Si substrate having an overlying layer of Si1-xGex; growing, over the layer of Si1-xGex, a layer of Si in an NFET region and a second layer of Si1-xGex in a PFET region; partitioning the layer of Si1-xGex into a structure including a first Si1-xGex sub-layer disposed in the NFET region and a second Si1-xGex sub-layer disposed in the PFET region; annealing the structure to convert the first Si1-xGex sub-layer and the overlying Si layer into a tensily strained Si1-xGex intermixed layer and to convert the second Si1-xGex sub-layer and the overlying second layer of Si1-xGex into a compressively strained Si1-xGex intermixed layer, where a value of x in the tensily strained Si1-xGex intermixed layer is less than a value of x in the compressively strained Si1-xGex intermixed layer and forming a first transistor in the NFET region and a second transistor in the PFET region.

Abstract: A method includes providing a substrate with at least one semiconducting layer. The method also includes forming a plurality of isolation barriers within the at least one semiconducting layer, thereby forming a plurality of device islands. The method further includes inserting a plurality of electronic devices into a portion of the at least one semiconducting layer such that each electronic device is substantially isolated from each other electronic device by the device islands.

Abstract: A method of fabricating a light emitting diode array, comprising: providing a temporary substrate; forming a first light emitting stack and a second light emitting stack on the temporary substrate; forming a first insulating layer covering partial of the first light emitting stack; forming a wire on the first insulating layer and electrically connecting to the first light emitting stack and the second light emitting stack; forming a second insulating layer fully covering the first light emitting stack, the wire and partial of the second light emitting stack; forming a metal connecting layer on the second insulating layer and electrically connecting to the second light emitting stack; forming a conductive substrate on the metal connecting layer; removing the temporary substrate; and forming a first electrode connecting to the first light emitting stack.

Abstract: In a method for producing at least at least one area (8) with reduced electrical conductivity within an electrically conductive III-V semiconductor layer (3), a ZnO layer (1) is applied to the area (8) of the semiconductor layer (3) and subsequently annealed at a temperature preferably between 300° C. and 500° C. The ZnO layer (1) is preferably deposited on the III-V semiconductor layer (3) at a temperature of less than 150° C., preferably at a temperature greater than or equal to 25° C. and less than or equal to 120° C. The area (8) with reduced electrical conductivity is preferably located in a radiation emitting optoelectronic device between the active zone (4) and a connecting contact (7) in order to reduce current injection into the areas of the active zone (4) located opposite to the connecting contact (7).

Abstract: A method and apparatus for the deposition of thin films is described. In embodiments, systems and methods for epitaxial thin film formation are provided, including systems and methods for forming binary compound epitaxial thin films. Methods and systems of embodiments of the invention may be used to form direct bandgap semiconducting binary compound epitaxial thin films, such as, for example, GaN, InN and AlN, and the mixed alloys of these compounds, e.g., (In, Ga)N, (Al, Ga)N, (In, Ga, Al)N. Methods and apparatuses include a multistage deposition process and system which enables rapid repetition of sub-monolayer deposition of thin films.

Abstract: A method of fabricating a light emitting diode array, comprising: providing a temporary substrate; forming a first light emitting stack and a second light emitting stack on the temporary substrate; forming a first insulating layer covering partial of the first light emitting stack; forming a wire on the first insulating layer and electrically connecting to the first light emitting stack and the second light emitting stack; forming a second insulating layer fully covering the first light emitting stack, the wire and partial of the second light emitting stack; forming a metal connecting layer on the second insulating layer and electrically connecting to the second light emitting stack; forming a conductive substrate on the metal connecting layer; removing the temporary substrate; and forming a first electrode connecting to the first light emitting stack.

Abstract: The process forms a FET with a channel region that has in plane compressive stress in one direction and in plane tensile stress in a perpendicular direction. The process deposits a germanium silicon sacrificial stressor layer on a silicon substrate so that the germanium silicon is in a state of compressive stress. Etching trenches forms silicon pillars covered by the stressor layer and transfers tensile strain to the upper portion of the pillar. The process fills the trenches with stiff insulating material to maintain the strain in the pillar and etching removes the stressor layer. More etching creates recesses on either side of a channel region in the upper portion of the pillar. Doped germanium silicon layers fill the recesses, apply lateral compressive stress to the pillar's channel region and act as source and drain electrodes. A gate is formed above the strained channel region.

Abstract: III-nitride materials are used to form isolation structures in high voltage ICs to isolate low voltage and high voltage functions on a monolithic power IC. Critical performance parameters are improved using III-nitride materials, due to the improved breakdown performance and thermal performance available in III-nitride semiconductor materials. An isolation structure may include a dielectric layer that is epitaxially grown using a III-nitride material to provide a simplified manufacturing process. The process permits the use of planar manufacturing technology to avoid additional manufacturing costs. High voltage power ICs have improved performance in a smaller package in comparison to corresponding silicon structures.

Abstract: A laser diode epitaxial wafer has an n-type GaAs substrate, an n-type cladding layer formed on the n-type GaAs substrate, an active layer formed on the n-type cladding layer, and a p-type cladding layer formed on the active layer. The n-type cladding layer, the active layer, and the p-type cladding layer are formed of an AlGaInP-based material. The p-type cladding layer has carbon as a p-type impurity. The p-type cladding layer has a carrier concentration in the range of not less than 8.0×1017 cm?3 and not more than 1.5×1018 cm?3.

Abstract: A separation element formed of one of a conduction region and a metal layer is placed between two elements in proximity to each other. The separation element is connected to a high resistance element and to a direct current terminal pad. A connection route extending from the direct current terminal pad to the separation element is a route in which a potential does not vibrate with high frequency. This results in a placement of a high frequency GND potential between the two elements, at least one of which is subjected to transmitting the high frequency signals, whereby leak of the high frequency signals can be prevented between the two elements.

Abstract: A compound semiconductor substrate manufacturing method suitable for manufacturing a compound semiconductor element having high electrical characteristics. The compound semiconductor substrate manufacturing method is a method for manufacturing a compound semiconductor substrate having pn junction, including an epitaxial growing process, a selective growing process and other discretionary processes after the epitaxial growing process. The highest temperatures in the selective growing process and other discretionary processes after the epitaxial growing process are lower than that in the epitaxial growing process prior to the selective growing process.

Abstract: The invention relates to a method of producing a semiconductor device, comprising the following steps consisting in: forming first, second and third semiconductor layers (1, 2, 3), whereby the first and second layers (1, 3) contain a smaller concentration of oxidisable species than the second layer (2); forming a mask (4) on the third layer (3); and oxidising the second layer (2) with the diffusion of oxidising species through the third layer (3).

Abstract: A method for fabricating an isolation layer in a semiconductor device includes providing a substrate, forming a trench over the substrate, forming a liner nitride layer and a liner oxide layer along a surface of the trench, forming an insulation layer having an etch selectivity ratio different from that of the liner oxide layer over the liner oxide layer, forming a spin on dielectric (SOD) oxide layer to fill a portion of the trench over the insulation layer, and forming a high density plasma (HDP) oxide layer for filling the remaining a portion of the trench.

Abstract: In a method of manufacturing a semiconductor device, a semiconductor layer is patterned to form a source region, a channel region, and a drain region in the semiconductor layer. The channel region extends between the source region and the drain region. Corners of the channel region are rounded by annealing the channel region to form a nano-rod structure. Part of the nano-rod structure is then used as a gate channel. Preferably, a gate dielectric and a gate electrode both wrap around the nano-rod structure, with the gate dielectric being between the nano-rod structure and the gate electrode, to form a transistor device.