Abstract: A design support apparatus includes a storage that stores first layout data and pattern data, the first layout data indicating a circuit pattern of a design target circuit, the circuit pattern including circuit patterns, dummy patterns of the component circuits, and a wiring pattern, the component circuits being included in the design target circuit, the pattern data indicating a second dummy pattern, the second dummy pattern having a shape different from a shape of a first dummy pattern, the first dummy pattern being included in the first layout data, and a processor coupled to the storage, configured to specifies a component circuit, the specified component circuit being included in an area in the arrangement area, extracts pattern data indicating a dummy pattern, generates second layout data, the second layout data indicating a circuit pattern, and outputs the second layout data.

Abstract: A manufacturing method for a shallow trench isolation. First, a substrate is provided, a hard mask layer and a patterned photoresist layer are sequentially formed on the substrate, at least one trench is then formed in the substrate through an etching process, the hard mask layer is removed. Afterwards, a filler is formed at least in the trench and a planarization process is then performed on the filler. Since the planarization process is performed only on the filler, so the dishing phenomenon can effectively be avoided.

Abstract: A semiconductor device and a method of making a semiconductor device are disclosed. The method of manufacturing a semiconductor device comprises forming a material layer on a substrate, patterning a first semi-global region with a first main pattern and patterning a second semi-global region with a second main pattern, wherein the first main pattern is different than the second main pattern. The method further comprises introducing a first dummy pattern in the first semi-global region so that a first sidewall area surface density of the first main pattern and the first dummy pattern in the first semi-global region and a second sidewall area surface density of the second main pattern in the second semi-global region are substantially a same density.

Abstract: A method of making a semiconductor device includes forming a dielectric layer over a semiconductor substrate. The method further includes forming a copper-containing layer in the dielectric layer, wherein the copper-containing layer has a first portion and a second portion. The method further includes forming a first barrier layer between the first portion of the copper-containing layer and the dielectric layer. The method further includes forming a second barrier layer at a boundary between the second portion of the copper-containing layer and the dielectric layer wherein the second barrier layer is adjacent to an exposed portion of the dielectric layer. The first barrier layer is a dielectric layer, and the second barrier layer is a metal oxide layer, and a boundary between a sidewall of the copper-containing layer and the first barrier layer is free of the second barrier layer.

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a plurality of circuit devices over a substrate. The method includes forming an organic layer over the substrate. The organic layer is formed over the plurality of circuit devices. The method includes polishing the organic layer to planarize a surface of the organic layer. The organic layer is free of being thermally treated prior to the polishing. The organic material is un-cross-linked during the polishing. The method includes depositing a LT-film over the planarized surface of the organic layer. The depositing is performed at a temperature less than about 150 degrees Celsius. The depositing is also performed without using a spin coating process. The method includes forming a patterned photoresist layer over the LT-film.

Abstract: Techniques disclosed herein prevent wire flaking (collapse). One aspect is an improved way of forming wires over trenches, which may be located in a hookup region of a 3D memory array, and may be used to form electrical connections between conductive lines in the memory array and drivers. The trenches are formed between CMP dummy structures. The trenches are partially filled with a flowable oxide film, which leaves a gap in the trench that is at least as wide as the total pitch of the wires to be formed. A capping layer is formed over the flowable film. After forming a conductive layer over the dielectric layer, the conductive layer is etched to form conductive wires. Some of the capping layer, as well as the CMP dummy structures may be removed. Thus, the conductive wires may be at least temporarily supported by lines of material formed from the capping layer.

Abstract: In accordance with an embodiment, a semiconductor device includes a substrate, a line-and-space structure, a first film and a second film. The line-and-space structure includes line patterns arranged on the substrate parallel to one another at a predetermined distance. The first film is formed on side surfaces and bottom surfaces of the line patterns by an insulating film material. The second film is formed on the line-and-space structure across a space between the line patterns by a material showing low wettability to the first film. Space between the line patterns includes an air gap in which at least a bottom surface of the first film is totally exposed.

Abstract: A display substrate includes first, second, and third insulating layers in a display area thereof. The first and third insulating layers are in not only the display area but also a pad area adjacent to the display area and including a pad therein. Thus, defects of the display panel may be reduced.

Abstract: A copper interconnect includes a copper layer formed in a dielectric layer, having a first portion and a second portion. A first barrier layer is formed between the first portion of the copper layer and the dielectric layer. A second barrier layer is formed at the boundary between the second portion of the copper layer and the dielectric layer. The first barrier layer is a dielectric layer, and the second barrier layer is a metal oxide layer.

Abstract: The present disclosure relates to a method of forming a back-end-of-the-line metallization layer. The method is performed by forming a plurality of freestanding metal layer structures (i.e., metal layer structures not surrounded by a dielectric material) on a semiconductor substrate within an area defined by a patterned photoresist layer. A diffusion barrier layer is deposited onto the metal layer structure in a manner such that the diffusion barrier layer conforms to the top and sides of the metal layer structure. A dielectric material is formed on the surface of the substrate to fill areas between metal layer structures. The substrate is planarized to remove excess metal and dielectric material and to expose the top of the metal layer structure.

Abstract: A method of forming a biosensor chip enables a bond pad and detector electrode to be formed of different materials (one is formed of a connection layer such as copper and the other is formed of a diffusion barrier layer such as tantalum or tantalum nitride). A single planarizing operation is used for both the bond pad and the detector electrode. By using the same processing, resist patterning on an already-planarized surface is avoided, and the cleanliness of both the bond pad and detector electrode is ensured. Self-aligned nanoelectrodes and bond pads are obtained.

Abstract: A semiconductor device and a method of making a semiconductor device are disclosed. The method of manufacturing a semiconductor device comprises forming a material layer on a substrate, patterning a first semi-global region with a first main pattern and patterning a second semi-global region with a second main pattern, wherein the first main pattern is different than the second main pattern. The method further comprises introducing a first dummy pattern in the first semi-global region so that a first sidewall area surface density of the first main pattern and the first dummy pattern in the first semi-global region and a second sidewall area surface density of the second main pattern in the second semi-global region are substantially a same density.

Abstract: A method of manufacturing a semiconductor device includes forming a first insulating film above a semiconductor substrate, forming a wiring to be buried in the first insulating film, forming a protruding portion in an upper surface of the wiring, forming a second insulating film above the first insulating film and the wiring including the protruding portion, planarizing a surface of the second insulating film, forming a third insulating film on the second insulating film whose surface is planarized, forming a lower electrode on the third insulating film, forming a capacitor insulating film on the lower electrode, and forming an upper electrode on the capacitor insulating film.

Abstract: A method for fabricating a semiconductor device includes (a) depositing an insulating film on a semiconductor substrate; (b) forming a recess in the insulating film; (c) depositing a conductive film on the insulating film while filling the recess with the conductive film; and (d) polishing the conductive film. Step (d) includes a first polishing substep of using a first polisher pad conditioned with a first dresser and a second polishing substep of using a second polisher pad conditioned with a second dresser different from the first dresser.

Abstract: Methods of forming a semiconductor include forming an insulation layer over a semiconductor substrate in which a first region and a second region are defined. A storage node contact (SNC) that passes through the insulation layer is formed and is electrically connected to the first region. A conductive layer that passes through the insulation layer is deposited and is electrically connected to the second region on the insulation layer and the SNC. A bit line is formed by removing an upper portion of the conductive layer, an upper portion of the insulation layer and an upper portion of the SNC until the SNC and the conductive layer are electrically separated from each other, wherein the bit line is a remaining part of the conductive layer.

Abstract: A method of fabricating a lower bottom electrode for a memory element and a semiconductor structure having the same includes forming a dielectric layer over a semiconductor substrate having a plurality of conductive contacts formed therein to be connected to access circuitry, forming a dielectric cap layer over exposed portions of the dielectric layer and the conductive contacts, depositing a planarizing material over the dielectric cap layer, etching a via to an upper surface of each conductive contact, removing the planarizing material, depositing electrode material over the dielectric cap layer and within the vias, the electrode material contacting an upper surface of each conductive contact, and planarizing the electrode material to form a lower bottom electrode over each conductive contact.

Abstract: The present invention generally relates to the formation of a micro-electromechanical system (MEMS) cantilever switch in a complementary metal oxide semiconductor (CMOS) back end of the line (BEOL) process. The cantilever switch is formed in electrical communication with a lower electrode in the structure. The lower electrode may be either blanket deposited and patterned or simply deposited in vias or trenches of the underlying structure. The excess material used for the lower electrode is then planarized by chemical mechanical polishing or planarization (CMP). The cantilever switch is then formed over the planarized lower electrode.

Abstract: An integrated circuit structure and a method of forming the same are provided. The method includes providing a surface; performing an ionized oxygen treatment to the surface; forming an initial layer comprising silicon oxide using first process gases comprising a first oxygen-containing gas and tetraethoxysilane (TEOS); and forming a silicate glass over the initial layer. The method may further include forming a buffer layer using second process gases comprising a second oxygen-containing gas and TEOS, wherein the first and the second process gases have different oxygen-to-TEOS ratio.

Abstract: There is provided a method of manufacturing a semiconductor device, the method including performing at least one of: processing, when forming the first redistribution layer, of forming the first electrically conductive material layer by growing the first electrically conductive material using electroplating, and polishing the first resist film and the first electrically conductive material layer from the main surface side to flatten their surfaces; and processing, when forming the second redistribution layer, forming the second electrically conductive material layer by growing the second electrically conductive material using electroplating, and polishing the second resist film and the second electrically conductive material layer from the main surface side to flatten their surfaces.

Abstract: A barrier layer is deposited over a layer of passivation including in an opening to a contact pad created in the layer of passivation. A column of three layers of metal is formed overlying the barrier layer and aligned with the contact pad and having a diameter that is about equal to the surface of the contact pad. The three metal layers of the column comprise, in succession when proceeding from the layer that is in contact with the barrier layer, a layer of pillar metal, a layer of under bump metal and a layer of solder metal. The layer of pillar metal is reduced in diameter, the barrier layer is selectively removed from the surface of the layer of passivation after which reflowing of the solder metal completes the solder bump of the invention.

Abstract: A method of forming a low-k dielectric layer or film includes forming a porous low-k dielectric layer or film over a wafer or substrate. Active bonding is introduced into the porous low-k dielectric layer or film to improve damage resistance and chemical integrity of the layer or film, to retain the low dielectric constant of the layer and film after subsequent processing. Introduction of the active bonding may be accomplished by introducing OH and/or H radicals into pores of the porous low-k dielectric layer or film to generate, in the case of a Si based low-k dielectric layer or film, Si—OH and/or Si—H active bonds. After further processing of the low-k dielectric film, the active bonding is removed from the low-k dielectric layer or film.

Abstract: A substantially planar surface coexposes conductive or semiconductor features and a dielectric etch stop material. A second dielectric material, different from the dielectric etch stop material, is deposited on the substantially planar surface. A selective etch etches a hole or trench in the second dielectric material, so that the etch stops on the conductive or semiconductor feature and the dielectric etch stop material. In a preferred embodiment the substantially planar surface is formed by filling gaps between the conductive or semiconductor features with a first dielectric such as oxide, recessing the oxide, filling with a second dielectric such as nitride, then planarizing to coexpose the nitride and the conductive or semiconductor features.

Abstract: Methods for forming voids in BEOL interconnect structures and BEOL interconnect structures. The methods include forming a temporary feature on a top surface of a first dielectric layer and depositing a second dielectric layer on the top surface of the first dielectric layer. The temporary feature is removed from the second dielectric layer to define a void in the second dielectric layer that is laterally adjacent to a conductive feature in the second dielectric layer. The void operates to reduce the effective dielectric constant of the second dielectric layer, which reduces parasitic capacitance between the conductive feature and other conductors in the BEOL interconnect structure.

Abstract: A method for manufacturing a semiconductor device is provided, the method includes forming a coated film by coating a solution containing a solvent and an organic component above an insulating film located above a semiconductor substrate and having a recess, baking the coated film at a first temperature which does not accomplish cross-linking of the organic component to obtain an organic film precursor, polishing the organic film precursor using a slurry containing resin particles to leave the organic film precursor in the recess, baking the left organic film precursor at a second temperature which is higher than the first temperature to remove the solvent to obtain a first organic film embedded in the recess, forming a second organic film on the insulating film, thereby obtaining an underlying film, forming an intermediate layer and a resist film successively above the underlying film, and subjecting the resist film to patterning exposure.

Abstract: There is provided a semiconductor device and method of fabricating the same that employs an insulation film of a borazine-based compound to provided enhanced contact between a material for insulation and that for interconnection, increased mechanical strength, and other improved characteristics. The semiconductor device includes a first insulation layer having a recess with a first conductor layer buried therein, an etching stopper layer formed on the first insulation layer, a second insulation layer formed on the etching stopper layer, a third insulation layer formed on the second insulation layer, and a second conductor layer buried in a recess of the second and third insulation layers. The second and third insulation layers are grown by chemical vapor deposition with a carbon-containing borazine compound used as a source material and the third insulation layer is smaller in carbon content than the second insulation layer.

Abstract: A semiconductor substrate includes semi-insulating portions beneath openings in a patterned hardmask film formed over a semiconductor substructure to a thickness sufficient to prevent charged particles from passing through the hardmask. The semi-insulating portions include charged particles and may extend deep into the semiconductor substrate and electrically insulate devices formed on opposed sides of the semi-insulating portions. The charged particles may advantageously be protons and further substrate portions covered by the patterned hardmask film are substantially free of the charged particles.

Abstract: A design structure is provided for interconnect structures containing various capping materials for electrical fuses and other related applications. The structure includes a first interconnect structure having a first interfacial structure and a second interconnect structure adjacent to the first structure. The second interconnect structure has second interfacial structure different from the first interfacial structure.

Abstract: The invention provides for polysilicon vias connecting conductive polysilicon layers formed at different heights. Polysilicon vias are advantageously used in a monolithic three dimensional memory array of charge storage transistors. Polysilicon vias according to the present invention can be used, for example, to connect the channel layer of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells formed above the first device level. Similarly, vias according to the present invention can be used to connect the wordline of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells.

Abstract: A device isolation film in a semiconductor device and a method for forming the same are provided. The method includes etching a middle portion of a device isolation film having a deposition structure including a Spin-On-Dielectric (SOD) oxide film and a High Density Plasma (HDP) oxide film to form a hole and filling an upper portion of the hole with an oxide film having poor step coverage characteristics to form a second hole extending along the middle portion of the device isolation film. The second hole serves as a buffer for stress generated at the interface between an oxide film, which can be a device isolation film, and a silicon layer, which can be a semiconductor substrate, thereby increasing the operating current of a transistor and improving the electrical characteristics of the resulting device.

Abstract: A substantially planar surface coexposes conductive or semiconductor features and a dielectric etch stop material. A second dielectric material, different from the dielectric etch stop material, is deposited on the substantially planar surface. A selective etch etches a hole or trench in the second dielectric material, so that the etch stops on the conductive or semiconductor feature and the dielectric etch stop material. In a preferred embodiment the substantially planar surface is formed by filling gaps between the conductive or semiconductor features with a first dielectric such as oxide, recessing the oxide, filling with a second dielectric such as nitride, then planarizing to coexpose the nitride and the conductive or semiconductor features.

Abstract: A method of fabricating a self-aligned contact pad (SAC) includes forming stacks of a conductive line and a capping layer on a semiconductor substrate, spacers covering sidewalls of the stacks, and an insulation layer filling gaps between the stacks and exposing the top of the capping layer, etching the capping layer to form damascene grooves, forming a plurality of first etching masks with a material different from that of the capping layer to fill the damascene grooves without covering the top of the insulation layer, and forming a second etching mask having an opening region that exposes some of the first etching masks and a portion of the insulation layer located between the first etching masks.

Abstract: An integrated circuit processing system is provided including providing a substrate having an integrated circuit, forming an interconnect layer over the integrated circuit, applying a low-K dielectric layer over the interconnect layer, applying an ultra low-K dielectric layer over the low-K dielectric layer, forming an opening through the ultra low-K dielectric layer and the low-K dielectric layer to the interconnect layer, depositing an interconnect metal in the opening, and chemical-mechanical polishing the interconnect metal and the ultra low-K dielectric layer.

Abstract: Methods for planarizing layers of a material, such as a dielectric, and interconnect structures formed by the planarization methods. The method includes depositing a first dielectric layer on a top surface of multiple conductive features and on a top surface of a substrate between the conductive features. A portion of the first dielectric layer is selectively removed from the top surface of at least one of the conductive features without removing a portion the first dielectric layer that is between the conductive features. A second dielectric layer is formed on the top surface of the at least one of the conductive features and on a top surface of the first dielectric layer, and a top surface of the second dielectric layer is planarized. A layer operating as an etch stop is located between the top surface of at least one of the conductive features and the second dielectric layer.

Abstract: A semiconductor device includes a semiconductor substrate and a via electrode. The via electrode has a first portion on the substrate and extends towards the substrate and has a plurality of spikes that extends from the first portion into the substrate, each of the spikes being spaced apart form one another.

Abstract: The present invention relates to a process that minimizes the cracking of low-k dielectric polymers. In an example embodiment, on a semiconductor substrate (200), there is a method of forming a composite dielectric disposed on a metal layer passivated with plasma deposited silicon oxide SiOx. The method comprises depositing a first layer of a first predetermined thickness of a spin-on dielectric on the metal layer protected with a plasma deposited silicon oxide SiOx. Next a thin stress relief layer of a second predetermined thickness is disposed on the first layer of spin-on-dielectric. Upon the thin stress-relief layer, a second layer of a third predetermined thickness of spin-on dielectric is deposited. Low-k spin-on dielectrics may include hydrogen silsequioxane (HSQ) and methyl silsequioxane (MSQ).

Abstract: Methods are provided for forming a structure that includes an air gap. In one embodiment, a method is provided for forming a damascene structure comprises depositing a porous low dielectric constant layer by a method including reacting an organosilicon compound and a porogen-providing precursor, depositing a porogen-containing material, and removing at least a portion of the porogen-containing material, depositing an organic layer on the porous low dielectric constant layer by reacting the porogen-providing precursor, forming a feature definition in the organic layer and the porous low dielectric constant layer, filing the feature definition with a conductive material therein, depositing a mask layer on the organic layer and the conductive material disposed in the feature definition, forming apertures in the mask layer to expose the organic layer, removing a portion or all of the organic layer through the apertures, and forming an air gap adjacent the conductive material.

Abstract: A method of fabricating a semiconductor device including a metal interconnect structure with a conductive region formed in a first dielectric layer, and an overlying, low-k, dielectric layer. A via and trench are formed in a dual damascene structure in the overlying dielectric layer, the via aligned with the conductive region and the trench. A sacrificial liner to release organic residues is deposited in the via and over the upper surface of the wafer, over which an organic planarization layer is deposited. The organic planarization layer is removed with a dry plasma etch, followed by a wet clean to remove the sacrificial liner. A diffusion barrier to separate the conductive material from the dielectric layers is deposited over the dual damascene structure and over the upper surface of the wafer. A conductive structure is formed over the diffusion barrier and polished to form an even surface for further processing steps.

Abstract: According to various embodiments, there are eSiGe CMOS devices and methods of making them. The method of making a substrate for a CMOS device can include providing a DSB silicon substrate including a first bonded to a second layer, wherein each layer has a (100) oriented surface and a first direction and a second direction and the first direction of the first layer is approximately aligned with the second direction of the second layer. The method can also include performing amorphization on a selected region of the first layer to form a localized amorphous silicon region and recrystallizing the localized amorphous silicon region across the interface using the second layer as a template, such that the first direction of the first layer in the selected region is approximately aligned with the first direction of the second layer.

Abstract: A semiconductor sensor device is formed using MEMS technology by placing a thin layer of single-crystal silicon, which includes semiconductor devices, over a cavity, which has been formed in a semiconductor material. The thin layer of single-crystal silicon can be formed by forming the semiconductor devices in the top surface of a single-crystal silicon wafer, thinning the silicon wafer to a desired thickness, and then dicing the thinned wafer to form silicon layers of a desired size. The MEMS device can be used to implement a pressure sensor, microphone, temperature sensor, and a joystick.

Abstract: A CMOS image sensor and a manufacturing method are disclosed. The gates of the transistors are formed in the active region of the unit pixel, and a diffusion region for the photo diode is defined by an ion implantation of impurities to the semiconductor substrate. The patterns of the photoresist that are the masking layer against ion implantation are formed on the semiconductor substrate in such a manner that they have the boundary portion of the isolation layer so as not to make the boundary of the defined photo diode contact with the boundary of the isolation layer. Damages by an ion implantation of impurities at the boundary portion between the diffusion region for the photo diode and the isolation layer are prevented, which reduces dark current of the COMS image sensor.

Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.

Abstract: A wiring pattern forming method which is a method of forming a wiring pattern by using a liquid droplet ejection method on a preset area on a substrate, includes: forming a bank on the preset area on the substrate; ejecting a functional liquid including a wiring pattern material on an area surrounded by the bank and drying the functional liquid to form the wiring pattern; and removing part of the bank so as to make a height of the bank and a thickness of the wiring pattern approximately the same.

Abstract: A method for forming semi-insulating portions in a semiconductor substrate provides depositing a hardmask film over a semiconductor substructure to a thickness sufficient to prevent charged particles from passing through the hardmask. The hardmask is patterned creating openings through which charged particles pass and enter the substrate during an implantation process. The semi-insulating portions may extend deep into the semiconductor substrate and electrically insulate devices formed on opposed sides of the semi-insulating portions. The charged particles may advantageously be protons and further substrate portions covered by the patterned hardmask film are substantially free of the charged particles.

Abstract: A CMOS image sensor may include at least one of: a semiconductor substrate over which a photodiode and transistors are formed; passivation layers formed over a semiconductor substrate; and color PRs buried in trenches formed in the passivation layers and formed to be higher than the trenches.

Abstract: Example embodiments of the present invention relate to an electrode structure, a method of manufacturing the electrode structure, a phase-change memory device having the electrode structure and a method of manufacturing the phase-change memory device. The electrode structure may include a pad, a first insulation layer pattern, a second insulation layer pattern and/or an electrode. The first insulation layer pattern may be formed on the pad. The first insulation layer pattern may have a first opening that partially exposes the pad. The second insulation layer pattern may be formed on the first insulation layer pattern. The second insulation layer pattern may have a second opening connected to the first opening. The electrode may be formed on the pad and filling the first and the second openings.

Abstract: A semiconductor device which is capable of avoiding an increase in pattern ratio and allowing wiring dummy patterns to improve global steps developed by CMP upon insertion of the dummy patterns which are different from an actual wiring pattern. The semiconductor device has a configuration wherein a gate wiring pattern is formed on a semiconductor substrate, a plurality of dummy patterns are provided therearound, and a BPSG oxide film which is flattened by CMP is formed on the gate wiring pattern and the dummy patterns as an interlayer insulating film. In the semiconductor device, the dummy patterns are formed so as to include pattern non-forming regions such as slits.

Abstract: A method for forming a single damascene and/or dual damascene interconnect structure, comprising: performing front end processing, depositing copper, annealing the copper, performing CMP planarization, performing a post copper CMP clean process, performing a BTA rinse, performing IPA drying process, performing doping during thermal ramp up and performing remaining back end processing.

Abstract: An integrated layer stack arrangement, an optical sensor and a method for producing an integrated layer stack arrangement is disclosed. Generally, an integrated layer stack arrangement includes a plurality of layer stacks arranged on top of each other, each layer stack including a metal layer and a dielectric layer arranged; at least one photodiode integrated into the plurality of layer stacks; a trench arranged above the last least one photodiode, the trench extending through at least a portion of the plurality of layer stacks so that light impinging on the plurality of layer stacks impinges on the integrated photodiode along the trench; a first passivation partial layer applied on the plurality of layer stacks; and a second passivation partial layer applied on the plurality of layer stacks and a bottom and walls of the trench.

Abstract: Integrated circuit package assemblies and packaging methods are provided. An integrated circuit package assembly includes a first circuit package including a first substrate having a top surface and a bottom surface, a first circuit die containing a programmable processor mounted to and electrically connected to the bottom surface of the first substrate, a bottom connector on the bottom surface of the first substrate and top circuit connections on the top surface of the first substrate, and a second circuit package mounted on the top surface of the first substrate and electrically connected to the top circuit connections of the first circuit package.

Abstract: A method of processing a substrate which enables a surface damaged layer and polishing remnants on the surface of an insulating film to be removed, and enable the amount removed of the surface damaged layer and polishing remnants to be controlled easily. An insulating film on a substrate, which has been revealed by chemical mechanical polishing, is exposed to an atmosphere of a mixed gas containing ammonia and hydrogen fluoride under a predetermined pressure. The insulating film which has been exposed to the atmosphere of the mixed gas is heated to a predetermined temperature.