Interconnections, Comprising Conductors And Dielectrics, For Carrying Current Between Separate Components Within Device (epo) Patents (Class 257/E21.575)

  • Patent number: 10566411
    Abstract: Device structures and fabrication methods for an on-chip resistor. A resistor body is formed on an interlayer dielectric layer of a contact level. A contact is formed that extends vertically through the interlayer dielectric layer. One or more dielectric layers are formed over the contact level, and a metal feature is formed in the one or more dielectric layers. The metal feature is at least in part in direct contact with a portion of the resistor body.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: February 18, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Atsushi Ogino, Lin Hu, Brian Greene
  • Patent number: 10504861
    Abstract: A semiconductor device and a method for manufacturing the semiconductor device which ensure improved reliability, permit further miniaturization, and suppress the increase in manufacturing cost. The semiconductor device includes: a pad electrode formed in the uppermost wiring layer of a multilayer wiring layer formed over a semiconductor substrate; a surface protective film formed in a manner to cover the pad electrode; an opening made in the surface protective film in a manner to expose the pad electrode partially; and a conductive layer formed over the pad electrode exposed at the bottom of the opening. The thickness of the conductive layer formed over the pad electrode is smaller than the thickness of the surface protective film formed over the pad electrode.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: December 10, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takashi Moriyama, Takashi Tonegawa
  • Patent number: 10502706
    Abstract: The present disclosure provides a biological field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device includes a plurality of micro wells having a sensing gate bottom and a number of stacked well portions. A bottom surface area of a well portion is different from a top surface area of a well portion directly below. The micro wells are formed by multiple etching operations through different materials, including a sacrificial plug, to expose the sensing gate without plasma induced damage.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Hsien Chang, Chun-Ren Cheng, Shih-Wei Lin, Yi-Shao Liu
  • Patent number: 10373911
    Abstract: Semiconductor device and fabrication method are provided. The method includes: providing a base substrate with a bottom metallic layer in the base substrate and a dielectric layer on the base substrate; forming interconnect openings through the dielectric layer and exposing the bottom metallic layer, where each interconnect openings includes a contacting hole and a groove on the contacting hole; forming a first conducting layer in the contacting hole, where the first conducting layer is made of a material having a first conductivity along a direction from the bottom metallic layer to a top surface of the first conducting layer; and after forming the first conducting layer, forming a second conducting layer in the groove, where the second conducting layer is made of a material having a second conductivity along a direction parallel to the top surface of the base substrate and the first conductivity is greater than the second conductivity.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: August 6, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTRING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Hai Yang Zhang, Cheng Long Zhang, Xin Jiang
  • Patent number: 10361206
    Abstract: A junctionless vertical gate transistor includes an active pillar vertically protruding from a substrate and including a first impurity region, a second impurity region and a third impurity region sequentially formed over the first impurity region; gate electrodes coupled to sidewalls of the second impurity region; and bit lines arranged in a direction of intersecting with the gate electrodes and each contacting the first impurity region. The first to the third impurity regions include impurities of the same polarity.
    Type: Grant
    Filed: August 12, 2015
    Date of Patent: July 23, 2019
    Assignees: SK HYNIX INC., KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Jung-Min Moon, Tae-Kyun Kim, Seok-Hee Lee
  • Patent number: 10256116
    Abstract: A method for packaging a circuit component, comprising: forming a first protruding pad on a first copper substrate and a through-hole in the first protruding pad; forming a second protruding pad on a second copper substrate and placing a circuit dice of the circuit component on the second protruding pad having a conductive paste coated thereon wherein a first electrode of the dice facing the second protruding pad; stacking the first copper substrate onto the second copper substrate with the first protruding pad having a conductive paste coated thereon aligned and pressing onto the circuit dice placed on the second protruding pad wherein a second electrode of the dice facing the first protruding pad; inserting a copper rod tightly into the through-hole until contacting with a conductive paste coated on the second substrate; heat-treating the stacked structure for the circuit dice and the copper rod to form secured electrical connection with the first and second copper substrates respectively and further formin
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: April 9, 2019
    Inventor: Chih-liang Hu
  • Patent number: 10141253
    Abstract: A semiconductor device includes a substrate, a first redistribution layer (RDL) over a first side of the substrate, one or more semiconductor dies over and electrically coupled to the first RDL, and an encapsulant over the first RDL and around the one or more semiconductor dies. The semiconductor device also includes connectors attached to a second side of the substrate opposing the first side, the connectors being electrically coupled to the first RDL. The semiconductor device further includes a polymer layer on the second side of the substrate, the connectors protruding from the polymer layer above a first surface of the polymer layer distal the substrate. A first portion of the polymer layer contacting the connectors has a first thickness, and a second portion of the polymer layer between adjacent connectors has a second thickness smaller than the first thickness.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: November 27, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Chi-Hsi Wu, Chen-Hua Yu, Po-Hao Tsai
  • Patent number: 10073806
    Abstract: An apparatus and methods are disclosed for a bidirectional front-end circuit included within a system on chip (SoC). The bidirectional front-end circuit includes a differential bidirectional terminal for receiving and transmitting signals. The bidirectional front-end circuit is configured to provide a first communication path between a first controller and a connector through the differential bidirectional terminal when operating in a first mode. And, the bidirectional front-end circuit is reconfigured to provide a second communication path between a second controller and the connector through the differential bidirectional terminal when operating in a second mode.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: September 11, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Zhi Zhu, Xiaohua Kong, Nir Gerber, Christian Josef Wiesner
  • Patent number: 10025559
    Abstract: A method of protecting a modular exponentiation calculation on a first number and an exponent, modulo a first modulo, executed by an electronic circuit using a first register or memory location and a second register or memory location, successively including, for each bit of the exponent: generating a random number; performing a modular multiplication of the content of the first register or memory location by that of the second register or memory location, and placing the result in one of the first and second registers or memory locations selected according to the state of the bit of the exponent; performing a modular squaring of the content of one of the first and second registers or memory locations selected according to the state of the exponent, and placing the result in this selected register or memory location, the multiplication and squaring operations being performed modulo the product of the first modulo by said random number.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: July 17, 2018
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Ibrahima Diop, Yanis Linge, Pierre-Yvan Liardet
  • Patent number: 9991158
    Abstract: A semiconductor device includes a substrate having an active area, a gate structure over the active area, a lower conductive layer over and electrically coupled to the active area, and an upper conductive layer over and electrically coupled to the lower conductive layer. The lower conductive layer is at least partially co-elevational with the gate structure. The lower conductive layer includes first and second conductive segments spaced from each other. The upper conductive layer includes a third conductive segment overlapping the first and second conductive segments. The third conductive segment is electrically coupled to the first conductive segment, and electrically isolated from the second conductive segment.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: June 5, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tung-Heng Hsieh, Hui-Zhong Zhuang, Chung-Te Lin, Sheng-Hsiung Wang, Ting-Wei Chiang, Li-Chun Tien, Tsung-Chieh Tsai
  • Patent number: 9947622
    Abstract: An electrical device including an opening in a low-k dielectric material, and a copper including structure present within the opening for transmitting electrical current. A liner is present between the opening and the copper including structure. The liner includes a superlattice structure comprised of a metal oxide layer, a metal layer present on the metal oxide layer, and a metal nitride layer that is present on the metal layer. A first layer of the superlattice structure that is in direct contact with the low-k dielectric material is one of said metal oxide layer and a final layer of the superlattice structure that is in direct contact with the copper including structure is one of the metal nitride layers.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: April 17, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Donald F. Canaperi, Daniel C. Edelstein, Alfred Grill, Son V. Nguyen, Takeshi Nogami, Deepika Priyadarshini, Hosadurga Shobha
  • Patent number: 9859150
    Abstract: A method for manufacturing a semiconductor device include forming a dielectric layer over an underlying layer; forming an etch barrier over the dielectric layer, wherein a partial via opening is formed in the etch barrier and exposes a lower portion of the etch barrier; forming an assist-etch barrier over the etch barrier to fill the partial via opening; patterning the assist-etch barrier to form an initial trench opening in the assist-etch barrier, wherein the initial trench opening communicates with the partial via opening; patterning the lower portion of the etch barrier exposed by the partial via opening to form a final via opening in the etch barrier; patterning the dielectric layer exposed by the final via opening to form an initial via hole in the dielectric layer; patterning the etch barrier exposed by the initial trench opening to form a final trench opening in the etch barrier; patterning a lower portion of the dielectric layer exposed by the initial via hole to form a final via hole in the dielectr
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: January 2, 2018
    Assignee: SK Hynix Inc.
    Inventor: Jin-Gi Jung
  • Patent number: 9859153
    Abstract: Aluminum oxide films characterized by a dielectric constant (k) of less than about 7 (such as between about 4-6) and having a density of at least about 2.5 g/cm3 (such as about 3.0-3.2 g/cm3) are deposited on partially fabricated semiconductor devices over both metal and dielectric to serve as etch stop layers. The films are deposited using a deposition method that does not lead to oxidative damage of the metal. The deposition involves reacting an aluminum-containing precursor (e.g., a trialkylaluminum) with an alcohol and/or aluminum alkoxide. In one implementation the method involves flowing trimethylaluminum to the process chamber housing a substrate having an exposed metal and dielectric layers; purging and/or evacuating the process chamber; flowing t-butanol to the process chamber and allowing it to react with trimethylaluminum to form an aluminum oxide film and repeating the process steps until the film of desired thickness is formed.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: January 2, 2018
    Assignee: Lam Research Corporation
    Inventors: Meliha Gozde Rainville, Nagraj Shankar, Kapu Sirish Reddy, Dennis M. Hausmann
  • Patent number: 9824981
    Abstract: A semiconductor device provided on a semiconductor substrate includes an element region including an element, a moisture-resistant frame surrounding the element region, an insulating layer provided between the moisture-resistant frame and an outer peripheral edge of the semiconductor device and on the semiconductor substrate, a first metal line extending along the outer peripheral edge and provided in the insulating layer, and a groove provided in the insulating layer.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: November 21, 2017
    Assignee: SOCIONEXT INC.
    Inventors: Tomoyuki Yamada, Fumio Ushida, Shigetoshi Takeda, Tomoharu Awaya, Koji Banno, Takayoshi Minami
  • Patent number: 9691705
    Abstract: An electrical device including an opening in a low-k dielectric material, and a copper including structure present within the opening for transmitting electrical current. A liner is present between the opening and the copper including structure. The liner includes a superlattice structure comprised of a metal oxide layer, a metal layer present on the metal oxide layer, and a metal nitride layer that is present on the metal layer. A first layer of the superlattice structure that is in direct contact with the low-k dielectric material is one of said metal oxide layer and a final layer of the superlattice structure that is in direct contact with the copper including structure is one of the metal nitride layers.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: June 27, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Donald F. Canaperi, Daniel C. Edelstein, Alfred Grill, Son V. Nguyen, Takeshi Nogami, Deepika Priyadarshini, Hosadurga Shobha
  • Patent number: 9691719
    Abstract: A semiconductor device is a semiconductor device in which one chip region is formed through divided exposure. An interlayer insulating film has a via and an interconnection trench in an element formation region and has a guard ring hole in a guard ring region. An interconnection conductive layer is formed in the via and the interconnection trench. A guard ring conductive layer is formed in the guard ring hole. A minimum dimension of a width of the guard ring conductive layer is greater than a minimum dimension of a width of the interconnection conductive layer in the via.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: June 27, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Kazuo Tomita
  • Patent number: 9685407
    Abstract: Optimized metal wires for resistance or electromigration, methods of manufacturing thereof and design methodologies are disclosed. The method includes depositing metal material within openings and on a surface of dielectric material resulting in metal filled openings and a topography of recessed areas aligned with the metal filled openings. The method further includes depositing an alloying material over the metal material, including within the recessed areas. The method further includes planarizing the metal material, leaving the alloying material within the recessed areas. The method further includes diffusing the alloying material into the metal material forming alloyed regions self-aligned with the metal filled openings.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: June 20, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lawrence A. Clevenger, Baozhen Li, Kirk D. Peterson
  • Patent number: 9658275
    Abstract: An apparatus includes three components. The first component includes a first transmission line; the second component is coupled with the first component and includes a second transmission line; and the third component electrically coupled with the first component and/or the second component. The transmission lines each include a substrate with a p-well or n-well within the substrate and a shielding layer over the p-well or n-well. The transmission lines also each include a plurality of intermediate conducting layers over the shielding layer, the plurality of intermediate conducting layers coupled by a plurality of vias. The transmission lines further each include a top conducting layer over the plurality of intermediate conducting layers.
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: May 23, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiao-Tsung Yen, Chin-Wei Kuo, Ho-Hsiang Chen, Sa-Lly Liu, Yu-Ling Lin
  • Patent number: 9536858
    Abstract: Provided are a semiconductor device including an interposer having a relatively thin thickness without a through silicon via and a method of manufacturing the same. The method of manufacturing a semiconductor device includes forming an interposer including a redistribution layer and a dielectric layer on a dummy substrate, connecting a semiconductor die to the redistribution layer facing an upper portion of the interposer, encapsulating the semiconductor die by using an encapsulation, removing the dummy substrate from the interposer, and connecting a bump to the redistribution layer facing a lower portion of the interposer.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: January 3, 2017
    Assignee: AMKOR TECHNOLOGY, INC.
    Inventors: Won Chul Do, Doo Hyun Park, Jong Sik Paek, Ji Hun Lee, Seong Min Seo
  • Patent number: 9508647
    Abstract: A single damascene interconnect structure which includes a first layer that includes a first dielectric material having a first filled opening that has a barrier layer of a refractory material with Cu filling the first filled opening. Also included is a second layer of a second dielectric material having a second filled opening that has a sidewall layer which includes a compound of a metal, O, and Si such that the metal is Mn, Ti and Al, and with Cu filling the second filled opening. The compound is in direct contact with the second dielectric material. The first layer is adjacent to the second layer and the first filled opening is aligned with the second filled opening so that the first filled opening is a via and the second filled opening is a trench.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: November 29, 2016
    Assignee: International Business Machines Corporation
    Inventors: Shyng-Tsong Chen, Daniel C. Edelstein, Takeshi Nogami
  • Patent number: 9502308
    Abstract: A method includes forming first and second contact openings so as to expose first and second source/drain regions, respectively, of a semiconductor material. At least one process operation is performed to selectively form a first liner only in the first contact opening. The first liner covers a bottom portion of the first contact opening and exposes a sidewall portion of the first contact opening. A second liner is formed in the first and second contact openings. At least one process operation is performed so as to form a conductive material above the second liner to fill the first and second contact openings and define first and second contacts conductively coupled to the first and second source/drain regions, respectively.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: November 22, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Chanro Park, Hoon Kim, Ruilong Xie, Min Gyu Sung
  • Patent number: 9472503
    Abstract: An electrical device including an opening in a low-k dielectric material, and a copper including structure present within the opening for transmitting electrical current. A liner is present between the opening and the copper including structure. The liner includes a superlattice structure comprised of a metal oxide layer, a metal layer present on the metal oxide layer, and a metal nitride layer that is present on the metal layer. A first layer of the superlattice structure that is in direct contact with the low-k dielectric material is one of said metal oxide layer and a final layer of the superlattice structure that is in direct contact with the copper including structure is one of the metal nitride layers.
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: October 18, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Donald F. Canaperi, Daniel C. Edelstein, Alfred Grill, Son V. Nguyen, Takeshi Nogami, Deepika Priyadarshini, Hosadurga Shobha
  • Patent number: 9373576
    Abstract: An integrated circuit (IC) package substrate is provided. In one embodiment, the IC package substrate includes a dielectric layer having first and second opposing surfaces and a matrix of pillars disposed in the dielectric layer and arranged to receive a matrix of conductive elements of an IC die. Each pillar of the matrix of pillars is exposed at the first surface of the dielectric layer. Each pillar of the matrix of pillars extends through the dielectric layer to contact a metal layer attached to the second surface of the dielectric layer.
    Type: Grant
    Filed: January 9, 2014
    Date of Patent: June 21, 2016
    Assignee: Broadcom Corporation
    Inventor: Kwok Cheung Tsang
  • Patent number: 9349728
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a metal-oxide semiconductor (MOS) transistor thereon and a first interlayer dielectric (ILD) layer surrounding the MOS transistor; forming a source layer, a drain layer, a first opening between the source layer and the drain layer, and a second ILD layer on the MOS transistor and the first ILD layer, wherein the top surfaces of the source layer, the drain layer, and the second ILD layer are coplanar; forming a channel layer on the second ILD layer, the source layer, and the drain layer and into the first opening; and performing a first planarizing process to remove part of the channel layer so that the top surface of the channel layer is even with the top surfaces of the source layer and the drain layer.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: May 24, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Fu Hsu, Bo-Rong Chen
  • Patent number: 9305782
    Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.
    Type: Grant
    Filed: October 6, 2014
    Date of Patent: April 5, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Baosuo Zhou, Mirzafer K. Abatchev, Ardavan Niroomand, Paul A. Morgan, Shuang Meng, Joseph Neil Greely, Brian J. Coppa
  • Patent number: 9041122
    Abstract: Provided are a semiconductor device and a method of manufacturing the semiconductor device. In order to improve reliability by solving a problem of conductivity that may occur when an air spacer structure that may reduce a capacitor coupling phenomenon between a plurality of conductive lines is formed, there are provided a semiconductor device including: a substrate having an active region; a contact plug connected to the active region; a landing pad spacer formed to contact a top surface of the contact plug; a contact conductive layer formed to contact the top surface of the contact plug and formed in a space defined by the landing pad spacer; a metal silicide layer formed on the contact conductive layer; and a landing pad connected to the contact conductive layer in a state in which the metal silicide layer is disposed between the landing pad and the contact conductive layer, and a method of manufacturing the semiconductor device.
    Type: Grant
    Filed: May 1, 2014
    Date of Patent: May 26, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-seok Yoo, Young-seok Kim, Han-jin Lim, Jeon-Il Lee
  • Patent number: 9041203
    Abstract: A system and method for manufacturing a semiconductor device including multi-layer bitlines. The location of the bitlines in multiple layers provides for increased spacing and increased width thereby overcoming the limitations of the pitch dictated by the semiconductor fabrication process used. The bitlines locations in multiple layers thus allows the customization of the spacing and width according to the use of a semiconductor device.
    Type: Grant
    Filed: October 10, 2008
    Date of Patent: May 26, 2015
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Zubin Patel, Nian Yang, Fan Wan Lai, Alok Nandini Roy
  • Patent number: 9029260
    Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a patterned dielectric layer having a plurality of first openings. The method includes forming a conductive liner layer over the patterned dielectric layer, the conductive liner layer partially filling the first openings. The method includes forming a trench mask layer over portions of the conductive liner layer outside the first openings, thereby forming a plurality of second openings, a subset of which are formed over the first openings. The method includes depositing a conductive material in the first openings to form a plurality of vias and in the second openings to form a plurality of metal lines. The method includes removing the trench mask layer.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: May 12, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Chieh Lin, Hung-Wen Su, Minghsing Tsai, Syun-Ming Jang
  • Patent number: 9018751
    Abstract: A semiconductor module system includes a module substrate and a semiconductor substrate having a through wire interconnect bonded to an electrode on the module substrate. The through wire interconnect includes a via, a wire in the via having a first end bonded to a substrate contact on the semiconductor substrate and a polymer layer at least partially encapsulating the wire. The semiconductor module system can also include a second substrate stacked on the semiconductor substrate having a second through wire interconnect in electrical contact with the through wire interconnect.
    Type: Grant
    Filed: April 21, 2014
    Date of Patent: April 28, 2015
    Assignee: Micron Technology, Inc.
    Inventors: David R Hembree, Alan G. Wood
  • Patent number: 9006098
    Abstract: A method of improving electrical interconnections between two electrical elements is made available by providing a meta-material overlay in conjunction with the electrical interconnection. The meta-material overlay is designed to make the electrical signal propagating via the electrical interconnection to act as though the permittivity and permeability of the dielectric medium within which the electrical interconnection is formed are different than the real component permittivity and permeability of the dielectric medium surrounding the electrical interconnection. In some instances the permittivity and permeability resulting from the meta-material cause the signal to propagate as if the permittivity and permeability have negative values. Accordingly the method provides for electrical interconnections possessing enhanced control and stability of impedance, reduced noise, and reduced loss.
    Type: Grant
    Filed: August 22, 2008
    Date of Patent: April 14, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Christopher Wyland
  • Patent number: 9006028
    Abstract: This document describes the fabrication and use of multilayer ceramic substrates, having one or more levels of internal thick film metal conductor patterns, wherein any or all of the metal vias intersecting one or both of the major surface planes of the substrates, extend out of the surface to be used for making flexible, temporary or permanent interconnections, to terminals of an electronic component. Such structures are useful for wafer probing, and for packaging, of semiconductor devices.
    Type: Grant
    Filed: September 11, 2009
    Date of Patent: April 14, 2015
    Inventors: Ananda H. Kumar, Ashish Asthana, Farooq Quadri
  • Patent number: 9000593
    Abstract: A substrate for a semiconductor device is provided. The substrate includes a first metal line, a second metal line, a metal support part, a first insulating part, and a second insulating part. The first metal line is electrically connected to a first electrode of the semiconductor device. The second metal line is electrically connected to a second electrode of the semiconductor device and spaced apart from the first metal line. The metal support part is disposed between the first metal line and the second metal line. The first insulating part is disposed between the first metal line and the metal support part and configured to electrically insulate the first metal line from the metal support part. The second insulating part is disposed between the second metal line and the metal support part and configured to electrically insulate the second metal line from the metal support part.
    Type: Grant
    Filed: August 7, 2012
    Date of Patent: April 7, 2015
    Assignee: Research & Business Foundation Sungkyunkwan University
    Inventors: Su Jeong Suh, Hwa Sun Park, Hyeong Chul Youn
  • Patent number: 8987034
    Abstract: A method of manufacturing a backside illumination image sensor includes forming an epitaxial layer on a silicon (Si) substrate, and forming an inter-metal dielectric (IMD) on the epitaxial layer. The method includes forming a trench in one side region of the epitaxial layer, forming an insulating layer at a side wall and bottom of the trench, forming a color filter and microlens on the IMD, bonding a support wafer onto the IMD with the color filter and microlens formed therein, and/or removing the Si substrate.
    Type: Grant
    Filed: January 14, 2013
    Date of Patent: March 24, 2015
    Assignee: Dongbu Hitek Co., Ltd.
    Inventors: Jong Taek Hwang, Han Choon Lee
  • Patent number: 8987913
    Abstract: Disclosed herein is a deformable network structure, which includes a first device portion, a second device portion and at least one connector interconnecting between the first device portion and the second device portion. Moreover, the second device portion can be electrically connected to the first device portion through one of the connectors. The first and second device portions respectively have a first and a second center. Each of the connectors may be deformable from an initial state to a final state, such that a first distance between the first and second centers in the final state varies by at least 10% of a second distance between the first and second centers in the initial state.
    Type: Grant
    Filed: May 27, 2013
    Date of Patent: March 24, 2015
    Assignee: MonoLithe Semiconductor Inc.
    Inventors: Kevin T. Y. Huang, Hsiao-Huey Huang
  • Patent number: 8963240
    Abstract: This invention discloses a semiconductor power device that includes a plurality of power transistor cells surrounded by a trench opened in a semiconductor substrate. At least one of the cells constituting an active cell has a source region disposed next to a trenched gate electrically connecting to a gate pad and surrounding the cell. The trenched gate further has a bottom-shielding electrode filled with a gate material disposed below and insulated from the trenched gate. At least one of the cells constituting a source-contacting cell surrounded by the trench with a portion functioning as a source connecting trench is filled with the gate material for electrically connecting between the bottom-shielding electrode and a source metal disposed directly on top of the source connecting trench.
    Type: Grant
    Filed: April 26, 2013
    Date of Patent: February 24, 2015
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Anup Bhalla, Sik K. Lui
  • Patent number: 8957465
    Abstract: Gate to contact shorts are reduced by forming dielectric caps in replaced gate structures. Embodiments include forming a replaced gate structure on a substrate, the replaced gate structure including an ILD having a cavity, a first metal on a top surface of the ILD and lining the cavity, and a second metal on the first metal and filling the cavity, planarizing the first and second metals, forming an oxide on the second metal, removing the oxide, recessing the first and second metals in the cavity, forming a recess, and filling the recess with a dielectric material. Embodiments further include dielectric caps having vertical sidewalls, a trapezoidal shape, a T-shape, or a Y-shape.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: February 17, 2015
    Assignees: GLOBALFOUNDRIES Singapore Pte. Ltd., International Business Machines Corporation
    Inventors: Ruilong Xie, Balasubramanian Pranatharthi Haran, David V. Horak, Su Chen Fan
  • Patent number: 8957483
    Abstract: A method of forming an electrically conductive buried line and an electrical contact thereto includes forming of a longitudinally elongated conductive line within a trench in substrate material. A longitudinal end part thereof within the trench is of spoon-like shape having a receptacle. The receptacle is filled with conductive material. Insulative material is formed over the conductive material that is within the receptacle. A contact opening is formed over the conductive material that is within the receptacle. Conductor material is formed in the contact opening in electrical connection with the second conductive material that is within the receptacle. Other method and device implementations are disclosed.
    Type: Grant
    Filed: June 5, 2013
    Date of Patent: February 17, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Brent Gilgen
  • Patent number: 8957523
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate comprises a plurality of metal layers. The semiconductor device also includes dielectric posts disposed in the metal layers. The density of the dielectric posts in the metal layers is equal to about 15-25%.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: February 17, 2015
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Fan Zhang, Wei Shao, Juan Boon Tan, Yeow Kheng Lim, Mahesh Bhatkar, Soh Yun Siah
  • Patent number: 8951916
    Abstract: A number of first hard mask portions are formed on a dielectric layer to vertically shadow a respective one of a number of underlying gate structures. A number of second hard mask filaments are formed adjacent to each side surface of each first hard mask portion. A width of each second hard mask filament is set to define an active area contact-to-gate structure spacing. A first passage is etched between facing exposed side surfaces of a given pair of neighboring second hard mask filaments and through a depth of the semiconductor wafer to an active area. A second passage is etched through a given first hard mask portion and through a depth of the semiconductor wafer to a top surface of the underlying gate structure. An electrically conductive material is deposited within both the first and second passages to respectively form an active area contact and a gate contact.
    Type: Grant
    Filed: September 23, 2013
    Date of Patent: February 10, 2015
    Assignee: Tela Innovations, Inc.
    Inventor: Michael C. Smayling
  • Patent number: 8952528
    Abstract: A semiconductor package is provided. The semiconductor package includes a semiconductor chip having opposite first and second surfaces; an RDL structure formed on the first surface of the semiconductor chip and having opposite third and fourth surfaces and a plurality of first conductive through holes penetrating the third and fourth surfaces thereof, wherein the RDL structure is formed on the semiconductor chip through the fourth surface thereof and electrically connected to the semiconductor chip through a plurality of first conductive elements, and the third surface of the RDL structure has a redistribution layer formed thereon; a plurality of conductive bumps formed on the redistribution layer; and an encapsulant formed on the first surface of the semiconductor chip for encapsulating the RDL structure, wherein the conductive bumps are embedded in and exposed from the encapsulant. The invention effectively prevents warpage of the semiconductor package and improves the electrical connection significantly.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: February 10, 2015
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chien-Feng Chan, Chun-Tang Lin, Yi Che Lai
  • Patent number: 8952538
    Abstract: A semiconductor device includes: an integrated circuit having an electrode pad; a first insulating layer disposed on the integrated circuit; a redistribution layer including a plurality of wirings and disposed on the first insulating layer, at least one of the plurality of wirings being electrically coupled to the electrode pad; a second insulating layer having a opening on at least a portion of the plurality of wirings; a metal film disposed on the opening and on the second insulating layer, and electrically coupled to at least one of the plurality of wirings; and a solder bump the solder bump overhanging at least one of the plurality of wirings not electrically coupled to the metal film.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: February 10, 2015
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Hirohisa Matsuki
  • Patent number: 8946884
    Abstract: A substrate-less interposer for a stacked silicon interconnect technology (SSIT) product, includes: a plurality of metallization layers, at least a bottom most layer of the metallization layers comprising a plurality of metal segments, wherein each of the plurality of metal segments is formed between a top surface and a bottom surface of the bottom most layer of the metallization layers, and the metal segments are separated by dielectric material in the bottom most layer; and a dielectric layer formed on the bottom surface of the bottom most layer, wherein the dielectric layer includes one or more openings for providing contact to the plurality of metal segments in the bottom most layer.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: February 3, 2015
    Assignee: Xilinx, Inc.
    Inventors: Woon-Seong Kwon, Suresh Ramalingam, Namhoon Kim, Joong-Ho Kim
  • Patent number: 8937009
    Abstract: Disclosed are a method for metallization during semiconductor wafer processing and the resulting structures. In this method, a passivation layer is patterned with first openings aligned above and extending vertically to metal structures below. A mask layer is formed and patterned with second openings aligned above the first openings, thereby forming two-tier openings extending vertically through the mask layer and passivation layer to the metal structures below. An electrodeposition process forms, in the two-tier openings, both under-bump pad(s) and additional metal feature(s), which are different from the under-bump pad(s) (e.g., a wirebond pad; a final vertical section of a crackstop structure; and/or a probe pad). Each under-bump pad and additional metal feature initially comprises copper with metal cap layers thereon.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: January 20, 2015
    Assignee: International Business Machines Corporation
    Inventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, Karen P. McLaughlin, Ekta Misra, Christopher D. Muzzy, Eric D. Perfecto, Wolfgang Sauter
  • Patent number: 8927359
    Abstract: The present disclosure provides a method of semiconductor device fabrication including forming a multi-composition ILD layer by forming a first portion of an inter-layer dielectric (ILD) layer on a semiconductor substrate; and forming a second portion of an ILD layer on the first portion of the ILD layer. The second portion may have a greater silicon content than the first portion. For example, the second portion may be a silicon rich oxide.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: January 6, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Su-Hao Liu, Chun-Yi Chang, Ming-Feng Lin, Sheng-Wen Yu, Ziwei Fang
  • Patent number: 8916977
    Abstract: A semiconductor device includes a semiconductor substrate configured to include a plurality of active regions that are stretched in parallel to each other, a plurality of first contact plugs and the plurality of active regions, wherein each active region is coupled with a corresponding first contact plug, and a contact pad configured to couple with a given number of first contact plugs among the plurality of first contact plugs. Misalignment occurring at the ends of a series of drain contacts may be prevented, and the size of well-pickup contacts may be decreased by forming contact plugs that are coupled with drain regions with the same distance to a well-pickup contact region without additionally forming well-pickup contact plugs and using the contact plugs as well-pickup contact plugs. Therefore, loss of a substrate may be minimized, and burden of Optical Proximity Correction (OPC) is relieved, reducing Turn-Around Time (TAT).
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: December 23, 2014
    Assignee: SK Hynix Inc.
    Inventor: Dae-Sung Eom
  • Patent number: 8906799
    Abstract: A method and structure for preventing integrated circuit failure due to electromigration and time dependent dielectric breakdown is disclosed. A randomly patterned metal cap layer is selectively formed on the metal interconnect lines (typically copper (Cu)) with an interspace distance between metal cap segments that is less than the critical length (for short-length effects). Since the diffusivity is lower for the Cu/metal cap interface than for the Cu/dielectric cap interface, the region with a metal cap serves as a diffusion barrier.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: December 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Ronald G. Filippi, Erdem Kaltalioglu, Wai-Kin Li, Ping-Chuan Wang, Lijuan Zhang
  • Patent number: 8883626
    Abstract: A method is provided for fabricating an interconnection structure. The method includes providing a semiconductor substrate having certain semiconductor devices inside, a dielectric layer covering the semiconductor devices, and vias inside the dielectric layer connecting with connection pads of the semiconductor devices. The method also includes forming a first conductive layer on the semiconductor substrate, and forming a second conductive layer with smaller grain sizes by doping the first conductive layer. Further, the method includes forming an interconnection pad by patterning the second conductive layer, and forming a connection wire on the interconnection pad.
    Type: Grant
    Filed: October 23, 2013
    Date of Patent: November 11, 2014
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Ming Zhou
  • Patent number: 8883630
    Abstract: A method of forming contact holes includes: forming a first conductive layer and a second conductive layer; forming an insulating layer on the first conductive layer and the second conductive layer; forming a photoresist pattern which exposes first and second etch surfaces of a top surface of the insulating layer; performing a first etching process on the insulating layer at a first etching rate; and performing a second etching process on the insulating layer at a second etching rate which is higher than the first etching rate, after a top surface of the first conductive layer is exposed through the insulating layer. The first etch surface is on the first conductive layer, the second etch surface is on the second conductive layer, and a distance between the second etch surface and the second conductive layer is greater than a distance between the first etch surface and the first conductive layer.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: November 11, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventor: Yong Jae Jang
  • Patent number: 8878252
    Abstract: A structure comprises a substrate, a mask, a buffer/nucleation layer, and a group III-V compound semiconductor material. The substrate has a top surface and has a recess from the top surface. The recess includes a sidewall. The first mask is the top surface of the substrate. The buffer/nucleation layer is along the sidewall, and has a different material composition than a material composition of the sidewall. The III-V compound semiconductor material continuously extends from inside the recess on the buffer/nucleation layer to over the first mask.
    Type: Grant
    Filed: February 12, 2014
    Date of Patent: November 4, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Lin Yu, Chen-Hua Yu, Ding-Yuan Chen, Wen-Chih Chiou
  • Patent number: 8865588
    Abstract: A method of manufacturing a semiconductor device includes forming a first interconnection and a second interconnection above a semiconductor substrate, forming a first sidewall insulating film on a side wall of the first interconnection, and a second sidewall insulating film on a side wall of the second interconnection, forming a conductive film above the semiconductor substrate with the first interconnection, the first sidewall insulating film, the second interconnection and the second sidewall insulating film formed on, and selectively removing the conductive film above the first interconnection and the second interconnection to form in a region between the first interconnection and the second interconnection a third interconnection formed of the conductive film and spaced from the first interconnection and the second interconnection by the first sidewall insulating film and the second sidewall insulating film.
    Type: Grant
    Filed: December 24, 2013
    Date of Patent: October 21, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Takeshi Kagawa