Characterized By Formation And Post Treatment Of Conductors, E.g., Patterning (epo) Patents (Class 257/E21.582)
  • Patent number: 11955379
    Abstract: A metal adhesion layer may be formed on a bottom and a sidewall of a trench prior to formation of a metal plug in the trench. A plasma may be used to modify the phase composition of the metal adhesion layer to increase adhesion between the metal adhesion layer and the metal plug. In particular, the plasma may cause a shift or transformation of the phase composition of the metal adhesion layer to cause the metal adhesion layer to be composed of a (111) dominant phase. The (111) dominant phase of the metal adhesion layer increases adhesion between the metal adhesion layer.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pei-Wen Wu, Chun-I Tsai, Chi-Cheng Hung, Jyh-Cherng Sheu, Yu-Sheng Wang, Ming-Hsing Tsai
  • Patent number: 11923244
    Abstract: Embodiments of the present disclosure generally relate to subtractive metals, subtractive metal semiconductor structures, subtractive metal interconnects, and to processes for forming such semiconductor structures and interconnects. In an embodiment, a process for fabricating a semiconductor structure is provided. The process includes performing a degas operation on the semiconductor structure and depositing a liner layer on the semiconductor structure. The process further includes performing a sputter operation on the semiconductor structure, and depositing, by physical vapor deposition, a metal layer on the liner layer, wherein the liner layer comprises Ti, Ta, TaN, or combinations thereof, and a resistivity of the metal layer is about 30 ??·cm or less.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: March 5, 2024
    Assignee: Applied Materials, Inc.
    Inventors: He Ren, Hao Jiang, Shi You, Mehul B. Naik
  • Patent number: 11908738
    Abstract: A method of making a semiconductor component includes depositing a first metal material onto a structure having a first cavity and a second cavity such that the first metal material fills the first cavity and forms a first lining on exposed surfaces of the second cavity. The method further includes depositing a dielectric material onto the structure such that the dielectric material forms a second lining on exposed surfaces of the first lining. The method further includes depositing a second metal material onto the structure such that the second metal material fills remaining volume in the second cavity.
    Type: Grant
    Filed: October 18, 2021
    Date of Patent: February 20, 2024
    Assignee: International Business Machines Corporation
    Inventors: Nicholas Anthony Lanzillo, Chih-Chao Yang
  • Patent number: 11901228
    Abstract: In an embodiment, a method includes forming a first conductive feature in a first inter-metal dielectric (IMD) layer; depositing a blocking film over and physically contacting the first conductive feature; depositing a first dielectric layer over and physically contacting the first IMD layer; depositing a second dielectric layer over and physically contacting the first dielectric layer; removing the blocking film; depositing an etch stop layer over any physically contacting the first conductive feature and the second dielectric layer; forming a second IMD layer over the etch stop layer; etching an opening in the second IMD layer and the etch stop layer to expose the first conductive feature; and forming a second conductive feature in the opening.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: February 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cai-Ling Wu, Hsiu-Wen Hsueh, Wei-Ren Wang, Po-Hsiang Huang, Chii-Ping Chen, Jen Hung Wang
  • Patent number: 11891693
    Abstract: A semiconductor processing device can include a reactor assembly comprising a reaction chamber sized to receive a substrate therein. An exhaust line can be in fluid communication with the reaction chamber, the exhaust line configured to transfer gas out of the reaction chamber. A valve can be disposed along the exhaust line to regulate the flow of the gas along the exhaust line. A control system can be configured to operate in an open loop control mode to control the operation of the valve.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: February 6, 2024
    Assignee: ASM IP Holding B.V.
    Inventors: Jereld Lee Winkler, Cheuk Li, Michael F. Schultz, John Kevin Shugrue
  • Patent number: 11876047
    Abstract: A semiconductor component includes an insulative layer having a lowermost surface arranged on top of a bottom dielectric material. The semiconductor component further includes a first interconnect structure arranged in the bottom dielectric material such that an uppermost surface of the first interconnect structure is arranged at a first height relative to the lowermost surface of the insulative layer. The semiconductor component further includes a pillar connected to the first interconnect structure and extending through the insulative layer. The semiconductor component further includes a second interconnect structure arranged in the bottom dielectric material such that an uppermost surface of the second interconnect structure is arranged at a second height relative to the lowermost surface of the insulative layer. The second height is different than the first height.
    Type: Grant
    Filed: September 14, 2021
    Date of Patent: January 16, 2024
    Assignee: International Business Machines Corporation
    Inventors: Saumya Sharma, Ashim Dutta, Tianji Zhou, Chih-Chao Yang
  • Patent number: 11823901
    Abstract: The present disclosure provides systems and methods for processing channel structures of substrates that include positioning the substrate in a first processing chamber having a first processing volume. The substrate includes a channel structure with high aspect ratio features having aspect ratios greater than about 20:1. The method includes forming a silicon-containing layer over the channel structure to a hydrogen-or-deuterium plasma in the first processing volume at a flow rate of about 10 sccm to about 5000 sccm. The substrate is maintained at a temperature of about 100° C. to about 1100° C. during the exposing, the exposing forming a nucleated substrate. Subsequent to the exposing a thermal anneal operation is performed on the substrate.
    Type: Grant
    Filed: February 12, 2021
    Date of Patent: November 21, 2023
    Assignee: APPLIED MATERIALS INC.
    Inventors: Xinming Zhang, Abhilash J. Mayur, Shashank Sharma, Norman L. Tam, Matthew Spuller
  • Patent number: 11810915
    Abstract: Disclosed is a semiconductor package including: a redistribution substrate; at least one passive device in the redistribution substrate, the passive device including a first terminal and a second terminal; and a semiconductor chip on a top surface of the redistribution substrate, the semiconductor chip vertically overlapping at least a portion of the passive device, wherein the redistribution substrate includes: a dielectric layer in contact with a first lateral surface, a second lateral surface opposite to the first lateral surface, and a bottom surface of the passive device; a lower conductive pattern on the first terminal; a lower seed pattern provided between the first terminal and the conductive pattern, and directly connected to the first terminal; a first upper conductive pattern on the second terminal and a first upper seed pattern provided between the second terminal and the first upper conductive pattern, and directly connected to the second terminal.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: November 7, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyoung Lim Suk, Seokhyun Lee, Jaegwon Jang
  • Patent number: 11812610
    Abstract: Electronic devices (e.g., semiconductor devices, which may be configured for 3D NAND memory devices), comprise pillars extending through a stack of alternating conductive tiers and insulative tiers. The conductive tiers, which may include control gates for access lines (e.g., word lines), include conductive rails along an outer sidewall of the conductive tiers, distal from the pillars extending through the conductive tiers. The conductive rails protrude laterally beyond outer sidewalls of the insulative tiers. The conductive rails increase the amount of conductive material that may otherwise be in the conductive tiers, which may enable the conductive material to exhibit a lower electrical resistance, improving operational performance of the electronic devices.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: November 7, 2023
    Assignee: Micron Technology, Inc.
    Inventors: John D. Hopkins, Rita J. Klein, Jordan D. Greenlee
  • Patent number: 11804449
    Abstract: According to one embodiment, a semiconductor device includes a substrate; a semiconductor chip provided on the substrate; a resin covering the semiconductor chip; and a metal film provided on the resin. The metal film includes a first metal layer provided on the resin, a second metal layer provided on the first metal layer, and a third metal layer provided on the second metal layer. The first metal layer and the second metal layer contain a same material, and a particle diameter of the second metal layer is smaller than a particle diameter of the first metal layer.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: October 31, 2023
    Assignee: KIOXIA CORPORATION
    Inventor: Akihito Sawanobori
  • Patent number: 11798840
    Abstract: Some embodiments of the present disclosure relate to a semiconductor structure including a first conductive wire disposed over a substrate. A dielectric liner is arranged along sidewalls and an upper surface of the first conductive wire and is laterally surrounded by a first dielectric layer. The dielectric liner and the first dielectric layer are different materials. A conductive via is disposed within a second dielectric layer over the first conductive wire. The conductive via has a first lower surface disposed over the first dielectric layer and a second lower surface below the first lower surface and over the first conductive wire.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: October 24, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Hao Liao, Hsi-Wen Tien, Chih Wei Lu, Yu-Teng Dai, Hsin-Chieh Yao, Chung-Ju Lee
  • Patent number: 11798845
    Abstract: Method for forming tungsten gap fill on a structure, including high aspect ratio structures includes depositing a tungsten liner in the structure using a physical vapor deposition (PVD) process with high ionization and an ambient gas of argon or krypton. The PVD process is performed at a temperature of approximately 20 degrees Celsius to approximately 300 degrees Celsius. The method further includes treating the structure with a nitridation process and depositing bulk fill tungsten into the structure using a chemical vapor deposition (CVD) process to form a seam suppressed boron free tungsten fill. The CVD process is performed at a temperature of approximately 300 degrees Celsius to approximately 500 degrees Celsius and at a pressure of approximately 5 Torr to approximately 300 Torr.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: October 24, 2023
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Xi Cen, Kai Wu, Min Heon, Wei Min Chan, Tom Ho Wing Yu, Peiqi Wang, Ju Ik Kang, Feihu Wang, Nobuyuki Sasaki, Chunming Zhou
  • Patent number: 11791261
    Abstract: A semiconductor structure and a method for forming the same are provided. The method includes forming a dielectric layer on a substrate; forming a contact in the dielectric layer; recessing the dielectric layer so that the upper portion of the contact protrudes from the upper surface of the dielectric layer; and etching the upper portion of the contact to reduce the size of the upper portion of the contact. The semiconductor structure includes a substrate, a contact on the substrate and having an upper portion and a lower portion, a liner on the sidewall and bottom of the lower portion of the contact, and a dielectric layer surrounding the contact. The dielectric layer is in direct contact with the sidewall of the upper portion of the contact.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: October 17, 2023
    Assignee: WINBOND ELECTRONICS CORP.
    Inventor: Chia-Hsin Huang
  • Patent number: 11791327
    Abstract: A memory-containing die includes a three-dimensional memory array, a memory dielectric material layer located on a first side of the three-dimensional memory array, and memory-side bonding pads. A logic die includes a peripheral circuitry configured to control operation of the three-dimensional memory array, logic dielectric material layers located on a first side of the peripheral circuitry, and logic-side bonding pads included in the logic dielectric material layers. The logic-side bonding pads includes a pad-level mesh structure electrically connected to a source power supply circuit within the peripheral circuitry and containing an array of discrete openings therethrough, and discrete logic-side bonding pads. The logic-side bonding pads are bonded to a respective one, or a respective subset, of the memory-side bonding pads. The pad-level mesh structure can be used as a component of a source power distribution network.
    Type: Grant
    Filed: August 25, 2021
    Date of Patent: October 17, 2023
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Kwang-Ho Kim, Masaaki Higashitani, Fumiaki Toyama, Akio Nishida
  • Patent number: 11784132
    Abstract: An interposer-type component carrier includes a stack comprising at least one electrically conductive layer structure and at least one electrically insulating layer structure; a cavity formed in an upper portion of the stack; an active component embedded in the cavity and having at least one terminal facing upwards; and a redistribution structure having only one electrically insulating layer structure above the component. A method of manufacturing an interposer-type component carrier is also disclosed.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: October 10, 2023
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventors: Markus Leitgeb, Gerhard Freydl
  • Patent number: 11764070
    Abstract: An etching method includes: providing, in a chamber, a substrate including a structure including a first film selected from a molybdenum film and a tungsten film; performing a first etching on the first film by supplying an oxidation gas and a first gas selected from a MoF6 gas and a WF6 gas into the chamber; when a pore present inside the first film is exposed by the first etching, filling the pore with one of molybdenum and tungsten by stopping the first etching and supplying a reduction gas and a second gas selected the MoF6 gas and the WF6 gas into the chamber; and performing a second etching on a filling layer formed in the filling and the first film by supplying the oxidation gas and a third gas selected from the MoF6 gas and the WF6 gas into the chamber.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: September 19, 2023
    Assignee: Tokyo Electron Limited
    Inventors: Satoshi Toda, Naoki Shindo, Haruna Suzuki, Gen You
  • Patent number: 11698387
    Abstract: Provided is a physical quantity sensor including: a movable body; a base body; and a lid body, in which the movable body is accommodated in a space between the base body and the lid body, the space is sealed with a melt portion obtained by melting a through hole provided in the lid body, the lid body and the melt portion contain silicon, and the melt portion has a continuous curved surface having unevenness.
    Type: Grant
    Filed: September 14, 2021
    Date of Patent: July 11, 2023
    Inventor: Teruo Takizawa
  • Patent number: 11696510
    Abstract: The present disclosure describes an exemplary method that can prevent or reduce out-diffusion of Cu from interconnect layers to magnetic tunnel junction (MTJ) structures. The method includes forming an interconnect layer over a substrate that includes an interlayer dielectric stack with openings therein; disposing a metal in the openings to form corresponding conductive structures; and selectively depositing a diffusion barrier layer on the metal. In the method, selectively depositing the diffusion barrier layer includes pre-treating the surface of the metal; disposing a precursor to selectively form a partially-decomposed precursor layer on the metal; and exposing the partially-decomposed precursor layer to a plasma to form the diffusion barrier layer. The method further includes forming an MTJ structure on the interconnect layer over the diffusion barrier layer, where the bottom electrode of the MTJ structure is aligned to the diffusion barrier layer.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: July 4, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jung-Tang Wu, Jui-Hung Ho, Chin-Szu Lee, Meng-Yu Wu, Szu-Hua Wu
  • Patent number: 11694838
    Abstract: A coil electronic component includes an insulating substrate, a coil portion disposed on at least one surface of the insulating substrate, a body in which the insulating substrate and the coil portion are embedded, a lead-out portion connected to the coil portion and exposed from a surface of the body, and a connection portion including a plurality of connecting conductors each having a bent portion to increase lengths of the plurality of connecting conductors embedded in the body, the plurality of connecting conductors being spaced apart from each other, the connection portion connecting an end of the coil portion to the lead-out portion to each other.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: July 4, 2023
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Yong Min Kim, Jae Hun Kim, Ji Hyuk Lim, Jong Yun Kim
  • Patent number: 11677033
    Abstract: A semiconductor device includes: a semiconductor base body of a first conductivity-type; a first electrode electrically connected to the semiconductor base body; a first semiconductor region of a second conductivity-type provided at an upper part of the semiconductor base body; a second semiconductor region of the first conductivity-type provided at an upper part of the first semiconductor region; a second electrode electrically connected to the first semiconductor region; an insulating film provided on a top surface of the second semiconductor region; and a passive element provided on a top surface of the insulating film.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: June 13, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yoshiaki Toyoda
  • Patent number: 11674216
    Abstract: Methods and apparatus for performing physical vapor deposition in a reactor chamber to form aluminum material on a substrate including: depositing a first aluminum layer atop a substrate to form a first aluminum region having a first grain size and a first temperature; and cooling the first aluminum region atop a substrate to a second temperature at a rate sufficient to increase the first grain size to a second grain size.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: June 13, 2023
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Siew Kit Hoi, Yaoying Zhong, Xinxin Wang, Zheng Min Clarence Chong
  • Patent number: 11665977
    Abstract: In an embodiment, a device includes: a magnetoresistive random access memory (MRAM) array including MRAM cells arranged in rows and columns, where a first column of the columns includes: first bottom electrodes arranged along the first column; first magnetic tunnel junction (MTJ) stacks over the first bottom electrodes; a first shared electrode over each of the first MTJ stacks; second bottom electrodes arranged along the first column; second MTJ stacks over the second bottom electrodes; a second shared electrode over each of the second MTJ stacks; and a bit line electrically connected to the first shared electrode and the second shared electrode.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: May 30, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tai-Yen Peng, Yu-Feng Yin, An-Shen Chang, Han-Ting Tsai, Qiang Fu
  • Patent number: 11658121
    Abstract: A semiconductor device includes a semiconductor substrate; a first insulating film and a second insulating film provided above the semiconductor substrate; a low-k film provided between the first insulating film and the second insulating film; an element formation region in which elements included in an electric circuit are formed in the semiconductor substrate; a scribe region provided around the element formation region; a cut portion provided on the outer periphery of the scribe region; and a groove formed between the cut portion and the element formation region, wherein the groove penetrates through the low-k film.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: May 23, 2023
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Shigeru Sugioka, Hidenori Yamaguchi, Noriaki Fujiki, Keizo Kawakita
  • Patent number: 11637100
    Abstract: The present disclosure generally relates to a semiconductor device having a capacitor and a resistor and a method of forming the same. More particularly, the present disclosure relates to a metal-insulator-metal (MIM) capacitor and a thin film resistor (TFR) formed in a back end of line portion of an integrated circuit (IC) chip.
    Type: Grant
    Filed: August 11, 2021
    Date of Patent: April 25, 2023
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Qiying Wong, Handoko Linewih, Yudi Setiawan, Chengang Feng, Siow Lee Chwa
  • Patent number: 11637981
    Abstract: A photoelectric conversion apparatus having a first substrate and a second substrate overlaid on each other and including electrically conductive portions is provided. The first substrate includes a photoelectric conversion element, a first portion configured to form part of a first surface, a second portion which is included in an electrically conductive pattern closest to the first portion, and a third portion which is included in an electrically conductive pattern second closest to the first portion. The second substrate includes a fourth portion configured to form part of a second surface, and a circuit. In a planar view with respect to the first surface, an area of the first portion is smaller than an area of the second portion and larger than an area of a portion of the third portion overlaying the second portion.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: April 25, 2023
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takanori Yamashita, Kazuhiro Saito, Tatsuya Ryoki, Yoshikazu Yamazaki
  • Patent number: 11626221
    Abstract: A resistance element includes a plurality of resistance chips stacked vertically, each of the plurality of resistance chips including a semiconductor substrate, one or more resistance layers on a field insulating film, a pad forming electrode on electrically connected to the one or more resistance layers, a relay wiring on the interlayer insulating film, laterally separated from the pad forming electrode, electrically connected to another end of at least one of the one or more resistance layers on one end and to a semiconductor substrate on another end, and a back surface electrode at a bottom of the semiconductor substrate, making ohmic contact with the semiconductor substrate, wherein the plurality of resistance chips have the same planar outer shape, and are stacked one over another so as to constitute a resistor as a whole.
    Type: Grant
    Filed: May 2, 2022
    Date of Patent: April 11, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Taichi Karino
  • Patent number: 11616046
    Abstract: A multi-chip package comprising an interconnection substrate; a first semiconductor IC chip over the interconnection substrate, wherein the first semiconductor IC chip comprises a first silicon substrate, a plurality of first metal vias passing through the first silicon substrate, a plurality of first transistors on a top surface of the first silicon substrate and a first interconnection scheme over the first silicon substrate, wherein the first interconnection scheme comprises a first interconnection metal layer over the first silicon substrate, a second interconnection metal layer over the first interconnection layer and the first silicon substrate and a first insulating dielectric layer over the first silicon substrate and between the first and second interconnection metal layers; a second semiconductor IC chip over and bonded to the first semiconductor IC chip; and a plurality of second metal vias over and coupling to the interconnection substrate, wherein the plurality of second metal vias are in a space
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: March 28, 2023
    Assignee: iCometrue Company Ltd.
    Inventors: Mou-Shiung Lin, Jin-Yuan Lee
  • Patent number: 11594423
    Abstract: The present disclosure provides a method of forming a capacitor array and a semiconductor structure. The method of forming a capacitor array includes: providing a substrate, the substrate including an array region and a non-array region, wherein a base layer and a dielectric layer are formed in the substrate, and a first barrier layer is formed between the base layer and the dielectric layer; forming, on a surface of the dielectric layer, a first array definition layer and a second array definition layer respectively corresponding to the array region and the non-array region; forming a pattern transfer layer on a surface of each of the first array definition layer and the second array definition layer; patterning the dielectric layer and the second array definition layer by using the pattern transfer layer as a mask, and forming a capacitor array located in the array region.
    Type: Grant
    Filed: January 17, 2022
    Date of Patent: February 28, 2023
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Qiang Wan
  • Patent number: 11569250
    Abstract: A memory device includes metal interconnect structures embedded within dielectric material layers that overlie a top surface of a substrate, a thin film transistor embedded in a first dielectric material layer selected from the dielectric material layers, and is vertically spaced from the top surface of the substrate, and a ferroelectric memory cell embedded within the dielectric material layers. A first node of the ferroelectric memory cell is electrically connected to a node of the thin film transistor through a subset of the metal interconnect structures that is located above, and vertically spaced from, the top surface of the substrate.
    Type: Grant
    Filed: April 14, 2021
    Date of Patent: January 31, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Bo-Feng Young, Mauricio Manfrini, Sai-Hooi Yeong, Han-Jong Chia, Yu-Ming Lin
  • Patent number: 11569126
    Abstract: A dielectric layer and a method of forming thereof. An opening defined in a dielectric layer and a wire deposited within the opening, wherein the wire includes a core material surrounded by a jacket material, wherein the jacket material exhibits a first resistivity ?1 and the core material exhibits a second resistivity ?2 and ?2 is less than ?1.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: January 31, 2023
    Assignee: Intel Corporation
    Inventors: Hui Jae Yoo, Tejaswi K. Indukuri, Ramanan V. Chebiam, James S. Clarke
  • Patent number: 11563116
    Abstract: A vertical type transistor includes: a substrate; a first source/drain electrode layer provided on the substrate; a second source/drain electrode layer provided above the first source/drain electrode layer; a first gate electrode layer provided between the first and second source/drain electrode layers; a first gate insulating film passing through the first gate electrode layer; a hole passing through the second source/drain electrode layer, the first gate insulating film, and the first source/drain electrode layer; and a first channel layer provided on a lateral side of the hole, wherein the first channel layer may include a 2D semiconductor.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: January 24, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Minhyun Lee, Minsu Seol, Yeonchoo Cho, Hyeonjin Shin
  • Patent number: 11557482
    Abstract: An electrode structure with an alloy interface is provided. In one aspect, a method of forming a contact structure includes: patterning a via in a first dielectric layer; depositing a barrier layer onto the first dielectric layer, lining the via; depositing and polishing a first metal layer (Element A) into the via to form a contact in the via; depositing a second metal layer (Element B) onto the contact in the via; annealing the first and second metal layers under conditions sufficient to form an alloy AB; depositing a third metal layer onto the second metal layer; patterning the second and third metal layers into a pedestal stack over the contact to form an electrode over the contact, wherein the alloy AB is present at an interface of the electrode and the contact; and depositing a second dielectric that surrounds the pedestal stack. A contact structure is also provided.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: January 17, 2023
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Daniel Charles Edelstein, Chao-Kun Hu, Oscar van der Straten
  • Patent number: 11538777
    Abstract: A method of forming a semiconductor structure includes providing a semiconductor wafer including a plurality of semiconductor dies, providing a polymerized material layer, attaching the polymerized material layer to the semiconductor wafer such that the polymerized material layer is polymerized prior to the step of attaching the polymerized material layer to the semiconductor wafer, applying and patterning an etch mask layer over the polymerized material layer, such that openings are formed through the etch mask layer, etching portions of the polymerized material layer that are proximal to the openings through the etch mask layer by applying an etchant into the openings through the etch mask layer in an etch process, and removing the etch mask layer selective to the polymerized material layer. Alternatively, a patterned polymerized material layer may be transferred from a transfer substrate to the semiconductor wafer.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: December 27, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Hajime Arai
  • Patent number: 11532556
    Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a substrate having a front side and a back side; a gate stack formed on the front side of the substrate and disposed on an active region of the substrate; a first source/drain feature formed on the active region and disposed at an edge of the gate stack; a backside power rail formed on the back side of the substrate; and a backside contact feature interposed between the backside power rail and the first source/drain feature, and electrically connecting the backside power rail to the first source/drain feature. The backside contact feature further includes a first silicide layer on the back side of the substrate.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: December 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Xuan Huang, Ching-Wei Tsai, Cheng-Ting Chung, Cheng-Chi Chuang, Shang-Wen Chang
  • Patent number: 11515351
    Abstract: There is provided a semiconductor device in which the inter-wiring capacitance of wiring lines provided in any layout is further reduced. A semiconductor device (1) including: a first inter-wiring insulating layer (120) that is provided on a substrate (100) and includes a recess on a side opposite to the substrate; a first wiring layer (130) that is provided inside the recess in the first inter-wiring insulating layer; a sealing film (140) that is provided along an uneven shape of the first wiring layer and the first inter-wiring insulating layer; a second inter-wiring insulating layer (220) that is provided on the first inter-wiring insulating layer to cover the recess; and a gap (150) that is provided between the second inter-wiring insulating layer and the first wiring layer and the first inter-wiring insulating layer. The second inter-wiring insulating layer has a planarized surface that is opposed to the recess.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: November 29, 2022
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Masaki Haneda
  • Patent number: 11465904
    Abstract: A method of making carbon nanotubes is provided, the method includes depositing a catalyst layer on a substrate, placing the substrate having the catalyst layer in a reaction furnace, heating the reaction furnace to a predetermined temperature, introducing a carbon source gas and a protective gas into the reaction furnace to grow a first carbon nanotube segment structure comprising a plurality of metallic carbon nanotube segments, and applying a pulsed electric field to grow a second carbon nanotube segment structure from the plurality of metallic carbon nanotube segments, where the pulsed electric field is a periodic electric field including a plurality of positive electric field pulses and a plurality of negative electric field pulses alternately arranged, and the second carbon nanotube segment structure includes a plurality of semiconducting carbon nanotube segments.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: October 11, 2022
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Jiang-Tao Wang, Peng Liu, Kai-Li Jiang, Shou-Shan Fan
  • Patent number: 11417536
    Abstract: A method for wafer planarization includes forming a second insulating layer and a polishing layer on a substrate having a chip region and a scribe lane region; forming a first through-hole in the polishing layer in the chip region and the scribe lane region and a second through-hole in the second insulating layer in the chip region, wherein the second through-hole and the first through-hole meet in the chip region; forming a pad metal layer inside the first through-hole and the second through-hole and on an upper surface of the polishing layer; and polishing the polishing layer and the pad metal layer by a chemical mechanical polishing (CMP) process to expose an upper surface of the second insulating layer in the chip region and the scribe lane region.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: August 16, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Joo Hee Jang, Seok Ho Kim, Hoon Joo Na, Kwang Jin Moon, Jae Hyung Park, Kyu Ha Lee
  • Patent number: 11404368
    Abstract: An integrated circuit structure includes a dielectric layer and an etch stop layer. The etch stop layer includes a first sub layer including a metal nitride over the first dielectric layer, and a second sub layer overlying or underlying the first sub layer. The second sub layer includes a metal compound comprising an element selected from carbon and oxygen, and is in contact with the first sub layer.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: August 2, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD
    Inventors: Shiu-Ko JangJian, Tsung-Hsuan Hong, Chun Che Lin, Chih-Nan Wu
  • Patent number: 11348867
    Abstract: Embodiments of the disclosure provide a capacitor for an integrated circuit (IC). The capacitor may include a first vertical electrode on an upper surface of a first conductor within a first wiring layer. A capacitor dielectric may be on an upper surface of the first vertical electrode. A second vertical electrode may be on an upper surface of the capacitor dielectric. The second vertical electrode is vertically between the capacitor dielectric and a second conductor. An inter-level dielectric (ILD) layer is adjacent to each of the first vertical electrode, the capacitor dielectric, and the second vertical electrode. The ILD layer is vertically between the first conductor and the second conductor.
    Type: Grant
    Filed: November 5, 2020
    Date of Patent: May 31, 2022
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Dewei Xu, Sunil K. Singh, Seung-Yeop Kook, Roderick A. Augur
  • Patent number: 11268983
    Abstract: An apparatus an apparatus comprising: a substrate having a plane; and an array of at least one conductive probe having a base affixed to the substrate, the at least one conductive probe having a major axis extending from the plane of the substrate and terminating at a tip, wherein the one or more conductive probes comprise at least three points that are non-collinear.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: March 8, 2022
    Assignee: Intel Corporation
    Inventor: Pooya Tadayon
  • Patent number: 11133462
    Abstract: A void-less bottom electrode structure is formed at least partially in a via opening having a small feature size and containing a conductive landing pad structure which is composed of a metal-containing seed layer that is subjected to a reflow anneal. A metal-containing structure is located on a topmost surface of the bottom electrode structure. The metal-containing structure may be composed of an electrically conductive metal-containing material or a material stack of electrically conductive metal-containing materials. In some embodiments, the bottom electrode and the metal-containing structure collectively provide a non-volatile memory device.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: September 28, 2021
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Baozhen Li, Andrew Tae Kim
  • Patent number: 10954129
    Abstract: A method of fabricating a semiconductor structure is described. The method comprises forming at least one mandrel on a substrate, the at least one mandrel comprising a diamond-like carbon and having a top and two opposing sidewalls, the diamond-like carbon comprising at least 40% sp3 hybridized carbon atoms. The mandrel may be used in Self-Aligned Multiple Patterning (SAMP) processes.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: March 23, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Takehito Koshizawa, Eswaranand Venkatasubramanian, Pramit Manna, Chi Lu, Chi-I Lang, Nancy Fung, Abhijit Basu Mallick
  • Patent number: 10937598
    Abstract: A flexible electrode is provided in which an increase in resistance change rate caused by repeated stretch is reduced. A sensor element is also provided, which uses the flexible electrode. A strain sensor, a pressure sensor, and a temperature sensor are also provided, each using the sensor element. The flexible electrode can include an insulating flexible substrate and an electrode film laminated on the flexible substrate. The electrode film can include a fibrous carbon nanohorn aggregate.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: March 2, 2021
    Assignee: NEC CORPORATION
    Inventor: Ryota Yuge
  • Patent number: 10885978
    Abstract: A non-volatile nanotube switch and memory arrays constructed from these switches are disclosed. A non-volatile nanotube switch includes a conductive terminal and a nanoscopic element stack having a plurality of nanoscopic elements arranged in direct electrical contact, a first comprising a nanotube fabric and a second comprising a carbon material, a portion of the nanoscopic element stack in electrical contact with the conductive terminal. Control circuitry is provided in electrical communication with and for applying electrical stimulus to the conductive terminal and to at least a portion of the nanoscopic element stack. At least one of the nanoscopic elements is capable of switching among a plurality of electronic states in response to a corresponding electrical stimuli applied by the control circuitry to the conductive terminal and the portion of the nanoscopic element stack. For each electronic state, the nanoscopic element stack provides an electrical pathway of corresponding resistance.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: January 5, 2021
    Assignee: Nantero, Inc.
    Inventors: Claude L. Bertin, Eliodor G. Ghenciu, Thomas Rueckes, H. Montgomery Manning
  • Patent number: 10861813
    Abstract: A semiconductor chip stack includes a first semiconductor chip, a second semiconductor chip, and a connection via which the first electrode and the second electrode are electrically connected to each other. The connection includes a first column and a second column. The first column is constituted by a material having a higher degree of activity with respect to heat than a material that constitutes the second column and is smaller in volume than the second column. Further, the connection has an aspect ratio of 0.5 or higher in a height direction.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: December 8, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Toshiya Ishio
  • Patent number: 10811312
    Abstract: A method of fabricating an integrated circuit (IC) chip is disclosed. The method starts with opening a window on a first surface of the IC chip through a passivation overcoat to expose the copper metallization layer. The window has sidewalls and a bottom that is adjacent the copper metallization layer. The method continues with depositing a barrier conductive stack on the passivation overcoat and exposed portions of the copper metallization layer, then depositing a sacrificial conductive stack on the barrier conductive stack. The sacrificial conductive stack has a thickness between 50 ? and 500 ?. The first surface of the semiconductor chip is polished to remove the sacrificial conductive stack and the barrier conductive stack from the surface of the passivation overcoat.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: October 20, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Manoj K. Jain
  • Patent number: 10615048
    Abstract: A semiconductor structure and a method for fabricating the semiconductor structure are provided. The method includes providing a substrate including a device region, and forming a functional layer on the substrate. The method also includes forming a plurality of discrete initial core layers on the functional layer. Adjacent initial core layers are spaced apart by a first gap. In addition, the method includes forming a sidewall spacer on a sidewall surface of an initial core layer, and forming a first opening in the functional layer by removing the functional layer at a bottom of the first gap. Moreover, the method includes forming a core layer and a second gap between sidewall spacers by performing a patterning process to remove a portion of the initial core layer. Further, the method includes forming a second opening by removing the functional layer exposed at a bottom of the second gap.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: April 7, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Duohui Bei
  • Patent number: 10510590
    Abstract: Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication. In some implementations, the methods involve providing a tungsten (W)-containing layer on a substrate; and depositing a molybdenum (Mo)-containing layer on the W-containing layer. In some implementations, the methods involve depositing a Mo-containing layer directly on a dielectric or titanium nitride (TiN) substrate without an intervening W-containing layer.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: December 17, 2019
    Assignee: Lam Research Corporation
    Inventors: Shruti Vivek Thombare, Raashina Humayun, Michal Danek, Chiukin Steven Lai, Joshua Collins, Hanna Bamnolker, Griffin John Kennedy, Gorun Butail, Patrick A. van Cleemput
  • Patent number: 10490448
    Abstract: A method of fabricating an integrated circuit (IC) chip is disclosed. The method starts with opening a window on a first surface of the IC chip through a passivation overcoat to expose the copper metallization layer. The window has sidewalls and a bottom that is adjacent the copper metallization layer. The method continues with depositing a barrier conductive stack on the passivation overcoat and exposed portions of the copper metallization layer, then depositing a sacrificial conductive stack on the barrier conductive stack. The sacrificial conductive stack has a thickness between 50 ? and 500 ?. The first surface of the semiconductor chip is polished to remove the sacrificial conductive stack and the barrier conductive stack from the surface of the passivation overcoat.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: November 26, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Manoj K. Jain
  • Patent number: 10410986
    Abstract: A semiconductor device and its manufacturing method are presented. The manufacturing method includes: providing a semiconductor structure comprising: an interlayer dielectric layer, a first metal layer surrounded by the interlayer dielectric layer, and a semiconductor layer on the interlayer dielectric layer; etching the semiconductor layer to form an opening exposing the interlayer dielectric layer, wherein the opening comprises a first opening and a second opening on the first opening; forming an insulation layer on the semiconductor structure; etching the insulation layer and the interlayer dielectric layer at the bottom of the first opening to form a groove exposing a portion of the first metal layer; forming a second metal layer on the insulation layer and on the bottom and a side surface of the groove; and patterning the second metal layer. The second metal layer in this inventive concept can be removed more completely than conventional methods.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: September 10, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: You Wu, Jun Zhu