Abstract: Methods of forming a metal oxide surface that is enriched with metal oxide in its higher oxidation state are provided. A metal oxide surface that is enriched with metal oxide in its higher oxidation state is also provided.

Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Abstract: A fabricating method for a flat panel display device having a thin film pattern over a substrate is disclosed. The fabricating method includes depositing a hydrophilic resin over a substrate and patterning the hydrophilic resin to form hydrophilic resin patterns over areas outside where thin film patterns are to be formed over the substrate. The fabricating method also includes depositing a hydrophobic nano powder thin film material over the substrate and between the hydrophilic resin patterns and removing the hydrophilic resin patterns to form hydrophobic nano powder thin film patterns over the substrate. Moreover, the fabricating method includes treating the hydrophobic nano powder thin film patterns to form the thin film pattern.

Abstract: A nano-electrode or nano-wire may be etched centrally to form a gap between nano-electrode portions. The portions may ultimately constitute a single electron transistor. The source and drain formed from the electrode portions are self-aligned with one another. Using spacer technology, the gap between the electrodes may be made very small.

Abstract: Methods are described for eliminating void formation during the fabrication of and/or operation of memory cells/devices. According to one aspect of the present disclosure, the methods to eliminate voids include formation of an opening on a semiconductor structure, formation of a diffusion barrier layer, deposition of a metal into the opening, preamorphization of the metal using preamorphization implants, and formation of a conductivity facilitating layer. According to another aspect of the present disclosure, the methods to eliminate voids include formation of an opening on a semiconductor structure, formation of a diffusion barrier layer, deposition of a metal into the opening, preamorphization of the metal using a contact with a plasma, and formation of a conductivity facilitating layer.

Abstract: A method is provided for depositing a patterning material onto an optically transparent substrate by the use of a laser beam. A solid layer of a patterning material is placed adjacent to a receiving surface of the substrate. A laser beam is directed at an incident angle between 0 and 90° relative to the receiving surface. The laser beam is transmitted through the substrate and onto the solid layer to cause patterning material from the solid layer to deposit onto the receiving surface of the substrate.

Abstract: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

Abstract: A copper film is annealed at high pressure to enhance grain growth and remove voids. Other films, such as dielectrics, may also be suitable. High pressure can be used in conjunction with temperatures lower than room temperature for annealing or higher temperatures may be used to further enhance grain growth.

Abstract: The invention includes a method of forming a metal-containing film over a surface of a semiconductor substrate. The surface is exposed to a supercritical fluid. The supercritical fluid has H2, at least one H2-activating catalyst, and at least one metal-containing precursor dispersed therein. A metal-containing film is formed across the surface of the semiconductor substrate from metal of the at least one metal-containing precursor. The invention also includes semiconductor constructions having metal-containing layers which include one or more of copper, cobalt, gold and nickel in combination with one or more of palladium, platinum, iridium, rhodium and ruthenium.

Abstract: A system for personalizing one or more electrical circuits having plurality of layers with electrical characteristics. The layers being produced by an electrical characteristic determination process (ECDP). The system for personalizing includes a wafer stage for receiving a wafer in order to produce a plurality of electrical circuits. The system is configured to apply a personalization process during production of the layers. The personalization process includes using a first ECDP in the layer to produce identical electrical characteristics on the wafer in each of the plurality of electrical circuits, and using a second ECDP in the layer to modify one or more electrical characteristics in selected electrical circuits so as to incorporate in the selected circuits an individualized digital number, giving rise to the desired personalizing of one or more of the specified electrical circuits. Related apparatus and methods are also provided.

Abstract: A method of treating a conductive layer to assure enhanced adhesion of the layer to selected dielectric layers used to form a circuitized substrate. The conductive layer includes at least one surface with the appropriate roughness to enable such adhesion and also good signal passage if the layer is used as a signal layer. The method is extendible to the formation of such substrates, including to the formation of multilayered substrates having many conductive and dielectric layers. Such substrates may include one or more electrical components (e.g., semiconductor chips) mounted thereon and may also be mounted themselves onto other substrates.

Abstract: When an oxidation treatment for regenerating a gate insulating film 6 is performed after forming gate electrodes 7A of a polymetal structure in which a WNx film and a W film are stacked on a polysilicon film, a wafer 1 is heated and cooled under conditions for reducing a W oxide 27 on the sidewall of each gate electrode 7A. As a result, the amount of the W oxide 27 to be deposited on the surface of the wafer 1 is reduced.

Abstract: Electro-mechanical switches and memory cells using vertically-disposed nanofabric articles and methods of making the same are described. An electro-mechanical device, includes a structure having a major horizontal surface and a channel formed therein. A conductive trace is in the channel; and a nanotube article vertically suspended in the channel, in spaced relation to a vertical wall of the channel. The article is electro-mechanically deflectable in a horizontal direction toward the conductive trace. Under certain embodiments, the vertically suspended extent of the nanotube article is defined by a thin film process. Under certain embodiments, the vertically suspended extent of the nanotube article is about 50 nanometers or less. Under certain embodiments, the nanotube article is clamped with a conducting material disposed in porous spaces between some nanotubes of the nanotube article. Under certain embodiments, the nanotube article is formed from a porous nanofabric.

Abstract: In a metal film production apparatus, a copper plate member is etched with a Cl2 gas plasma within a chamber to form a precursor comprising a Cu component and a Cl2 gas; and the temperatures of the copper plate member and a substrate and a difference between their temperatures are controlled as predetermined, to deposit the Cu component of the precursor on the substrate, thereby forming a film of Cu. In this apparatus, Cl* is formed in an excitation chamber of a passage communicating with the interior of the chamber to flow a Cl2 gas, and the Cl* is supplied into the chamber to withdraw a Cl2 gas from the precursor adsorbed onto the substrate, thereby promoting a Cu film formation reaction. The apparatus has a high film formation speed, can use an inexpensive starting material, and can minimize impurities remaining in the film.

Abstract: The present invention is directed to a method of fabricating a local interconnect. A disclosed method involves forming two separate cavities in the ILD above two electrical contacts of a transistor. A first cavity extend down to an underlying etch stop layer. The first cavity is then filled with a protective layer. The second cavity is then formed adjacent to the first cavity and extends down to expose the underlying etch stop layer. The protective layer is removed to form an expanded cavity including the first and second cavities which expose the underlying etch stop layer in the expanded cavity. The etch stop material in the expanded cavity is also removed to expose an underlying gate contact and expose one of a source or drain contact. The gate contact is then electrically connected with one of the exposed source or drain contacts to form a local interconnect.

Abstract: A structure interfaces dual polycrystalline silicon layers. The structure includes a first layer of polycrystalline silicon and a metal interface layer formed on a surface of the first layer of polycrystalline silicon. The structure further includes a second layer of polycrystalline silicon formed on a surface of the interface layer.

Abstract: Structures and methods are provided which include a selective electroless copper metallization. The present invention includes a novel methodology for forming copper vias on a substrate. This method includes depositing a thin film seed layer of Palladium (Pd) or Copper (Cu) on a substrate. The seed layer is deposited to a thickness of less than 15 nanometers (nm). A photolithography technique is used to define a number of via holes above the seed layer. In one embodiment, using a photolithography technique includes forming a patterned photoresist layer to define the number of via holes above the seed layer. A layer of copper is deposited over the seed layer using electroless plating filling the number of via holes to a top surface of the patterned photoresist layer.

Abstract: A method of depositing a metal film on a substrate includes a supercritical preclean step, a supercritical desorb step, and a metal deposition step. Preferably, the preclean step comprises maintaining supercritical carbon dioxide and a chelating agent in contact with the substrate in order to remove an oxide layer from a metal surface of the substrate. More preferably, the preclean step comprises maintaining the supercritical carbon dioxide, the chelating agent, and an acid in contact with the substrate. Alternatively, the preclean step comprises maintaining the supercritical carbon dioxide and an amine in contact with the oxide layer. The desorb step comprises maintaining supercritical carbon dioxide in contact with the substrate in order to remove adsorbed material from the substrate.

Abstract: Methods of forming a metal oxide surface that is enriched with metal oxide in its higher oxidation state for use in a semiconductor device are provided. A metal oxide surface that is enriched with metal oxide in its higher oxidation state for use in a semiconductor device is also provided.

Abstract: The present invention discloses a multi-passivation layer structure for organic thin-film transistors and a method for fabricating the same by spin coating, inject printing, screen printing and micro-contact on organic thin-film transistors. The multi-passivation layer structure for organic thin-film transistors, comprising: a substrate; a gate layer formed on the substrate; an insulator layer formed on the substrate and the gate layer; an electrode layer formed on the insulator layer; a semiconductor layer formed on the insulator layer and the electrode layer; and a passivation layer formed on the semiconductor layer and the electrode layer, thereby forming a multi-passivation layer structure for organic thin-film transistors.

Abstract: A method of patterning organic semiconductor layers of electronic devices utilizing reverse printing.

Abstract: For forming a fine structure of a desired material, nanoparticles of the same material are prepared in a suspension. A layer of the suspension is applied by a drop-on-demand printing system to a substrate. At least part of the layer is exposed to laser light for melting the nanoparticles at least partially. Upon solidification, the molten particles are sintered together to form the desired structure. Due to the low melting point of nanoparticles as compared to the melting point of bulk material, this procedure avoids damage to the substrate and provides a better control over the structure generation process. It can be used for generating metallic and non-metallic structures on various substrates. The laser light may have non-Gaussian intensity distribution or can combine multiple beams of Gaussian and non-Gaussian distribution for improving the quality of the generated structure, or it may be pulsed for improved control of the heat flow into the substrate.

Abstract: A method for forming thoroughly deposited shallow trench isolation. A first oxide layer is formed conformally over the surface of a semiconductor substrate and on a trench thereon with an aspect ratio greater than 3. A liquid etching shield is filled in the trench by spin-spraying to cover the oxide layer in the trench. An etchant is then sprayed over the surface of the semiconductor substrate to remove the uncovered oxide layer and expose the surface of the semiconductor substrate. The density of the etchant is less than that of the liquid etching shield. A second oxide layer is deposited in the trench to form isolation without voids or seams.

Abstract: The copper interconnect formed by the use of a damascene technique is improved in dielectric breakdown strength (reliability). During post-CMP cleaning, alkali cleaning, a deoxidizing process due to hydrogen annealing or the like, and acid cleaning are carried out in this order. After the post-CMP cleaning and before forming an insulation film for a cap film, hydrogen plasma and ammonia plasma processes are carried out on the semiconductor substrate. In this way, a copper-based buried interconnect is formed in an interlayer insulation film structured of an insulation material having a low dielectric constant.