Abstract: A method (200) is described for an electronic assembly (30). An electronic die (24) with a sacrificial layer (28) on its back (27) and electrical contacts (26) on its front (25) is temporarily attached by its front (25) to a substrate (32). The back (27) is over-molded by a first material (34) extending over the substrate (32). The substrate (32) is removed leaving the die contacts (26) and the first material (33, 34) exposed. Interconnect layer(s) (44, 64) are provided over the first material (33, 34) and the die (24), electrically coupled to the contacts (26). Further components (66) can be coupled to the upper-most interconnects (64, 53). A second material (68) is over-molded over the components (66) and upper-most interconnects (64, 53). Thinning the first material (34) exposes the sacrificial layer (28) for removal.

Abstract: A method of etching a dielectric layer by a conductive mask includes providing the dielectric layer on a substrate, forming a pattern conductive mask on the dielectric layer, the pattern conductive mask contacting with the substrate, processing a dry etching on the dielectric layer by the pattern conductive mask. Because the conductive mask disperses a lot of electric charges, the electric charges are not able to be stored on the dry etched dielectric layer, and the multilevel interconnects and the elements under the dielectric layer will not burst.

Abstract: Embodiments of an apparatus and methods for correcting systematic non-uniformities using a gas cluster ion beam are generally described herein. Other embodiments may be described and claimed.

Abstract: In a semiconductor device, capacitance between copper interconnections is decreased and the insulation breakdown is improved simultaneously, and a countermeasure is taken for misalignment via by a manufacturing method including the steps of forming an interconnection containing copper as a main ingredient in an insulative film above a substrate, forming insulative films and a barrier insulative film for a reservoir pattern, forming an insulative film capable of suppressing or preventing copper from diffusing on the upper surface and on the lateral surface of the interconnection and above the insulative film and the insulative film, forming insulative films of low dielectric constant, in which the insulative film is formed such that the deposition rate above the opposing lateral surfaces of the interconnections is larger than the deposition rate therebelow to form an air gap between the adjacent interconnections and, finally, planarizing the insulative film by interlayer CMP.

Abstract: When dummy patterns are arranged to planarize LSI layout patterns, a plurality of dummy patterns 1 are arranged in a wiring layer in which signal wiring patterns 2 are formed, so as to be inclined at an angle of generally 45 degrees toward the associated signal wiring patterns 2. These dummy patterns 1 cross signal wiring patterns 3 formed in another vertically adjacent wiring layer to have an inclination angle of generally 45 degrees. A plurality of dummy patterns 13 are located in the wiring layer in which the signal wiring patterns 3 are formed, so as to be inclined at an angle of generally 45 degrees toward the associated signal wiring patterns 3. The dummy patterns 1 formed in one of the adjacent wiring layers cross the dummy patterns 13 formed in the other wiring layer at an angle of generally 90 degrees. This reduces fluctuations in wiring capacitance and equalizes fluctuations in the wiring capacitance to the maximum extent.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes the steps of forming an interlayer insulating layer on a semiconductor substrate, selectively patterning the interlayer insulating layer to form a contact hole, depositing a first metal on an inner surface of the contact hole, submerging the semiconductor substrate on which the first metal is deposited into an electrochemical plating (ECP) solution bath in which a second metal is dissolved, dissolving the first metal in the ECP solution bath, plating the first and second metals dissolved in the ECP solution bath at the same time to gap-fill an alloy of the first and second metals in the contact hole, and removing the alloy using the interlayer insulating layer as an end point in a CMP process to form an alloy interconnection.

Abstract: A method of manufacturing nonvolatile semiconductor memory devices comprises forming a first wiring material; and stacking memory cell materials on the first wiring material, which configure memory cells each including a variable resistor operative to nonvolatilely store information in accordance with variation in resistance. The method also comprises forming a plurality of first parallel trenches in the first wiring material and the stacked memory cell materials, the first trenches extending in a first direction, thereby forming first lines extending in the first direction and memory cell materials self-aligned with the first lines and separated by the first trenches. The method further comprises burying an interlayer insulator in the first trenches to form a block body and stacking a second wiring material on the block body.

Abstract: An integrated process for forming metallization layers for electronic devices that use damascene structures that include low-k dielectric and metal. According to one embodiment of the present invention, the integrated process includes planarizing a gapfill metal in low-k dielectric structures, generating a protective layer on the low-k dielectric followed by cleaning the surface of the gapfill metal. Another embodiment of the present invention includes a method of protecting low-k dielectrics such as carbon doped silicon oxide.

Abstract: A method of processing a substrate which enables a surface damaged layer and polishing remnants on the surface of an insulating film to be removed, and enable the amount removed of the surface damaged layer and polishing remnants to be controlled easily. An insulating film on a substrate, which has been revealed by chemical mechanical polishing, is exposed to an atmosphere of a mixed gas containing ammonia and hydrogen fluoride under a predetermined pressure. The insulating film which has been exposed to the atmosphere of the mixed gas is heated to a predetermined temperature.

Abstract: Disclosed is a method for fabricating a plurality of storage node contacts in a semiconductor device capable of minimizing an influence of a slurry residue and planarizing cruspidal patterns caused during a storage node contact isolation process. In accordance with the present invention, a chemical mechanical polishing (CMP) process that is the last process of the storage node contact isolation process is performed by using the slurry without the selectivity or the reverse selectivity, thereby removing the plurality of cruspidal patterns at every interface of the plurality of bit line patterns BL and the plurality of storage node contacts.

Abstract: Disclosed is a method for manufacturing a semiconductor device comprising forming a hydrophobic interlayer insulating film having a relative dielectric constant of 3.5 or less above a semiconductor substrate, forming a recess in the interlayer insulating film, depositing a conductive material above the interlayer insulating film having the recess to form a conductive layer, selectively removing the conductive material deposited above the interlayer insulating film by polishing to expose a surface of the interlayer insulating film while leaving the conductive material in the recess, and subjecting the surface of the interlayer insulating film having the recess filled with the conductive material to pressure washing using a resin member and an alkaline washing liquid containing an inorganic alkali and exhibiting a pH of more than 9.

Abstract: A method of manufacturing a semiconductor is provided. A fist metal layer can be formed on a lower structural layer, and an interlayer metal dielectric (IMD) layer can be formed on the first metal layer. A sacrificial oxide layer can be formed on the IMD layer, and a planarization process can be performed on the sacrificial oxide layer and the IMD layer to substantially eliminate a height difference of the IMD layer.

Abstract: A method for fabricating semiconductor device capable of minimizing hillocks and voids. The method includes subjecting an interlayer dielectric having a multi-protective dielectric structure including a first barrier metal layer and a first copper line to a plurality of NH3 treatment processes, forming a capping film on the first copper line, and planarizing the capping film via chemical mechanical polishing (CMP).

Abstract: A method for cleaning a dielectric and metal structure within a microelectronic structure uses an oxygen containing plasma treatment, followed by an alcohol treatment, in turn followed by an aqueous organic acid treatment. Another method for cleaning a dielectric and metal structure within a microelectronic structure uses an aqueous surfactant treatment followed by an alcohol treatment and finally followed by an aqueous organic acid treatment. The former method may be used to clean a plasma etch residue from a dual damascene aperture. The second method may be used to clean a chemical mechanical polish planarizing residue from a dual damascene structure. The two methods may be used sequentially, absent any intervening or subsequent sputtering method, to provide a dual damascene structure within a microelectronic structure.

Abstract: In a method for fabricating a semiconductor device, first, a first metal interconnect is formed in an interconnect formation region, and a second metal interconnect is formed in a seal ring region. Subsequently, by chemical mechanical polishing or etching, the upper portions of the first metal interconnect and the second metal interconnect are recessed to form recesses. A second insulating film filling the recesses is then formed above a substrate, and the upper portion of the second insulating film is planarized. Next, a hole and a trench are formed to extend halfway through the second insulating film, and ashing and polymer removal are performed. Subsequently to this, the hole and the trench are allowed to reach the first metal interconnect and the second metal interconnect.

Abstract: A method for planarizing a surface in an integrated circuit manufacturing process provides a first film of a first material over a non-uniform surface, such as a surface including isolation trenches. The first material includes, for example, a polysilicon layer to be used to form floating gates in a non-volatile memory integrated circuit. A second film, which is a sacrificial film formed using a second material, such as silicon oxide, is then provided over the first film. Partial removal of the second film is carried out using chemical mechanical polishing until a portion of the first film is exposed using a first slurry that is selective to the first material. Thereafter, the remaining layer of the second film is removed, along with planarization of the surface, using a second slurry that is highly selective, i.e., has a selectivity of the first film to the second film that is greater than a predetermine value (e.g., 16:1).

Abstract: This invention includes a chemical mechanical polishing method including providing a substrate having an organic material to be polished by chemical mechanical polishing. In one implementation, the organic material is chemical mechanically polished using a polishing pad downforce on the substrate of less than or equal to 1.75 psi, using an aqueous slurry comprising abrasive particles comprising an individual particle size of less than or equal to 100 nanometers and at a particle concentration of less than or equal to 20% by weight, and at least one of an acid or a surfactant effective to achieve a removal rate of the organic material of at least 500 Angstroms per minute. Other aspects and implementations are contemplated.

Abstract: The present technique is directed toward the fabrication of integrated circuits and provides for the production of a hardened metal layer on the surface of a semiconductor wafer to reduce the amount of material removed during chemical mechanical planarization (CMP) of the metal layer. This hardened layer may be produced, for example, by oxidizing the metal surface and/or coating the metal surface with a polymer. In one implementation, a relatively thick and dense oxide layer is formed on the wafer metal surface prior to CMP, by injecting, for example, an oxidant, such as oxygen or ozone, near the end of an annealing cycle. The hardened metal beneficially protects recessed regions from CMP chemical attack and CMP pad deformation, and thus reduces the thickness-to-planarity, dishing, and waste generation realized during CMP.

Abstract: Methods of electroless filling electrically different features such as contact openings to form interconnects and conductive contacts, and semiconductor devices, dies, and systems that incorporate the interconnects and contacts are disclosed. The contact openings are electrically shorted together with a selective material, a nucleation layer is selectively deposited onto the area to be plated (e.g., the base of the opening), and a conductive material is electroless plated onto the nucleation layer to fill the opening. The process achieves substantially simultaneous filling of openings having different surface potentials at an about even rate.

Abstract: A method for fabricating a contact structure for a stack storage capacitor includes forming the contact structure in a node contact region with contact openings, an insulating liner and a conductive filling material prior to the patterning of bit lines.

Abstract: A semiconductor device manufacturing method wherein a metal suicide layer is formed via an in-situ process. The method includes forming a gate electrode on a semiconductor substrate; forming an insulation side wall at either lateral surface of the gate electrode; forming a source/drain region in a surface of the semiconductor substrate at either side of the gate electrode; forming a metal layer on the surface of the semiconductor substrate including the gate electrode; performing a plasma treatment on the metal layer; forming a capping material layer on the metal layer; performing an annealing process upon the semiconductor substrate, to form a metal silicide layer on the surface of the semiconductor substrate at positions corresponding to the gate electrode and the source/drain region; and removing the capping material layer and the metal layer remained without reaction with the gate electrode and the semiconductor substrate.

Abstract: A method and apparatus for electroprocessing a substrate is provided. In one embodiment, a method for electroprocessing a substrate includes the steps of biasing a first electrode to establish a first electroprocessing zone between the electrode and the substrate, and biasing a second electrode disposed radially inward of the first electrode with a bias that is different than the bias applied to the first electrode. In one embodiment, the first electrode is coated with an inert material and in this way the same polish rate is obtained with a lower potential level applied to the first electrode.

Abstract: Via structure and process flow for interconnection in a semiconductor product. A bottom metal layer is provided to represent a connection layer in the semiconductor product. An isolation layer on the bottom metal layer comprises a via hole exposing a portion of the bottom metal layer. The via hole comprises a sidewall and a bottom. A first barrier metal layer is disposed on the sidewall of the via hole, but not on the bottom of the via hole. A metal under-layer is formed on the bottom of the via hole and on the first barrier metal layer. A second barrier metal layer is formed on the metal under-layer. A metal fill layer fills the via hole. A lattice mismatch between the metal under-layer and the second barrier metal layer is less than about 5%.

Abstract: In one embodiment of a method of forming at least one through-substrate interconnect, a semiconductor substrate having first surface and an opposing second surface is provided. At least one opening is formed in the semiconductor substrate to extend from the first surface to an intermediate depth within the semiconductor substrate. The at least one opening is partially defined by a base. At least one metal-catalyst nanoparticle is provided on the base. Conductive material is deposited within the at least one opening under conditions in which the metal-catalyst nanoparticle promotes deposition of the conductive material. Material of the semiconductor substrate may be removed from the second surface to expose a portion of the conductive material filling the at least one opening. In another embodiment, instead of using the nanoparticle, the conductive material may be selected to selectively deposit on the base partially defining the at least one opening.

Abstract: First material (106) is situated on the surface of a substructure (100 and 102) and in an opening (104), such as a Wench, that extends partway through the substructure. Second material (108) is situated on the first material in the opening. A physical sputter etch is performed on the structure while it is in a sputter etch module (206) to remove the parts of the first material overlying the substructure's surface and situated above the opening and to remove part of the second material overlying the first material in the opening so that remaining parts of the first and second materials are situated in the opening. The so-modified structure is transferred from the sputter etch module under a substantial vacuum, normally via a transfer module (202), to a deposition module (203, 204, or 205) where a layer of third material is deposited over the substructure's surface and over the parts of the first and second materials in the opening.

Abstract: After an insulation layer is formed on a substrate, a contact hole is formed through the insulation layer. A recessed plug is formed to partially fill up the contact hole. The recessed plug has a height substantially smaller than a depth of the contact hole. A metal wiring structure is formed on the recessed plug and on the insulation layer. A lower portion of the metal wiring structure, formed within the contact hole, prevents damage to the recessed plug during an etching process for forming the metal wiring structure. Therefore, the recessed plug may be formed without damage thereof even if an alignment error occurs between an etching mask and the recessed plug during metal wiring structure formation.

Abstract: Provided is a method for fabricating a metal line of a semiconductor device. In a method according to one embodiment, an interlayer insulating layer is formed on a semiconductor substrate. After that, a first trench and a second trench having a wider width than that of the first trench are formed in the interlayer insulating layer. A seed layer is formed on the semiconductor substrate including the first and second trenches, and a first copper layer is formed on the seed layer. Subsequently, the first copper layer is polished until the interlayer insulating layer is exposed, and a second copper layer is formed on the first copper layer. Then, the second copper layer is planarized to form a copper line.

Abstract: A method of manufacturing a semiconductor device that prevents formation of scratches and occurrence of dishing in a CMP process. The method includes forming a first film on a part of a semiconductor substrate, forming a second film all over the semiconductor substrate, and a CMP process utilizing a ceria slurry to planarize the second film using the first film as a mask, the CMP process including performing a first CMP until a portion of the first film is exposed and performing a second CMP. A first ceria slurry of a predetermined abrasive grain concentration is employed in the first CMP, and a second ceria slurry of lower abrasive grain concentration is employed in the the second CMP. The number of scratches is reduced by reducing the abrasive grain concentration of the ceria slurry, and dishing is prevented by reducing a polishing rate ratio between the first and second films.

Abstract: Structures and methods are provided which include a selective electroless copper metallization. The present invention includes a novel methodology for forming copper vias on a substrate. This method includes depositing a thin film seed layer of Palladium (Pd) or Copper (Cu) on a substrate. The seed layer is deposited to a thickness of less than 15 nanometers (nm). A photolithography technique is used to define a number of via holes above the seed layer. In one embodiment, using a photolithography technique includes forming a patterned photoresist layer to define the number of via holes above the seed layer. A layer of copper is deposited over the seed layer using electroless plating filling the number of via holes to a top surface of the patterned photoresist layer.

Abstract: A method for manufacturing a semiconductor device includes a step of forming a first groove in a first insulating film, forming a conductive film in the first groove, a step of selectively forming a second insulating film on the conductive film and the first insulating film, a step of forming a second groove by removing part of the conductive film using the second insulating film as a mask, the second groove being formed so as to form a connecting portion of the conductive film under the second insulating film and form a first wiring layer by forming the connecting portion with a bottom of the first groove integrally with each other as one unit.

Abstract: Methods of forming isolation regions for semiconductor devices and structures thereof are disclosed. A workpiece having a top surface is provided, a chemical mechanical polish (CMP) stop layer is formed over the workpiece, and a sacrificial material is formed over the CMP stop layer. The sacrificial material, the CMP stop layer, and the workpiece are patterned with a trench for an isolation region. The isolation region is filled with an insulating material, and a CMP process is used to remove the insulating material from over the top surface of the CMP stop layer. The sacrificial material is removed during the CMP process.

Abstract: In a method of manufacturing a semiconductor device, a first trench is formed in a first region of a substrate and a second trench is formed in a second region of the substrate different from the first region. A depth of the first trench is less than that of the second trench. An insulation layer is formed in the second trench, so that semiconductor structures in the first trench are electrically isolated, and a conductive layer fills the first trench and extends above the first trench.

Abstract: A method of electrochemically filling features on a wafer surface to form a substantially planar copper layer is provided. The features to be filled includes a first feature that is an unfilled feature with the smallest width and a second feature having the next larger width after the smallest feature. The first and the second features are less than 10 micrometers in width. The method comprises applying a first cathodic current to form a first copper layer on the wafer surface. The first copper layer has a planar portion over a first feature and a non-planar portion over a second feature. After a surface of the first copper layer is treated by applying a first pulsed current, a second cathodic current is applied to form a second copper layer on the first copper layer. The second copper layer has a planar portion over both the first and second features.

Abstract: A method for forming metrology structures for a CMP process is described. A trench edge is formed in a base material or stack of materials which are preferably deposited as part of the process of fabricating the production structures on the wafer. A covering film of a second material with preferably with contrasting SEM properties is deposited over the trench edge in the base material. During CMP the covering film is preferentially worn away at the edge revealing the base material. The width of the base material which has been revealed is a measure of the progress of the CMP. Since the base material and the covering material are preferably selected to have contrasting images in an SEM, a CD-SEM can be used to precisely measure the CMP progress.

Abstract: In a semiconductor device, a wiring pattern groove is formed in a surface portion of a silicon oxide film provided above a semiconductor substrate. A wiring layer is buried into the wiring pattern groove with a barrier metal film interposed therebetween. The barrier metal film is selectively removed from each sidewall portion of the wiring pattern groove. In other words, the barrier metal film is left only on the bottom of the wiring pattern groove. Thus, a damascene wiring layer having a hollow section whose dielectric constant is low between each sidewall of the wiring pattern groove and each side of the wiring layer can be formed in the semiconductor device.

Abstract: Disclosed is a method for fabricating a semiconductor device without damaging a hard mask of a conductive structure. The method includes the steps of: forming a plurality of conductive structures on a substrate, each conductive structure including a conductive layer and a hard mask; sequentially forming a first nitride layer, an oxide layer, a second nitride layer, and an etch stop layer on the plurality of conductive structures; forming an inter-layer insulation layer on the etch stop layer; removing a portion of the inter-layer insulation layer through a planarization process; performing a self-aligned etching (SAC) process selectively etching the inter-layer insulation layer, the second nitride layer and the oxide layer until the SAC etching process is stopped at the first nitride layer to thereby form a contact hole exposing the first nitride layer; and removing the first nitride layer by performing a blanket etch-back process to thereby expose the conductive layer.

Abstract: Method and structure for optimizing and controlling chemical mechanical planarization are disclosed. Embodiments of the invention include planarization techniques to make nonplanar surfaces comprising alternating metal and intermetal layers. Relative protrusion dimensions and uniformity of various layers may be accurately controlled using the disclosed techniques.