Barrier, Adhesion Or Liner Layer (epo) Patents (Class 257/E21.584)
  • Patent number: 10757821
    Abstract: A single-layer circuit board, multi-layer circuit board, and manufacturing methods therefor. The method for manufacturing the single-layer circuit board (10) comprises the following steps: drilling a hole on a substrate (11), the hole comprising a blind hole and/or a through hole (S1); on a surface (12) of the substrate, forming a photoresist layer having a circuit negative image (S2); forming a conductive seed layer on the surface (12) of the substrate and a hole wall (19) of the hole (S3); removing the photoresist layer, and forming a circuit pattern on the surface (12) of the substrate (S4), wherein Step S3 comprises implanting a conductive material below the surface (12) of the substrate and below the hole wall (19) of the hole via ion implantation, and forming an ion implantation layer as at least part of the conductive seed layer.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: August 25, 2020
    Assignee: RICHVIEW ELECTRONICS CO., LTD.
    Inventors: Siping Bai, Xianglan Wu, Zhijian Wang, Zhigang Yang, Jinqiang Zhang
  • Patent number: 10727122
    Abstract: A self-aligned via interconnect structures and methods of manufacturing thereof are disclosed. The method includes forming a wiring structure in a dielectric material. The method further includes forming a cap layer over a surface of the wiring structure and the dielectric material. The method further includes forming an opening in the cap layer to expose a portion of the wiring structure. The method further includes selectively growing a metal or metal-alloy via interconnect structure material on the exposed portion of the wiring structure, through the opening in the cap layer. The method further includes forming an upper wiring structure in electrical contact with the metal or metal-alloy via interconnect structure.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: July 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin C. Backes, Brian A. Cohen, Joyeeta Nag, Carl J. Radens
  • Patent number: 10714586
    Abstract: A semiconductor device includes a source/drain region, a source/drain silicide layer formed on the source/drain region, and a first contact disposed over the source/drain silicide layer. The first contact includes a first metal layer, an upper surface of the first metal layer is at least covered by a silicide layer, and the silicide layer includes a same metal element as the first metal layer.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: July 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Ming Hsu, Pei-Yu Chou, Chih-Pin Tsao, Kuang-Yuan Hsu, Jyh-Huei Chen
  • Patent number: 10699946
    Abstract: Methods for depositing a metal layer in a feature definition of a semiconductor device are provided. In one implementation, a method for depositing a metal layer for forming a semiconductor device is provided. The method comprises performing a cyclic metal deposition process to deposit a metal layer on a substrate and annealing the metal layer disposed on the substrate. The cyclic metal deposition process comprises exposing the substrate to a deposition precursor gas mixture to deposit a portion of the metal layer on the substrate, exposing the portion of the metal layer to either a plasma treatment process or hydrogen annealing process and repeating the exposing the substrate to a deposition precursor gas mixture and exposing the portion of the metal layer to either a plasma treatment process or hydrogen annealing process until a predetermined thickness of the metal layer is achieved.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: June 30, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Bhushan N. Zope, Avgerinos V. Gelatos, Bo Zheng, Yu Lei, Xinyu Fu, Srinivas Gandikota, Sang Ho Yu, Mathew Abraham
  • Patent number: 10685842
    Abstract: The present disclosure relates to a method for fabricating a semiconductor structure. The method includes providing a substrate with a gate structure, an insulating structure over the gate structure, and a S/D region; depositing a titanium silicide layer over the S/D region with a first chemical vapor deposition (CVD) process. The first CVD process includes a first hydrogen gas flow. The method also includes depositing a titanium nitride layer over the insulating structure with a second CVD process. The second CVD process includes a second hydrogen gas flow. The first and second CVD processes are performed in a single reaction chamber and a flow rate of the first hydrogen gas flow is higher than a flow rate of the second hydrogen gas flow.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: June 16, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Wei Chang, Kao-Feng Lin, Min-Hsiu Hung, Yi-Hsiang Chao, Huang-Yi Huang, Yu-Ting Lin
  • Patent number: 10577386
    Abstract: Metal coordination complexes comprising a metal atom coordinated to at least one diazabutadiene ligand having a structure represented by: where each R is independently a C1-C13 alkyl or aryl group and each R? is independently H, C1-C10 alkyl or aryl group are described. Processing methods using the metal coordination complexes are also described.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: March 3, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Benjamin Schmiege, Jeffrey W. Anthis, David Thompson
  • Patent number: 10529722
    Abstract: Disclosed herein are methods and related apparatus for formation of multi-component tungsten-containing films including multi-component tungsten-containing films diffusion barriers. According to various embodiments, the methods involve deposition of multi-component tungsten-containing films using tungsten chloride (WClx) precursors and boron (B)-containing, silicon (Si)-containing or germanium (Ge)-containing reducing agents.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: January 7, 2020
    Assignee: Lam Research Corporation
    Inventors: Michal Danek, Hanna Bamnolker, Raashina Humayun, Juwen Gao
  • Patent number: 10483162
    Abstract: A semiconductor structure and a fabrication method are provided. The fabrication method includes: providing a substrate; forming a dielectric layer with an opening on the substrate; forming a first barrier layer on sidewall and bottom surfaces of the opening, the first barrier layer being doped by manganese; and forming a metal interconnect on the first barrier layer, the metal interconnect being located within the opening.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: November 19, 2019
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Hao Deng
  • Patent number: 10446496
    Abstract: A method for forming a conductor includes forming trenches in an insulator layer. An alloy layer is deposited in the trenches. The alloy layer includes a conductor material and a barrier material. The alloy layer is annealed to form a barrier layer on the insulator layer and to purify the alloy layer into a conductor layer, such that the barrier material in the alloy layer is driven to an interface between the alloy layer and the insulator layer.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: October 15, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Takeshi Nogami, Michael Rizzolo
  • Patent number: 10438847
    Abstract: Provided herein are methods of forming conductive cobalt (Co) interconnects and Co features. The methods involve deposition of a thin manganese (Mn)-containing film on a dielectric followed by subsequent deposition of cobalt on the Mn-containing film. The Mn-containing film may be deposited on a silicon-containing dielectric, such as silicon dioxide, and annealed to form a manganese silicate.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: October 8, 2019
    Assignee: Lam Research Corporation
    Inventors: Chiukin Steven Lai, Jeong-Seok Na, Raashina Humayun, Michal Danek, Kaihan Abidi Ashtiani
  • Patent number: 10418391
    Abstract: Disclosed are a display substrate, a manufacture method thereof, and a display device. The display substrate comprises: a base substrate, and a metal layer, at least one insulating layer and a metal oxide conducting layer respectively on the base substrate, wherein, the at least one insulating layer is disposed between the metal layer and the metal oxide conducting layer; the metal oxide conducting layer is electrically connected to the metal layer through at least one via hole penetrating the at least one insulating layer; and the metal oxide conducting layer in the at least one via hole comprises metal particles produced by reducing the metal oxide conducting layer.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: September 17, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Kui Gong, Qingli Feng
  • Patent number: 10403564
    Abstract: Techniques that can assist with fabricating a package layer that includes a plurality of dual-damascene zero-misalignment-vias (dual-damascene ZMVs) and a trace between the dual-damascene ZMVs are described. The disclosed techniques allow for the dual-damascene ZMVs and their corresponding trace to be plated simultaneously in a single step or operation. As such, there is little or no misalignment between the dual-damascene ZMVs, the trace, and the metal pads connected to the ZMVs. In this way, one or more of the embodiments described herein can assist with reducing manufacturing costs, reducing development time of fabricating a package layer, and with increasing the I/O density in a semiconductor package.
    Type: Grant
    Filed: December 30, 2017
    Date of Patent: September 3, 2019
    Assignee: Intel Corporation
    Inventors: Aleksandar Aleksov, Hiroki Tanaka, Robert A. May, Kristof Darmawikarta, Changhua Liu, Chung Kwang Tan, Srinivas Pietambaram, Sri Ranga Sai Boyapati
  • Patent number: 10354916
    Abstract: Methods of wordline separation in semiconductor devices (e.g., 3D-NAND) are described. A metal film is deposited in the wordlines and on the surface of a stack of spaced oxide layers. The metal film is removed by high temperature oxidation and etching of the oxide or low temperature atomic layer etching by oxidizing the surface and etching the oxide in a monolayer fashion. After removal of the metal overburden, the wordlines are filled with the metal film.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: July 16, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Yihong Chen, Ziqing Duan, Abhijit Basu Mallick, Kelvin Chan
  • Patent number: 10321581
    Abstract: A single-layer circuit board, multi-layer circuit board, and manufacturing methods therefor. The method for manufacturing the single-layer circuit board (10) comprises the following steps: drilling a hole on a substrate (11), the hole comprising a blind hole and/or a through hole (S1); on a surface (12) of the substrate, forming a photoresist layer having a circuit negative image (S2); forming a conductive seed layer on the surface (12) of the substrate and a hole wall (19) of the hole (S3); removing the photoresist layer, and forming a circuit pattern on the surface (12) of the substrate (S4), wherein Step S3 comprises implanting a conductive material below the surface (12) of the substrate and below the hole wall (19) of the hole via ion implantation, and forming an ion implantation layer as at least part of the conductive seed layer.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: June 11, 2019
    Assignee: RICHVIEW ELECTRONICS CO., LTD.
    Inventors: Siping Bai, Xianglan Wu, Zhijian Wang, Zhigang Yang, Jinqiang Zhang
  • Patent number: 10304773
    Abstract: An electrical device is provided that includes at least one contact surface and an interlevel dielectric layer present atop the electrical device. The interlevel dielectric layer may include at least one trench to the at least one contact surface of the electrical device. A liner of tantalum or tantalum nitride can be present on sidewalls of the trench structure and a base surface of the trench provided by the contact surface of the electrical device. A copper fill promoting liner that includes at least one ruthenium (Ru), rhodium (Rh), iridium (Ir), osmium (Os), molybdenum (Mo), and copper (Cu) may be in direct contact with the liner of tantalum or tantalum nitride. A copper containing metal that fills the at least one trench and is present directly on the copper fill promoting liner.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: May 28, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Praneet Adusumilli, Alexander Reznicek, Oscar van der Straten, Chih-Chao Yang
  • Patent number: 10304676
    Abstract: A method for forming a nitride film is provided. The method includes preparing a substrate to be processed, the substrate having a first base film formed of a material having a relatively long incubation time and a second base film formed of a material having a relatively short incubation time with respect to a nitride film, forming a nitride film on the substrate by means of ALD or CVD using a raw material gas and a nitriding gas while heating the substrate to a predetermined temperature, and etching nitride on the first base film to be removed by supplying an etching gas to thereby expose a film surface of the first base film, wherein the forming the nitride film and the etching the nitride are repeatedly performed a predetermined number of times to selectively form the nitride film on the second base film.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: May 28, 2019
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Takahiro Miyahara, Daisuke Suzuki, Hiroki Murakami
  • Patent number: 10304725
    Abstract: Embodiments are disclosed for processing microelectronic workpieces having patterned structures that include ultra-low dielectric constant (k) (ULK) material layers. In particular, embodiments are disclosed that deposit protective layers to protect ULK features during etch processing of patterned structures within substrates for microelectronic workpieces. For certain embodiments, these protective layers are deposited in-situ within the etch chamber.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: May 28, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Xinghua Sun, Takashi Yamamura, Hiroyuki Nagai, Ryuichi Asako, Katie Lutker-Lee
  • Patent number: 10297548
    Abstract: A semiconductor device includes a semiconductor substrate, an epitaxy structure present in the semiconductor substrate, and a silicide present on a textured surface of the epitaxy structure. A plurality of sputter ions are present between the silicide and the epitaxy structure. Since the surface of the epitaxy structure is textured, the contact area provided by the silicide is increased accordingly, thus the resistance of a interconnection structure in the semiconductor device is reduced.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: May 21, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Hung Lin, Chi-Wen Liu, Horng-Huei Tseng
  • Patent number: 10285268
    Abstract: A printed circuit board (PCB) includes: a substrate; and a circuit pattern disposed on the substrate, wherein the circuit pattern includes a first seed layer disposed on the substrate and including a nitride, and a metal layer disposed on the first seed layer.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: May 7, 2019
    Assignee: LG INNOTEK CO., LTD.
    Inventor: Gi Gon Park
  • Patent number: 10276501
    Abstract: An integrated circuit device includes a substrate including a dielectric layer patterned with a set of conductive line trenches, each conductive line trench having parallel vertical sidewalls and a horizontal bottom. A liner which is an alloy of a first metal and a selected element formed at interfaces of the metal layer and a surface of the dielectric and is created by an anneal and reflow process. The first metal having a first conductivity in a pure form. A second metal layer fills the set of conductive line trenches, the second metal having a second conductivity higher than the first conductivity.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: April 30, 2019
    Assignee: International Business Machines Corporation
    Inventors: Daniel C Edelstein, Chih-Chao Yang
  • Patent number: 10269714
    Abstract: A method of forming a contact to a semiconductor device is provided that forms an alloy composed of nickel (Ni), platinum (Pt), aluminum (Al), titanium (Ti) and a semiconductor material. The methods may include forming a nickel and platinum semiconductor alloy at a base of a via. A titanium layer having an angstrom scale thickness is deposited in the via in contact with the nickel platinum semiconductor alloy. An aluminum containing fill is deposited atop the titanium layer. A forming gas anneal including an oxygen containing atmosphere is applied to the structure to provide a contact alloy comprising nickel, platinum, aluminum, titanium and a semiconductor element from the contact surface of the semiconductor device.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: April 23, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John Bruley, Jack O. Chu, Kam-Leung Lee, Ahmet S. Ozcan, Paul M. Solomon, Jeng-bang Yau
  • Patent number: 10269926
    Abstract: A method includes placing a wafer in a wafer holder, placing the wafer holder on a loadport of a deposition tool, connecting the wafer holder to a front-end interface unit of the deposition tool, purging the front-end interface unit with nitrogen, and depositing a metal layer on the wafer in the deposition tool.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Ying Liu, Chun-Wen Nieh, Yu-Sheng Wang, Yu-Ting Lin, Wei-Yu Chen
  • Patent number: 10170425
    Abstract: A metal interconnect layer, a method of forming the metal interconnect layer, a method of forming a device that includes the metal interconnect layer are described. The method of forming the metal interconnect layer includes forming an opening in a dielectric layer, forming a metal layer in the opening and over a top surface of the dielectric layer. The method also includes disposing a metal passivation layer on an overburden portion of the metal layer formed over the top surface of the dielectric layer. The metal passivation layer includes a metal selected from a group of: cobalt (Co), ruthenium (Ru), tantalum (Ta), titanium (Ti), nickel (Ni), tungsten (W), any alloy thereof, nitrides of Co, Ru, Ti, Ni, or W, and any combination thereof. The method also includes performing an anneal at a temperature exceeding 100 degrees centigrade and below 300 degrees centigrade.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: January 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hong He, Juntao Li, Junli Wang, Chih-Chao Yang
  • Patent number: 10163929
    Abstract: The invention is related to a method for manufacturing a semiconductor device having a barrier pattern. The method includes alternately forming first sacrificial layers and insulating layers forming channel patterns penetrating the first sacrificial layers and the insulating layers, and forming a slit penetrating the first sacrificial layers and the insulating layers. In order to form the barrier pattern, the method also includes forming openings by removing the first sacrificial layers through the slit, and respectively forming conductive layers in the openings. The conductive layers include first barrier patterns having inclined inner surfaces and metal patterns in the first barrier patterns.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: December 25, 2018
    Assignee: SK Hynix Inc.
    Inventors: Ki Hong Lee, Duk Eui Lee
  • Patent number: 10128149
    Abstract: Provided is a highly reliable semiconductor device and a method for manufacturing same. The method for manufacturing the semiconductor device includes forming an interlayer insulating film on a semiconductor substrate, forming a conductive plug in the interlayer insulating film, the conductive plug having a top surface for forming the same plane as the top surface of the interlayer insulating film, forming a first titanium film on the interlayer insulating film and the conductive plug, forming an aluminum diffusion-preventing film on the first titanium film, forming a second titanium film on the aluminum diffusion-preventing film, forming an aluminum film on the second titanium film, and shaping the area from the aluminum film to the first titanium film by etching to form wiring.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: November 13, 2018
    Assignee: LONGITUDE LICENSING LIMITED
    Inventor: Takashi Kansaku
  • Patent number: 10128186
    Abstract: An integrated circuit device having a substrate including a dielectric layer is patterned with a set of conductive line trenches. Each conductive line trench of the conductive line pattern having parallel vertical sidewalls and a horizontal bottom. A metal fills the set of conductive line trenches, wherein the metal fill is created by an anneal and reflow process. A liner which is an alloy of the metal and a selected element formed at interfaces of the metal layer and a surface of the dielectric, created simultaneously with the metal fill by the anneal and reflow process.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: November 13, 2018
    Assignee: International Business Machines Corporation
    Inventors: Daniel C Edelstein, Chih-Chao Yang
  • Patent number: 10096545
    Abstract: There is provided an image capturing apparatus including a pixel circuit that generates a pixel signal based on an electric charge generated by photoelectric conversion and a logic circuit that outputs a signal based on the pixel signal. The image capturing apparatus includes a first contact plug connected to a source or a drain of a first transistor constituting the pixel circuit and a second contact plug connected to a source or a drain of a second transistor constituting the logic circuit. A diameter of the first contact plug is smaller than a diameter of the second contact plug.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: October 9, 2018
    Assignee: Canon Kabushiki Kaisha
    Inventors: Akihiro Kawano, Tsutomu Tange, Masao Ishioka, Koichi Tazoe
  • Patent number: 10026649
    Abstract: Techniques are disclosed for providing a decoupled via fill. Given a via trench, a first barrier layer is conformally deposited onto the bottom and sidewalls of the trench. A first metal fill is blanket deposited into the trench. The non-selective deposition is subsequently recessed so that only a portion of the trench is filled with the first metal. The previously deposited first barrier layer is removed along with the first metal, thereby re-exposing the upper sidewalls of the trench. A second barrier layer is conformally deposited onto the top of the first metal and the now re-exposed trench sidewalls. A second metal fill is blanket deposited into the remaining trench. Planarization and/or etching can be carried out as needed for subsequent processing. Thus, a methodology for filling high aspect ratio vias using a dual metal process is provided. Note, however, the first and second fill metals may be the same.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: July 17, 2018
    Assignee: INTEL CORPORATION
    Inventors: Yuriy V. Shusterman, Flavio Griggio, Tejaswi K. Indukuri, Ruth A. Brain
  • Patent number: 10008449
    Abstract: A method of forming electrically conductive structures that includes forming a copper containing layer including a barrier forming element, and applying a first anneal to the copper containing layer. The first anneal increases grain size of the copper in the copper containing layer. The copper containing layer is etched to provide a plurality of copper containing lines. A dielectric fill is deposited in the space between adjacent copper containing lines. A second anneal is applied to the plurality of copper containing lines. During the second anneal the barrier forming element diffuse to an interface between sidewalls of the copper containing lines and the dielectric fill to form a barrier layer along the sidewalls of the copper containing lines.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: June 26, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Theodorus E. Standaert, Vamsi K. Paruchuri
  • Patent number: 9988713
    Abstract: A method for preparing a device having a film on a substrate is disclosed. In the method, a film is deposited on a polymeric substrate. The film includes at least one metal. A metal in the film is converted to a metal oxide using microwave radiation. One example device prepared by the method includes a polyethylene napthalate substrate and a film on the substrate, wherein the film includes a semiconducting copper oxide and silver as a dopant.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: June 5, 2018
    Assignee: Arizona Board of Regents on Behalf of Arizona State University
    Inventors: Terry Alford, Sayantan Das
  • Patent number: 9953867
    Abstract: Disclosed are a method of forming a seed layer on a high-aspect ratio via and a semiconductor device having a high-aspect ratio via formed thereby. Thus, efficient Cu filling-plating is possible, and plating adhesion of the seed layer to filling-plated Cu can be simply and profitably enhanced, thus imparting high durability upon forming metal wiring for electronic components. Moreover, stress of the seed layer can be lowered, thereby enhancing plating adhesion.
    Type: Grant
    Filed: March 24, 2014
    Date of Patent: April 24, 2018
    Assignee: KOREA INSTITUTE OF INDUSTRIAL TECHNOLOGY
    Inventors: Young Sik Song, Tae Hong Yim
  • Patent number: 9899584
    Abstract: A semiconductor device includes a light emitting structure, and an interconnection bump including an under bump metallurgy (UBM) layer disposed on an electrode of at least one of the first and second conductivity-type semiconductor layers, and having a first surface disposed opposite to a surface of the electrode and a second surface extending from an edge of the first surface to be connected to the electrode, an intermetallic compound (IMC) disposed on the first surface of the UBM layer, a solder bump bonded to the UBM layer with the IMC therebetween, and a barrier layer disposed on the second surface of the UBM layer and substantially preventing the solder bump from being diffused into the second surface of the UBM layer.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: February 20, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Seok Min Hwang
  • Patent number: 9899258
    Abstract: Overhang reduction methods are disclosed. In some embodiments, a method includes forming a recess in a dielectric layer, the recess defining first sidewalls of the dielectric layer. The method also includes depositing a first conductive layer over an upper surface of the dielectric layer and the sidewalls of the dielectric layer, the first conductive layer having a first overhang, removing the first overhang of the first conductive layer using an etchant selected from the group consisting of a halide of the first conductive layer, Cl2, BCl3, SPM, SC1, SC2, and combinations thereof, and filling the recess with a second conductive layer.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: February 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pei-Wen Wu, Sung-Li Wang, Min-Hsiu Hung, Yida Li, Chih-Wei Chang, Huang-Yi Huang, Cheng-Tung Lin, Jyh-Cherng Sheu, Yee-Chia Yeo, Chi On Chui
  • Patent number: 9893071
    Abstract: A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes a semiconductor substrate including an active region defined by a device isolation film, a bit line contact plug that is coupled to the active region and that includes a first ion implantation region buried in a first inner void, and a storage node contact plug that is coupled to the active region and includes a second ion implantation region buried in a second inner void. Although the semiconductor device is highly integrated, a contact plug is buried to prevent formation of a void, so that increase in contact plug resistance is prevented, resulting in improved semiconductor device characteristics.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: February 13, 2018
    Assignee: SK HYNIX INC.
    Inventors: Jae Soo Kim, Jae Chun Cha
  • Patent number: 9881871
    Abstract: A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: January 30, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Hai-Ching Chen, Tien-I Bao
  • Patent number: 9881798
    Abstract: A middle-of-line interconnect structure including copper interconnects and integral copper alloy caps provides effective electromigration resistance. A metal cap layer is deposited on the top surfaces of the interconnects. A post-deposition anneal causes formation of the copper alloy caps from the interconnects and the metal cap layer. Selective removal of unalloyed metal cap layer material provides an interconnect structure free of metal residue on the dielectric material layer separating the interconnects.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: January 30, 2018
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Alexander Reznicek, Oscar van der Straten, Chih-Chao Yang
  • Patent number: 9875888
    Abstract: Processes for depositing SiO2 films on a wafer surface utilizing an aminosilane compound as a silicon precursor are described.
    Type: Grant
    Filed: October 1, 2015
    Date of Patent: January 23, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Wenbo Yan, Cong Trinh, Ning Li, Victor Nguyen, Mihaela Balseanu, Li-Qun Xia, Mark Saly
  • Patent number: 9865538
    Abstract: A semiconductor structure is provided that includes a first interconnect dielectric layer containing a first interconnect metal structure embedded therein. A second interconnect dielectric layer containing a second interconnect metal structure embedded therein is located atop the first interconnect dielectric layer. A metallic blocking layer is present that separates a surface of the second interconnect metal structure from a surface of the first interconnect metal structure. The metallic blocking layer has a lower resistivity than the first and second interconnect metal structures. The metallic blocking layer prevents electromigration of metallic ions from the first and second interconnect metal structure.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: January 9, 2018
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Alexander Reznicek, Oscar van der Straten, Chih-Chao Yang
  • Patent number: 9831181
    Abstract: An integrated circuit device having a substrate including a dielectric layer is patterned with a set of conductive line trenches. Each conductive line trench has parallel vertical sidewalls and a horizontal bottom. A first metal layer fills a first portion of the set of conductive line trenches. The first metal layer is created by an anneal and reflow process of a first metal. A liner which is an alloy of the first metal and a selected element is formed at interfaces of the metal layer and a surface of the dielectric. The liner is created simultaneously with the metal fill by the anneal and reflow process. A wetting layer is disposed on the first metal layer and fills a second portion of the set of conductive line trenches. A second metal layer is disposed on the wetting layer and fills a remainder portion of the set of conductive line trenches.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: November 28, 2017
    Assignee: International Business Machines Corporation
    Inventors: Daniel C Edelstein, Chih-Chao Yang
  • Patent number: 9806024
    Abstract: An integrated circuit device having a substrate including a dielectric layer is patterned with a set of conductive line trenches. Each conductive line trench has parallel vertical sidewalls and a horizontal bottom. A first metal fills a first portion of the set of conductive line trenches, wherein the metal fill is created by an anneal and reflow process. A liner which is an alloy of the first metal and a selected element is formed at the interfaces of the metal layer and a surface of the dielectric and is created simultaneously with the metal fill by the anneal and reflow process. A second metal layer fills a remainder portion of the set of conductive line trenches.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: October 31, 2017
    Assignee: International Business Machines Corporation
    Inventors: Daniel C. Edelstein, Chih-Chao Yang
  • Patent number: 9761487
    Abstract: It is to provide a manufacturing method of a semiconductor device including the following step of: preparing a semiconductor substrate having a silicon nitride film on the rear surface; forming an interlayer insulating film having a via hole on the main surface of the semiconductor substrate; and forming a via-fill selectively within the via hole. The method further includes the steps of: performing the wafer rear surface cleaning to expose the surface of the silicon nitride film formed on the rear surface of the semiconductor substrate; and thereafter, forming a photoresist film made of chemical amplification type resist on the interlayer insulating film and the via-fill over the main surface of the semiconductor substrate, in which the semiconductor substrate is stored in an atmosphere with the ammonium ion concentration of 1000 ?g/m3 and less.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: September 12, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kiyoshi Maeshima, Kotaro Horikoshi, Katsuhiko Hotta, Toshiyuki Takahashi, Hironori Ochi, Kenichi Shoji
  • Patent number: 9728399
    Abstract: In one aspect of the invention, a method for fabricating an advanced metal conductor structure includes a conductive line pattern including a set of conductive line trenches in a dielectric layer. Each conductive line trench of the conductive line pattern has parallel vertical sidewalls and a horizontal bottom. A surface treatment of the dielectric layer is performed. The surface treatment produces an element enriched surface layer in which a concentration of a selected element in a surface portion of the parallel sidewalls and horizontal bottoms of the conductive line trenches is increased. A first metal layer is deposited on the element enriched surface layer. A first thermal anneal is performed which simultaneously reflows the first metal layer to fill a first portion of the conductive line trenches and causes a chemical change at interfaces of the first metal layer and the element enriched surface layer creating a liner which is an alloy of the first metal and selected element.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: August 8, 2017
    Assignee: International Business Machines Corporation
    Inventors: Daniel C Edelstein, Chih-Chao Yang
  • Patent number: 9728414
    Abstract: The present method of forming an electronic structure includes providing a tantalum base layer and depositing a layer of copper on the tantalum layer, the deposition being undertaken by physical vapor deposition with the temperature of the base layer at 50.degree. C. or less, with the deposition taking place at a power level of 300 W or less.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: August 8, 2017
    Assignee: Cypress Semiconductor Corporation
    Inventors: Wen Yu, Stephen B. Robie, Jeremias D. Romero
  • Patent number: 9685371
    Abstract: Methods for depositing a metal layer in a feature definition of a semiconductor device are provided. In one implementation, a method for depositing a metal layer for forming a semiconductor device is provided. The method comprises performing a cyclic metal deposition process to deposit a metal layer on a substrate and annealing the metal layer disposed on the substrate. The cyclic metal deposition process comprises exposing the substrate to a deposition precursor gas mixture to deposit a portion of the metal layer on the substrate, exposing the portion of the metal layer to either a plasma treatment process or hydrogen annealing process and repeating the exposing the substrate to a deposition precursor gas mixture and exposing the portion of the metal layer to either a plasma treatment process or hydrogen annealing process until a predetermined thickness of the metal layer is achieved.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: June 20, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Bhushan N. Zope, Avgerinos V. Gelatos, Bo Zheng, Yu Lei, Xinyu Fu, Srinivas Gandikota, Sang Ho Yu, Mathew Abraham
  • Patent number: 9653352
    Abstract: Methods for forming metal organic tungsten for middle-of-the-line (MOL) applications are provided herein. In some embodiments, a method of processing a substrate includes providing a substrate to a process chamber, wherein the substrate includes a feature formed in a first surface of a dielectric layer of the substrate; exposing the substrate to a plasma formed from a first gas comprising a metal organic tungsten precursor to form a tungsten barrier layer atop the dielectric layer and within the feature, wherein a temperature of the process chamber during formation of the tungsten barrier layer is less than about 225 degrees Celsius; and depositing a tungsten fill layer over the tungsten barrier layer to fill the feature to the first surface.
    Type: Grant
    Filed: June 10, 2014
    Date of Patent: May 16, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Liqi Wu, Sang Ho Yu, Kazuya Daito, Kie Jin Park, Kai Wu, David Thompson
  • Patent number: 9601587
    Abstract: A semiconductor device includes a gate stack overlying a substrate. The semiconductor device further includes a spacer on sidewalls of the gate stack, where a top surface of the spacer is above a top surface of the gate stack. Additionally, the semiconductor device includes a protection layer overlying the gate stack and filling at least a portion of a space surrounded by the spacer above the top surface of the gate stack. Furthermore, the semiconductor device includes a contact hole over the spacer, where the contact hole extends over the gate stack, and where a sidewall of the contact hole has a step-wise shape.
    Type: Grant
    Filed: January 23, 2015
    Date of Patent: March 21, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sey-Ping Sun, Tsung-Lin Lee, Chin-Hsiang Lin, Chih-Hao Chang, Chen-Nan Yeh, Chao-An Jong
  • Patent number: 9583687
    Abstract: A semiconductor device includes a light emitting structure, and an interconnection bump including an under bump metallurgy (UBM) layer disposed on an electrode of at least one of the first and second conductivity-type semiconductor layers, and having a first surface disposed opposite to a surface of the electrode and a second surface extending from an edge of the first surface to be connected to the electrode, an intermetallic compound (IMC) disposed on the first surface of the UBM layer, a solder bump bonded to the UBM layer with the IMC therebetween, and a barrier layer disposed on the second surface of the UBM layer and substantially preventing the solder bump from being diffused into the second surface of the UBM layer.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: February 28, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Seok Min Hwang
  • Patent number: 9564359
    Abstract: Conductive structures and method of manufacture thereof are disclosed. In some embodiments, a method of forming a conductive structure includes providing a substrate having a recess formed therein, the recess lined with a first seed layer and partially filled with a first conductive material; removing a portion of the first seed layer free from the first conductive material to form an exposed surface of the recess; lining the exposed surface of the recess with a second seed layer; and filling the recess with a second conductive material, the second conductive material covering the first conductive material and the second seed layer.
    Type: Grant
    Filed: July 17, 2014
    Date of Patent: February 7, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pin-Wen Chen, Chih-Wei Chang
  • Patent number: 9543198
    Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate and forming a dielectric layer over the semiconductor substrate. An opening is formed in the dielectric layer. A conductive line is formed in the opening, wherein the conductive line has an open void formed therein. A sealing metal layer is formed overlying the conductive line, the dielectric layer, and the open void, wherein the sealing metal layer substantially fills the open void. The sealing metal layer is planarized so that a top surface thereof is substantially level with a top surface of the conductive line. An interconnect feature is formed above the semiconductor substrate, wherein the interconnect feature is electrically coupled with the conductive line and the sealing metal layer-filled open void.
    Type: Grant
    Filed: January 9, 2015
    Date of Patent: January 10, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chien Chi, Huang-Yi Huang, Szu-Ping Tung, Ching-Hua Hsieh
  • Patent number: 9472504
    Abstract: The present disclosure provides various embodiments of a via structure and method of manufacturing same. In an example, a via structure includes a via having via sidewall surfaces defined by a semiconductor substrate. The via sidewall surfaces have a first portion and a second portion. A conductive layer is disposed in the via on the first portion of the via sidewall surfaces, and a dielectric layer is disposed on the second portion of the via sidewall surfaces. The dielectric layer is disposed between the second portion of the via sidewall surfaces and the conductive layer. In an example, the dielectric layer is an oxide layer.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: October 18, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yuan-Chih Hsieh, Li-Cheng Chu, Ming-Tung Wu, Ping-Yin Liu, Lan-Lin Chao, Chia-Shiung Tsai