By Forming Conductive Members Before Deposition Of Protective Insulating Material, E.g., Pillars, Studs (epo) Patents (Class 257/E21.589)
  • Patent number: 10134580
    Abstract: Structures for metallization levels of integrated circuits and associated fabrication methods. A first metallization level with a metallization line is formed. A second metallization level is formed over the first metallization level, having two metallization lines and two conductive vias extending from the two metallization lines to the metallization line in the first metallization level. The first metallization line is separated into a first section and a second section disconnected from the first section, so that the first section is connected by one conductive via to one metallization line in the second metallization level, and the second section is connected by the other conductive via to the other metallization line in the second level.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: November 20, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Nicholas V. LiCausi, Errol Todd Ryan, Sean Xuan Lin
  • Patent number: 9691751
    Abstract: A method of fabricating an integrated circuit (IC) includes etching a trench in a semiconductor substrate having an aspect ratio (AR) ?5 and a trench depth ?10 ?m. A dielectric liner is formed along the walls of the trench to form a dielectric lined trench. In-situ doped polysilicon is deposited into the trench to form a dielectric lined polysilicon filled trench having a doped polysilicon filler therein. The doped polysilicon filler after completion of fabricating the IC is essentially polysilicon void-free and has a 25° C. sheet resistance ?100 ohms/sq. The method can include etching an opening at a bottom of the dielectric liner before depositing the polysilicon to provide ohmic contact to the semiconductor substrate.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: June 27, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Bhaskar Srinivasan, Khanh Quang Le, Collin White, Sopa Chevacharoenkul, Ashley Norris, Bernard John Fischer
  • Patent number: 9287164
    Abstract: Cavities of possibly different widths can be etched in a stack of conductive layers (such as metal) using the same lithographic mask. Dielectric can be formed in the cavities. The cavities may contain voids. Other embodiments are also provided.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: March 15, 2016
    Assignee: Tessera, Inc.
    Inventors: Cyprian Uzoh, Vage Oganesian, Ilyas Mohammed, Craig Mitchell, Belgacem Haba
  • Patent number: 9018769
    Abstract: A method of forming a conductive element on a substrate and the resulting assembly are provided. The method includes forming a groove in a sacrificial layer overlying a dielectric region disposed on a substrate. The groove preferably extends along a sloped surface of the substrate. The sacrificial layer is preferably removed by a non-photolithographic method, such as ablating with a laser, mechanical milling, or sandblasting. A conductive element is formed in the groove. The grooves may be formed. The grooves and conductive elements may be formed along any surface of the substrate, including within trenches and vias formed therein, and may connect to conductive pads on the front and/or rear surface of the substrate. The conductive elements are preferably formed by plating and may or may not conform to the surface of the substrate.
    Type: Grant
    Filed: April 2, 2014
    Date of Patent: April 28, 2015
    Assignee: Tessera, Inc.
    Inventors: Vage Oganesian, Belgacem Haba, Ilyas Mohammed, Craig Mitchell, Piyush Savalia
  • Patent number: 9006887
    Abstract: Methods of forming a microelectronic packaging structure are described. Those methods may include forming a solder paste comprising a sacrificial polymer on a substrate, curing the solder paste below a reflow temperature of the solder to form a solid composite hybrid bump on the conductive pads, forming a molding compound around the solid composite hybrid bump, and reflowing the hybrid bump, wherein the sacrificial polymer is substantially decomposed.
    Type: Grant
    Filed: March 4, 2009
    Date of Patent: April 14, 2015
    Assignee: Intel Corporation
    Inventors: Rajasekaran Swaminathan, Leonel Arana, Yoshihiro Tomita, Yosuke Kanaoka
  • Patent number: 8937008
    Abstract: A system and process for forming a ball grid array on a substrate includes defining a plurality of openings in a resist layer on the substrate, and forming a plurality of openings in the resist layer, each positioned over a contact pad of the substrate. Flux is then deposited in the openings, and solder balls are positioned in each opening with the flux. Solder bumps are formed by reflowing the solder balls in the respective openings. The resist layer is then removed, leaving an array of solder bumps on the substrate. The flux can be deposited by depositing a layer of flux, then removing the flux, except a portion that remains in each opening. Solder balls can be positioned by moving a ball feeder across the resist layer and dropping a solder ball each time an aperture in the ball feeder aligns with an opening in the resist layer.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: January 20, 2015
    Assignee: STMicroelectronics Pte Ltd.
    Inventor: Yonggang Jin
  • Patent number: 8901734
    Abstract: An interconnect pad is formed over a first substrate. A photoresist layer is formed over the first substrate and interconnect pad. A portion of the photoresist layer is removed to form a channel and expose a perimeter of the interconnect pad while leaving the photoresist layer covering a central area of the interconnect pad. A first conductive material is deposited in the channel of the photoresist layer to form a column of conductive material. The remainder of the photoresist layer is removed. A masking layer is formed around the column of conductive material while exposing the interconnect pad within the column of conductive material. A second conductive material is deposited over the first conductive layer. The second conductive material extends above the column of conductive material. The masking layer is removed. The second conductive material is reflowed to form a column interconnect structure over the semiconductor device.
    Type: Grant
    Filed: April 3, 2012
    Date of Patent: December 2, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: SungWon Cho, TaeWoo Kang
  • Patent number: 8766449
    Abstract: Disclosed is a variable interconnect geometry formed on a substrate that allows for increased electrical performance of the interconnects without compromising mechanical reliability. The compliance of the interconnects varies from the center of the substrate to edges of the substrate. The variation in compliance can either be step-wise or continuous. Exemplary low-compliance interconnects include columnar interconnects and exemplary high-compliance interconnects include helix interconnects. A cost-effective implementation using batch fabrication of the interconnects at a wafer level through sequential lithography and electroplating processes may be employed.
    Type: Grant
    Filed: May 24, 2007
    Date of Patent: July 1, 2014
    Assignee: Georgia Tech Research Corporation
    Inventors: Suresh K. Sitaraman, Karan Kacker, Thomas Sokol
  • Patent number: 8735276
    Abstract: Provided are semiconductor packages and methods of manufacturing the semiconductor package. The semiconductor packages may include a substrate including a chip pad, a redistributed line which is electrically connected to the chip pad and includes an opening. The semiconductor packages may also include an external terminal connection portion, and an external terminal connection pad which is disposed at an opening and electrically connected to the redistributed line. The present general inventive concept can solve the problem where an ingredient of gold included in a redistributed line may be prevented from being diffused into an adjacent bump pad to form a void or an undesired intermetallic compound. In a chip on chip structure, a plurality of bumps of a lower chip are connected to an upper chip to improve reliability, diversity and functionality of the chip on chip structure.
    Type: Grant
    Filed: February 3, 2012
    Date of Patent: May 27, 2014
    Assignee: SAMSUNG Electronics Co., Ltd.
    Inventors: Hyun-Soo Chung, Jae-Shin Cho, Dong-Ho Lee, Dong-Hyeon Jang, Seong-Deok Hwang, Seung-Duk Baek
  • Patent number: 8728931
    Abstract: A method for forming an interconnect structure includes forming a recess in a dielectric layer of a substrate. An adhesion barrier layer is formed to line the recess. A first stress level is present across a first interface between the adhesion barrier layer and the dielectric layer. A stress-reducing barrier layer is formed over the adhesion barrier layer. The stress-reducing barrier layer reduces the first stress level to provide a second stress level, less than the first stress level, across a second interface between the adhesion barrier layer, the stress-reducing barrier layer, and the dielectric layer. The recess is filled with a fill layer.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: May 20, 2014
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Vivian W. Ryan, Xunyuan Zhang, Paul R. Besser
  • Patent number: 8722534
    Abstract: A method for forming an interconnect structure includes forming a recess in a dielectric layer of a substrate, forming a first transition metal layer in the recess on corner portions of the recess, and forming a second transition metal layer in the recess over the first transition metal layer to line the recess. The method further includes filling the recess with a fill layer and annealing the substrate so that the first transition metal layer and the second transition metal layer form an alloy portion proximate the corner portions during the annealing, the alloy portion having a reduced wettability for a material of the fill layer than the second transition metal. Additionally, the method includes polishing the substrate to remove portions of the fill layer extending above the recess.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: May 13, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Xunyuan Zhang, Hoon Kim, Vivian W. Ryan
  • Patent number: 8723318
    Abstract: A packaged microelectronic element includes a microelectronic element having a front surface and a plurality of first solid metal posts extending away from the front surface. A substrate has a major surface and a plurality of conductive elements exposed at the major surface and joined to the first solid metal posts. In particular examples, the conductive elements can be bond pads or can be second posts having top surfaces and edge surfaces extending at substantial angles away therefrom. Each first solid metal post includes a base region adjacent the microelectronic element and a tip region remote from the microelectronic element, the base region and tip region having respective concave circumferential surfaces. Each first solid metal post has a horizontal dimension which is a first function of vertical location in the base region and which is a second function of vertical location in the tip region.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: May 13, 2014
    Assignee: Tessera, Inc.
    Inventor: Belgacem Haba
  • Patent number: 8723319
    Abstract: A BGA package structure and a method for fabricating the same, wherein the BGA package structure comprises: a substrate having a first surface used to carry a chip and a second surface opposite to the first surface, wherein the substrate is divided into several regions according to different distances from a central point of the substrate; a plurality of contact bonding pads on the second surface electrically connected with the chip; and a plurality of bumps respectively attached to each of the contact bonding pads, wherein the contact bonding pads and bumps in a region which is closest to the central point are the smallest, while the contact bonding pads and bumps in a region which is farthest to the central point are the biggest. Therefore the situation that the bumps at the edge are liable to peel off may improved.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: May 13, 2014
    Assignee: Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: TsingChow Wang
  • Publication number: 20140110836
    Abstract: Packaging devices, methods of manufacture thereof, and packaging methods for semiconductor devices are disclosed. In one embodiment, a packaging device includes a substrate including an integrated circuit die mounting region. An underfill material flow prevention feature is disposed around the integrated circuit die mounting region.
    Type: Application
    Filed: October 19, 2012
    Publication date: April 24, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Taiwan Semiconductor Manufacturing Company, Ltd.
  • Publication number: 20140110839
    Abstract: A structure comprises a first semiconductor chip with a first metal bump and a second semiconductor chip with a second metal bump. The structure further comprises a solder joint structure electrically connecting the first semiconductor chip and the second semiconductor chip, wherein the solder joint structure comprises an intermetallic compound region between the first metal bump and the second metal bump, wherein the intermetallic compound region is with a first height dimension and a surrounding portion formed along exterior walls of the first metal bump and the second metal bump, wherein the surrounding portion is with a second height dimension, and wherein the second height dimension is greater than the first height dimension.
    Type: Application
    Filed: October 22, 2012
    Publication date: April 24, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Taiwan Semiconductor Manufacturing Company, Ltd.
  • Publication number: 20140103532
    Abstract: An electronic apparatus includes a semiconductor substrate, a device structure supported by the semiconductor substrate, and a guard ring surrounding the device structure. The guard ring includes a plurality of conductive structures spaced apart from one another, supported by the semiconductor substrate, and coupled to a voltage source to establish an operating voltage for the guard ring.
    Type: Application
    Filed: October 12, 2012
    Publication date: April 17, 2014
    Inventors: Jenn Hwa Huang, Jose L. Suarez, Yun Wei
  • Patent number: 8680677
    Abstract: Electrical connection in an integrated circuit arrangement is facilitated with carbon nanotubes. According to various example embodiments, a carbon nanotube material (120, 135) is associated with another material (130, 125) such as a metal. The carbon nanotube material facilitates the electrical connection between different circuit components.
    Type: Grant
    Filed: November 4, 2005
    Date of Patent: March 25, 2014
    Assignee: NXP B.V.
    Inventor: Christopher Wyland
  • Publication number: 20140077383
    Abstract: A structure and method of making an offset-trench crackstop, which forms an air gap in a passivation layer that is adjacent to a passivated top metal layer of a metal crackstop in an integrated circuit (IC) die. The offset-trench crackstop may expose a portion of a topmost dielectric layer in the crackstop region, not expose a topmost patterned metal layer of the metal crackstop, and may be interposed between the metal crackstop and an active device region. Alternatively, the offset-trench crackstop may expose a portion of the topmost dielectric layer, which separates an outermost metal layer and an innermost metal layer of the metal crackstop, and does not expose any of the topmost patterned metal layer of the metal crackstop, where the innermost metal layer of the metal crackstop is interposed between the offset-trench crackstop in the crackstop region and the active device region of the IC die.
    Type: Application
    Filed: September 14, 2012
    Publication date: March 20, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, Christopher D. Muzzy, Wolfgang Sauter
  • Publication number: 20140054764
    Abstract: A semiconductor package includes a semiconductor substrate, a contact pad overlying the semiconductor substrate, an interconnect layer overlying the contact pad, a passivation layer formed between the contact pad and the interconnect layer, a bump overlying the interconnect layer, and a protection layer overlying the interconnect layer and the passivation layer and covering a lower portion of the bump. The protection layer includes a curved surface region.
    Type: Application
    Filed: August 24, 2012
    Publication date: February 27, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wen-Hsiung Lu, Ming-Da Cheng, Yi-Wen Wu, Yu-Peng Tsai, Chia-Wei Tu, Chung-Shi Liu
  • Patent number: 8653657
    Abstract: There are provided a semiconductor device capable of accurately determining whether a semiconductor chip is bonded to a solid-state device such as the other semiconductor chip parallelly with each other, a semiconductor chip used for the semiconductor device, and a method of manufacturing the semiconductor chip. The semiconductor chip includes a functional bump projected with a first projection amount from the surface of the semiconductor chip and electrically connecting the semiconductor chip to the solid-state device, and a connection confirmation bump projected with a second projection amount, which is smaller than the first projection amount, from the surface of the semiconductor chip and used for confirming the state of the electrical connection by the functional bump.
    Type: Grant
    Filed: August 18, 2006
    Date of Patent: February 18, 2014
    Assignee: Rohm Co., Ltd.
    Inventors: Osamu Miyata, Tadahiro Morifuji
  • Publication number: 20140035128
    Abstract: Among other things, a semiconductor seal ring and method for forming the same are provided. The semiconductor seal ring comprises a plurality of dielectric layers formed over a semiconductor substrate upon which a semiconductor device is formed. A plurality of conductive layers is arranged among at least some of the plurality of dielectric layers. An upper conductive layer is formed over the plurality of dielectric layers. An upper passivation layer is formed over the upper conductive layer to isolate the upper conductive layer from conductive debris resulting from a die saw process along a die saw cut line. In an example, a first columnar region comprising a first portion of the conductive layers is electrically isolated from the semiconductor device because the first columnar region is disposed relatively close to the die saw cut line and thus can be exposed to conductive debris which can cause undesired short circuits.
    Type: Application
    Filed: October 25, 2012
    Publication date: February 6, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chien-Chih Chou, Huei-Ru Liou, Kong-Beng Thei
  • Patent number: 8642446
    Abstract: A semiconductor wafer contains a plurality of semiconductor die separated by a saw street. A contact pad is formed over an active surface of the semiconductor die. A protective pattern is formed over the active surface of the semiconductor die between the contact pad and saw street of the semiconductor die. The protective pattern includes a segmented metal layer or plurality of parallel segmented metal layers. An insulating layer is formed over the active surface, contact pad, and protective pattern. A portion of the insulating layer is removed to expose the contact pad. The protective pattern reduces erosion of the insulating layer between the contact pad and saw street of the semiconductor die. The protective pattern can be angled at corners of the semiconductor die or follow a contour of the contact pad. The protective pattern can be formed at corners of the semiconductor die.
    Type: Grant
    Filed: September 27, 2010
    Date of Patent: February 4, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Xia Feng, Kang Chen, Jianmin Fang
  • Publication number: 20140027902
    Abstract: Generally, the subject matter disclosed herein relates to repairing anomalous stiff pillar bumps that may be detected above a metallization system of a semiconductor chip or wafer. One illustrative method disclosed herein includes, among other things, forming a pillar bump above a metallization system of a semiconductor chip, and forming a plurality of notches in the pillar bump, wherein the plurality of notches are adapted to adjust a flexibility of the pillar bump when the pillar bump is exposed to a lateral force.
    Type: Application
    Filed: July 27, 2012
    Publication date: January 30, 2014
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Vivian W. Ryan, Holm Geisler, Dirk Breuer
  • Publication number: 20140021606
    Abstract: A solder structure for joining an IC chip to a package substrate, and method of forming the same are disclosed. In an embodiment, a structure is formed which includes a wafer having a plurality of solder structures disposed above the wafer. A ball limiting metallurgy (BLM) layer disposed beneath each of the solder structures, above the wafer. At least one of the plurality of solder structures has a first composition, and at least another of the plurality of solder structures has a second composition.
    Type: Application
    Filed: July 19, 2012
    Publication date: January 23, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Charles L. Arvin, Wolfgang Sauter, Jennifer D. Schuler
  • Publication number: 20130320524
    Abstract: A system and method for preventing cracks in a passivation layer is provided. In an embodiment a contact pad has a first diameter and an opening through the passivation layer has a second diameter, wherein the first diameter is greater than the second diameter by a first distance of about 10 ?m. In another embodiment, an underbump metallization is formed through the opening, and the underbump metallization has a third diameter that is greater than the first diameter by a second distance of about 5 ?m. In yet another embodiment, a sum of the first distance and the second distance is greater than about 15 ?m.
    Type: Application
    Filed: November 2, 2012
    Publication date: December 5, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yao-Chun Chuang, Chita Chuang, Hao-Juin Liu, Chen-Cheng Kuo, Chen-Shien Chen
  • Publication number: 20130313702
    Abstract: A semiconductor device comprises a substrate, a word line, an insulation material, and an etch stop material. The substrate comprises a pillar that may comprise an active area. The word line is formed in the substrate. The insulation material is formed on the word line. The etch stop material is formed on the insulating material and around the pillar.
    Type: Application
    Filed: May 23, 2012
    Publication date: November 28, 2013
    Inventors: Guangjun YANG, Russell Benson
  • Patent number: 8586469
    Abstract: A method of patterning a metal layer is disclosed. The method includes providing a substrate and forming a material layer over the substrate. The method includes forming a second material layer over the first material layer. The method includes performing a first patterning process to the second material layer to form a trench in the second material layer. The first patterning process defines a width size of the trench, the width size being measured in a first direction. The method includes performing a second patterning process to the trench to transform the trench. The second patterning process defines a length size of the transformed trench. The length size is measured in a second direction different from the first direction. The method also includes filling the transformed trench with a conductive material.
    Type: Grant
    Filed: July 28, 2010
    Date of Patent: November 19, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Chen-Hao Yeh
  • Publication number: 20130285246
    Abstract: A device and method for fabricating a device is disclosed. An exemplary device includes a first conductive layer disposed over a substrate, the first conductive layer including a first plurality of conductive lines extending in a first direction. The device further includes a second conductive layer disposed over the first conductive layer, the second conductive layer including a second plurality of conductive lines extending in a second direction. The device further includes a self-aligned interconnect formed at an interface where a first conductive line of the first plurality of conductive lines is in electrical contact with a first conductive line of the second plurality of conductive lines. The device further includes a blocking portion interposed between a second conductive line of the first plurality of conductive lines and a second conductive line of the second plurality of conductive lines.
    Type: Application
    Filed: April 27, 2012
    Publication date: October 31, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Ming Chang, Ken-Hsien Hsieh, Tsong-Hua Ou, Ru-Gun Liu, Fang-Yu Fan, Yuan-Te Hou
  • Publication number: 20130277830
    Abstract: Disclosed herein is a bump-on-trace interconnect with a wetted trace sidewall and a method for fabricating the same. A first substrate having conductive bump with solder applied is mounted to a second substrate with a trace disposed thereon by reflowing the solder on the bump so that the solder wets at least one sidewall of the trace, with the solder optionally wetting between at least half and all of the height of the trace sidewall. A plurality of traces and bumps may also be disposed on the first substrate and second substrate with a bump pitch of less than about 100 ?m, and volume of solder for application to the bump calculated based on at least one of a joint gap distance, desired solder joint width, predetermined solder joint separation, bump geometry, trace geometry, minimum trace sidewall wetting region height and trace separation distance.
    Type: Application
    Filed: October 17, 2012
    Publication date: October 24, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Taiwan Semiconductor Manufacturing Company, Ltd.
  • Publication number: 20130256873
    Abstract: A system, method, and computer program product are provided for preparing a substrate post. In use, a first solder mask is applied to a substrate. Additionally, a post is affixed to each of one or more pads of the substrate. Further, a second solder mask is applied to the substrate.
    Type: Application
    Filed: April 3, 2012
    Publication date: October 3, 2013
    Applicant: NVIDIA CORPORATION
    Inventors: Leilei Zhang, Abraham F. Yee, Shantanu Kalchuri, Zuhair Bokharey
  • Publication number: 20130249082
    Abstract: A conductive bump structure is formed on a substrate having a plurality of bonding pads and a first insulating layer thereon. The first insulating layer has a plurality of openings formed therein for exposing the bonding pads and a conductive post is formed on the bonding pads exposed through the openings. Therein, a gap is formed between the conductive post and the wall of the opening such that no contact occurs between the conductive post and the first insulating layer, thereby preventing delamination of the conductive bump structure caused by stresses concentrating on an interface of different materials as in the prior art.
    Type: Application
    Filed: October 3, 2012
    Publication date: September 26, 2013
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Feng-Lung Chien, Yi-Hung Lin, Yi-Hsin Chen
  • Publication number: 20130249081
    Abstract: A method for manufacturing fine-pitch bumps comprises providing a silicon substrate; forming a titanium-containing metal layer having a plurality of first zones and a plurality of second zones on the silicon substrate; forming a photoresist layer on the titanium-containing metal layer; patterning the photoresist layer; forming a plurality of copper bumps having a plurality of first top surfaces and a plurality of first ring surfaces; heating the photoresist layer to form a plurality of body portions and removable portions; etching the photoresist layer; forming a plurality of bump protection layers on the titanium-containing metal layer, the first top surface and the first ring surface, each of the bump protection layers comprises a bump coverage portion; plating a plurality of gold layers at the bump coverage portion; eventually, removing the second zones to enable each of the first zones to form an under bump metallurgy layer.
    Type: Application
    Filed: March 22, 2012
    Publication date: September 26, 2013
    Applicant: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Cheng-Hung Shih, Yung-Wei Hsieh, Shu-Chen Lin, Cheng-Fan Lin, Hua-An Dai
  • Publication number: 20130249105
    Abstract: A semiconductor device has a semiconductor die and first insulating layer formed over the semiconductor die. A plurality of first micro-vias can be formed in the first insulating layer. A conductive layer is formed in the first micro-openings and over the first insulating layer. A second insulating layer is formed over the first insulating layer and conductive layer. A portion of the second insulating layer is removed to expose the conductive layer and form a plurality of second micro-openings in the second insulating layer over the conductive layer. The second micro-openings can be micro-vias, micro-via ring, or micro-via slots. Removing the portion of the second insulating layer leaves an island of the second insulating layer over the conductive layer. A bump is formed over the conductive layer. A third insulating layer is formed in the second micro-openings over the bump. The second micro-openings provide stress relief.
    Type: Application
    Filed: March 21, 2012
    Publication date: September 26, 2013
    Applicant: STATS CHIPPAC, LTD.
    Inventors: Yaojian Lin, Kang Chen
  • Publication number: 20130234319
    Abstract: Some embodiments include a planarization method. A liner is formed across a semiconductor substrate and along posts that extending upwardly from the substrate. Organic fill material is formed over the liner and between the posts. A planarized surface is formed which extends across the posts and across one or both of the liner and the fill material. Some embodiments include a semiconductor construction containing a semiconductor die. Electrically conductive posts extend through the die. The posts have upper surfaces above a backside surface of the die, and have sidewall surfaces extending between the backside surface and the upper surfaces. A liner is across the backside surface of the die and along the sidewall surfaces of the posts. Electrically conductive caps are over the upper surfaces of the posts, and have rims along the liner adjacent the sidewall surfaces of the posts.
    Type: Application
    Filed: March 12, 2012
    Publication date: September 12, 2013
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Jaspreet S. Gandhi
  • Publication number: 20130234315
    Abstract: Structures and methods for detecting solder wetting of pedestal sidewalls. The structure includes a semiconductor wafer having an array of integrated circuit chips, each of the integrated circuit chips having an array of chip pedestals having respective chip solder columns on top of the chip pedestals, the pedestals spaced apart a first distance in a first direction and a spaced apart second distance in second direction perpendicular to the first direction; and at least one monitor structure disposed in different regions of the wafer from the integrated circuit chips, the monitor structure comprising at least a first pedestal and a first solder column on a top surface of the first pedestal and a second pedestal and a second solder column on a top surface of the second pedestal, the first and the second pedestals spaced apart a third distance, the third distance less than the first and the second distances.
    Type: Application
    Filed: March 8, 2012
    Publication date: September 12, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, Christopher D. Muzzy, Wolfgang Sauter, Timothy D. Sullivan
  • Publication number: 20130234316
    Abstract: The invention provides a semiconductor chip structure having at least one aluminum pad structure and a polyimide buffering layer under the aluminum pad structure, wherein the polyimide buffering layer is self-aligned to the aluminum pad structure, and a method of forming the same. The method includes forming a polyimide buffering layer on a substrate, forming an aluminum pad structure on the buffering layer, and, using the aluminum pad structure as a mask, etching the substrate to remove the polyimide buffering layer from the substrate everywhere except under the aluminum pad structure.
    Type: Application
    Filed: March 9, 2012
    Publication date: September 12, 2013
    Applicant: International Business Machines Corporation
    Inventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, Christopher D. Muzzy, Wolfgang Sauter, Timothy D. Sullivan
  • Patent number: 8518816
    Abstract: A method for making electrical interconnections of carbon nanotubes, including a) depositing an ionic liquid including nanoparticles of at least one suspended electrically conducting material, covering at least one surface of an element configured to be used as a support for carbon nanotubes, b) forming a deposit of the nanoparticles at least against the surface of the element, c) removing the remaining ionic liquid, d) growing carbon nanotubes from the deposited nanoparticles, and further including between the c) removing the remaining ionic liquid and the d) growing carbon nanotubes, passivating the deposited nanoparticles not found against the surface of the element.
    Type: Grant
    Filed: March 24, 2010
    Date of Patent: August 27, 2013
    Assignees: Commissariat a l'Energie Atomique et aux Energies Alternatives, Centre National de la Recherche Scientifique
    Inventors: Paul-Henri Haumesser, Jean-Marie Basset, Paul Campbell, Simon Deleonibus, Thibaut Gutel, Gilles Marchand, Catherine Santini
  • Publication number: 20130214424
    Abstract: The invention provides a structure and a manufacturing method thereof for reducing a stress of a chip. The structure comprises a through-silicon via (TSV), a plurality of reinforcing base and a plurality of base bodies. The reinforcing bases are disposed near and around the TSV. The base bodies are disposed near and around the TSV, and the base is disposed on a side of the reinforcing base. The reinforcing base or the base body does not connected with the TSV.
    Type: Application
    Filed: June 27, 2012
    Publication date: August 22, 2013
    Inventors: Nien-Yu TSAI, Hao YU, Jui-Hung CHIEN, Shih-Chien CHANG
  • Publication number: 20130207258
    Abstract: A semiconductor device including a dielectric layer formed on the surface of a post-passivation interconnect (PPI) structures. A polymer layer is formed on the dielectric layer and patterned with an opening to expose a portion of the dielectric layer. The exposed portion of the dielectric layer is then removed to expose a portion of the PPI structure. A solder bump is then formed over and electrically connected to the first portion of the PPI structure.
    Type: Application
    Filed: February 10, 2012
    Publication date: August 15, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsien-Wei CHEN, Yi-Wen WU
  • Patent number: 8501615
    Abstract: A system and method for forming metal bumps is provided. An embodiment comprises attaching conductive material to a carrier medium and then contacting the conductive material to conductive regions of a substrate. Portions of the conductive material are then bonded to the conductive regions using a bonding process to form conductive caps on the conductive regions, and residual conductive material and the carrier medium are removed. A reflow process is used to reflow the conductive caps into conductive bumps.
    Type: Grant
    Filed: June 15, 2011
    Date of Patent: August 6, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Da Cheng, Chih-Wei Lin, Hsiu-Jen Lin, Tzong-Hann Yang, Wen-Hsiung Lu, Zheng-Yi Lim, Yi-Wen Wu, Chung-Shi Liu
  • Publication number: 20130193570
    Abstract: A bumping process includes providing a silicon substrate; forming a titanium-containing metal layer on silicon substrate, the titanium-containing metal layer comprises a plurality of first areas and a plurality of second areas; forming a first photoresist layer on titanium-containing metal layer; patterning the first photoresist layer to form a plurality of first opening slots; forming a plurality of copper bumps within first opening slots, said copper bump comprises a first top surface and a first ring surface; removing the first photoresist layer; forming a second photoresist layer on titanium-containing metal layer; patterning the second photoresist layer to form a plurality of second opening slots; forming a plurality of bump isolation layers at spaces, the first top surfaces and the first ring surfaces; forming a plurality of connective layers on bump isolation layers; removing the second photoresist layer, removing the second areas to form an under bump metallurgy layer.
    Type: Application
    Filed: February 1, 2012
    Publication date: August 1, 2013
    Applicant: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Chih-Ming Kuo, Yie-Chuan Chiu, Lung-Hua Ho
  • Patent number: 8486824
    Abstract: A protection layer is coated or otherwise formed over the interconnect structure. The interconnect structure includes a metal line (such as top and bottom metal layers connected by a metal via) and a low-K material. The protection layer includes a vertically aligned dielectric or other material dispersed with carbon nanotubes. The protection layer could include one or multiple layers of carbon nanotubes, and the carbon nanotubes could have any suitable dispersion, alignment, and pattern in each layer of the protection layer. Among other things, the carbon nanotubes help to reduce or prevent damage to the interconnect structure, such as by reducing or preventing the collapse of the low-K material or delamination between the metal line and the low-K material.
    Type: Grant
    Filed: July 10, 2012
    Date of Patent: July 16, 2013
    Assignees: STMicroelectronics Asia Pacific PTE., Ltd., Nanyang Technological University
    Inventors: Tong Yan Tee, Xueren Zhang, Shanzhong Wang, Valeriy Nosik, Jijie Zhou, Sridhar Idapalapati, Subodh Mhaisalkar, Zhi Yuan Shane Loo
  • Publication number: 20130171816
    Abstract: A system and process for forming a ball grid array on a substrate includes defining a plurality of openings in a resist layer on the substrate, and forming a plurality of openings in the resist layer, each positioned over a contact pad of the substrate. Flux is then deposited in the openings, and solder balls are positioned in each opening with the flux. Solder bumps are formed by reflowing the solder balls in the respective openings. The resist layer is then removed, leaving an array of solder bumps on the substrate. The flux can be deposited by depositing a layer of flux, then removing the flux, except a portion that remains in each opening. Solder balls can be positioned by moving a ball feeder across the resist layer and dropping a solder ball each time an aperture in the ball feeder aligns with an opening in the resist layer.
    Type: Application
    Filed: December 29, 2011
    Publication date: July 4, 2013
    Applicant: STMICROELECTRONICS PTE LTD.
    Inventor: Yonggang Jin
  • Patent number: 8455298
    Abstract: A method for fabricating a memory device includes depositing a phase-change and/or a resistive change material. The memory device is formed photolithographically using sixteen or fewer masks.
    Type: Grant
    Filed: August 18, 2009
    Date of Patent: June 4, 2013
    Assignee: Contour Semiconductor, Inc.
    Inventors: Mac D. Apodaca, Ailian Zhao, Jenn C. Chow, Thomas Brown, Lisa Ceder
  • Publication number: 20130134581
    Abstract: The mechanisms for forming bump structures reduce variation of standoffs between chips and package substrates. By planarizing the solder layer on bump structures on chips and/or substrates after plating, the heights of bump structures are controlled to minimize variation due to within die and within wafer locations, pattern density, die size, and process variation. As a result, the standoffs between chips and substrates are controlled to be more uniform. Consequently, underfill quality is improved.
    Type: Application
    Filed: November 30, 2011
    Publication date: May 30, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jing-Cheng LIN, Po-Hao TSAI
  • Publication number: 20130134580
    Abstract: A semiconductor device has a semiconductor wafer with a plurality of semiconductor die. A first conductive layer is formed over a surface of the wafer. A first insulating layer is formed over the surface of the wafer and first conductive layer. A second conductive layer has first and second segments formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and second conductive layer. A UBM layer is formed over the second insulating layer and the first segment of the second conductive layer. A first bump is formed over the UBM layer. The first bump is electrically connected to the second segment and electrically isolated from the first segment of the second conductive layer. A second bump is formed over the surface of the wafer and electrically connected to the first segment of the second conductive layer.
    Type: Application
    Filed: November 30, 2011
    Publication date: May 30, 2013
    Applicant: STATS ChipPAC, Ltd.
    Inventors: Xusheng Bao, Ma Phoo Pwint Hlaing, Jian Zuo
  • Publication number: 20130127045
    Abstract: The mechanisms of forming a copper post structures described enable formation of copper post structures on a flat conductive surface. In addition, the copper post structures are supported by a molding layer with a Young's modulus (or a harder material) higher than polyimide. The copper post structures formed greatly reduce the risk of cracking of passivation layer and delamination of at the dielectric interface surrounding the copper post structures.
    Type: Application
    Filed: February 27, 2012
    Publication date: May 23, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Shu LIN, Han-Ping PU, Ming-Da CHENG, Chang-Chia HUANG, Hao-Juin LIU
  • Publication number: 20130127047
    Abstract: A conductive structure for a semiconductor chip and a method for forming the conductive structure are provided. The semiconductor chip comprises a semiconductor substrate, a pad, a passivation layer and a patterned insulating layer. The patterned insulating layer is disposed on the passivation layer and partially and directly covers the first opening of the pad to expose a second opening. The conductive structure comprises an under bump metal (UBM) layer and a conductive bump. The UBM layer is disposed in the second opening defined by the patterned insulating layer and is electrically connected to the pad. The conductive bump is disposed on the UBM layer and is electrically connected to the UBM layer. The upper surface of the conductive bump is greater than the upper surface of the patterned insulating layer, while the portion of the conductive bump disposed in the second opening is covered by the UBM layer.
    Type: Application
    Filed: October 18, 2012
    Publication date: May 23, 2013
    Applicant: CHIPMOS TECHNOLOGIES INC.
    Inventor: CHIPMOS TECHNOLOGIES INC.
  • Patent number: 8440557
    Abstract: The present invention is directed to a method for manufacturing a semiconductor device by forming an ultraviolet radiation absorbing film of a silicon-rich film above a semiconductor substrate, measuring an extinction coefficient of the ultraviolet radiation absorbing film of a silicon-rich film for ultraviolet radiation, and etching the ultraviolet radiation absorbing film of a silicon-rich film under an etching condition using an oxygen gas flow rate corresponding to the extinction coefficient.
    Type: Grant
    Filed: July 20, 2010
    Date of Patent: May 14, 2013
    Assignee: Spansion LLC
    Inventors: Seiji Yokoyama, Yuuichirou Sekimoto, Sinichi Imada
  • Publication number: 20130113095
    Abstract: A packaging substrate includes a base body having at least a conductive pad on a surface thereof, a dielectric layer formed on the surface of the base body and having at least a first opening for exposing the conductive pad and at least a second opening formed at a periphery of the first opening, and a metal layer formed on the conductive pad and the dielectric layer and extending to a sidewall of the second opening, thereby effectively eliminating side-etching of the metal layer under a solder bump.
    Type: Application
    Filed: May 29, 2012
    Publication date: May 9, 2013
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chien-Lung Chuang, Po-Yi Wu, Meng-Tsung Lee, Yih-Jenn Jiang