Abstract: A semiconductor package includes a redistribution substrate having a dielectric layer and a wiring pattern in the dielectric layer, the wiring pattern including a line part that extends horizontally, and a via part connected to the line part, the via part having a width less than a width of the line part, a passivation layer on a top surface of the redistribution substrate, the passivation layer including a material different from a material of the dielectric layer, a conductive pillar that penetrates the passivation layer, the conductive pillar being connected to the via part, and a connection terminal on a top surface of the conductive pillar, a distance between the top surface of the conductive pillar and a top surface of the passivation layer being greater than a thickness of the passivation layer.

Abstract: A method for manufacturing a semiconductor device. A photolithographic coating, including a first film, a photolithographic film, and a second film, is formed on the to-be-connected structure. Refractive indexes of the first film and the second film are smaller than 1. The photolithographic coating is exposed to a light having a first wavelength, to image the to-be-connected structure to a first region of the photolithographic film. The photolithographic coating is exposed to a light having a second wavelength through a mask, to image the mask to a second region of the photolithographic film. A region in which the first region and the second region overlap serves as a connection region corresponding to the to-be-connected structure, and thereby self-alignment between a layer of the to-be-connected structure and a layer where a contact hole is arranged is implemented.

Abstract: A method of forming a sensor, such as a glass electrochemical sensor, is described. In some examples, the method may include forming a plurality of apertures in a glass substrate; forming a sensor body comprising the glass substrate and at least one glass sensor component, wherein one or more apertures of the glass substrate are aligned with the at least one glass sensor component to form an outer contact aperture; filling the outer contact aperture in the sensor body with a first conducting material to form an outer contact through glass via (TGV); and forming an electrode on the glass substrate adjacent at least one of the apertures of the plurality of apertures.

Abstract: Self-aligned patterning with colored blocking and resulting structures are described. In an example, an integrated circuit structure includes an inter-layer dielectric (ILD) layer above a substrate, and a hardmask layer on the ILD layer. A plurality of conductive interconnect lines is in and spaced apart by the ILD layer and the hardmask layer. The plurality of conductive interconnect lines includes a first interconnect line having a first width. A second interconnect line is immediately adjacent the first interconnect line by a first distance, the second interconnect line having the first width. A third interconnect line is immediately adjacent the second interconnect line by the first distance, the third interconnect line having the first width. A fourth interconnect line is immediately adjacent the third interconnect line by a second distance greater than the first distance, the fourth interconnect line having a second width greater than the first width.

Abstract: A semiconductor structure includes a substrate with a conductive structure thereon, a first dielectric layer, a conductive feature and a second dielectric layer. The substrate includes a conductive feature. The conductive feature is formed in the first dielectric layer, is electrically connected to the conductive feature. The second dielectric layer is formed on the first dielectric layer and is disposed adjacent to the conductive feature. The first dielectric layer and the second dielectric layer are made of different materials.

Abstract: A method comprises forming a first conductive line and a second conductive line in a first dielectric layer over a substrate, each having a planar top surface, applying an etch-back process to the first dielectric layer until a dielectric portion between the first conductive line and the second conductive line has been removed, and the first conductive line and the second conductive line have respective cross sectional shapes including a rounded surface and two rounded corners and depositing a second dielectric layer over the substrate, while leaving a first air gap between the first conductive line and the second conductive line.

Abstract: An electrical device that includes a substrate; a 3D capacitor including a capacitor dielectric region of a dielectric material, a capacitor electrode region of a conductive material, the capacitor dielectric region and the capacitor electrode region being arranged at least partially inside a cavity extending in the substrate from a top face of the substrate; and a surrounding through opening in the substrate and which surrounds a surrounded substrate region, the 3D capacitor being outside of the surrounded substrate region, the surrounding through opening extending from the top face to a bottom face of the substrate, wherein inside the surrounding through opening a surrounding dielectric region of the dielectric material and a surrounding conductive region of the conductive material are arranged.

Abstract: Methods and devices of having an enclosure structure formed in a multi-layer interconnect and a through-silicon-via (TSV) extending through the enclosure structure. In some implementations, a protection layer is formed between the enclosure structure and the TSV.

Abstract: The present disclosure relates to a field of chip technology, and discloses a three-phase inverter power chip and a preparation method therefor. The preparation method includes: forming active areas on a substrate and an isolation area located outside the active areas; forming a source electrode, a drain electrode and a gate electrode of a transistor in each active area; forming a first bond pad, second bond pads, third bond pads and fourth bond pads in the isolation area; the source electrode, the drain electrode and the gate electrode of the chip being extended to the first bond pad, the second bond pads, the third bond pads or the fourth bond pads corresponding thereto; and electrically connecting the source electrode, the drain electrode and the gate electrode of the transistor to the first bond pad, the second bond pads, the third bond pads or the fourth bond pads corresponding thereto.

Abstract: A method of forming a sensor, such as a glass electrochemical sensor, is described. In some examples, the method may include forming a plurality of apertures in a glass substrate; forming a sensor body comprising the glass substrate and at least one glass sensor component, wherein one or more apertures of the glass substrate are aligned with the at least one glass sensor component to form an outer contact aperture; filling the outer contact aperture in the sensor body with a first conducting material to form an outer contact through glass via (TGV); and forming an electrode on the glass substrate adjacent at least one of the apertures of the plurality of apertures.

Abstract: A semiconductor structure and a method for forming the same are disclosed. The method includes the steps of forming a first dielectric layer on a substrate, forming a plurality of first interconnecting structures in the first dielectric layer, forming at least a trench in the first dielectric layer and between the first interconnecting structures, performing a sputtering deposition process to form a second dielectric layer on the first dielectric layer, wherein the second dielectric layer at least partially seals an air gap in the trench, and forming a third dielectric layer on the second dielectric layer.

Abstract: A method of manufacturing a display device may include sequentially forming a first conductive layer, a second conductive layer including copper (Cu), a third conductive layer, and a fourth conductive layer on a substrate, patterning the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer together to form a conductive pattern including a first layer, a second layer, a third layer, and a fourth layer sequentially on the substrate, removing the fourth layer of the conductive pattern, forming a protective layer covering at least a sidewall of the conductive layer on the substrate, and forming a display element on the protective layer.

Abstract: An integrated circuit (IC) chip includes a via contact plug extending inside a through hole passing through a substrate and a device layer, a via contact liner surrounding the via contact plug, a connection pad liner extending along a bottom surface of the substrate, a dummy bump structure integrally connected to the via contact plug, and a bump structure connected to the connection pad liner. A method of manufacturing an IC chip includes forming an under bump metallurgy (UBM) layer inside and outside the through hole and forming a first connection metal layer, a second connection metal layer, and a third connection metal layer. The first connection metal layer covers the UBM layer inside the through hole, the second connection metal layer is integrally connected to the first connection metal layer, and the third connection metal layer covers the UBM layer on the connection pad liner.

Abstract: According to one implementation of the present disclosure, an integrated circuit includes a memory macro unit, and one or more through silicon vias (TSVs) at least partially coupled through the memory macro unit. According to one implementation of the present disclosure, a computer-readable storage medium comprising instructions that, when executed by a processor, cause the processor to perform operations including: receiving a user input corresponding to dimensions of respective pitches of one or more through silicon vias (TSVs); determining whether dimensions of a memory macro unit is greater than a size threshold, wherein the size threshold corresponds to the received user input; and determining one or more through silicon via (TSV) positionings based on the determined dimensions of the memory macro unit.

Abstract: Provided is a technique that can suppress remaining of air bubbles on a lower surface of an electric field shielding plate. A plating apparatus 1000 include a plating tank 10, a substrate holder 30, and an electric field shielding plate 60 configured to be arranged in a portion between an anode 50 and a substrate Wf in an inside of the plating tank for shielding a part of an electric field formed between the anode and the substrate. In a top view of the electric field shielding plate, in the inside of the plating tank, an unshielded region 70 that is without shielded by the electric field shielding plate is disposed. An inclined surface is disposed in a lower surface 61a of the electric field shielding plate, the inclined surface is inclined with respect to a horizontal direction and is configured to release an air bubble existing on the lower surface thereof to the unshielded region.

Abstract: A semiconductor device including a plurality of wirings and an insulating space is described. The insulating space is disposed between adjacent wirings of the plurality of wirings. An insulating material surrounds the insulating space. The insulating space is filled with air at a pressure no more than an atmospheric pressure.

Abstract: Structures for metallization levels of integrated circuits and associated fabrication methods. A first metallization level with a metallization line is formed. A second metallization level is formed over the first metallization level, having two metallization lines and two conductive vias extending from the two metallization lines to the metallization line in the first metallization level. The first metallization line is separated into a first section and a second section disconnected from the first section, so that the first section is connected by one conductive via to one metallization line in the second metallization level, and the second section is connected by the other conductive via to the other metallization line in the second level.

Abstract: A method of fabricating an integrated circuit (IC) includes etching a trench in a semiconductor substrate having an aspect ratio (AR) ?5 and a trench depth ?10 ?m. A dielectric liner is formed along the walls of the trench to form a dielectric lined trench. In-situ doped polysilicon is deposited into the trench to form a dielectric lined polysilicon filled trench having a doped polysilicon filler therein. The doped polysilicon filler after completion of fabricating the IC is essentially polysilicon void-free and has a 25° C. sheet resistance ?100 ohms/sq. The method can include etching an opening at a bottom of the dielectric liner before depositing the polysilicon to provide ohmic contact to the semiconductor substrate.

Abstract: Cavities of possibly different widths can be etched in a stack of conductive layers (such as metal) using the same lithographic mask. Dielectric can be formed in the cavities. The cavities may contain voids. Other embodiments are also provided.

Abstract: A method of forming a conductive element on a substrate and the resulting assembly are provided. The method includes forming a groove in a sacrificial layer overlying a dielectric region disposed on a substrate. The groove preferably extends along a sloped surface of the substrate. The sacrificial layer is preferably removed by a non-photolithographic method, such as ablating with a laser, mechanical milling, or sandblasting. A conductive element is formed in the groove. The grooves may be formed. The grooves and conductive elements may be formed along any surface of the substrate, including within trenches and vias formed therein, and may connect to conductive pads on the front and/or rear surface of the substrate. The conductive elements are preferably formed by plating and may or may not conform to the surface of the substrate.

Abstract: Methods of forming a microelectronic packaging structure are described. Those methods may include forming a solder paste comprising a sacrificial polymer on a substrate, curing the solder paste below a reflow temperature of the solder to form a solid composite hybrid bump on the conductive pads, forming a molding compound around the solid composite hybrid bump, and reflowing the hybrid bump, wherein the sacrificial polymer is substantially decomposed.

Abstract: A system and process for forming a ball grid array on a substrate includes defining a plurality of openings in a resist layer on the substrate, and forming a plurality of openings in the resist layer, each positioned over a contact pad of the substrate. Flux is then deposited in the openings, and solder balls are positioned in each opening with the flux. Solder bumps are formed by reflowing the solder balls in the respective openings. The resist layer is then removed, leaving an array of solder bumps on the substrate. The flux can be deposited by depositing a layer of flux, then removing the flux, except a portion that remains in each opening. Solder balls can be positioned by moving a ball feeder across the resist layer and dropping a solder ball each time an aperture in the ball feeder aligns with an opening in the resist layer.

Abstract: An interconnect pad is formed over a first substrate. A photoresist layer is formed over the first substrate and interconnect pad. A portion of the photoresist layer is removed to form a channel and expose a perimeter of the interconnect pad while leaving the photoresist layer covering a central area of the interconnect pad. A first conductive material is deposited in the channel of the photoresist layer to form a column of conductive material. The remainder of the photoresist layer is removed. A masking layer is formed around the column of conductive material while exposing the interconnect pad within the column of conductive material. A second conductive material is deposited over the first conductive layer. The second conductive material extends above the column of conductive material. The masking layer is removed. The second conductive material is reflowed to form a column interconnect structure over the semiconductor device.

Abstract: Disclosed is a variable interconnect geometry formed on a substrate that allows for increased electrical performance of the interconnects without compromising mechanical reliability. The compliance of the interconnects varies from the center of the substrate to edges of the substrate. The variation in compliance can either be step-wise or continuous. Exemplary low-compliance interconnects include columnar interconnects and exemplary high-compliance interconnects include helix interconnects. A cost-effective implementation using batch fabrication of the interconnects at a wafer level through sequential lithography and electroplating processes may be employed.

Abstract: Provided are semiconductor packages and methods of manufacturing the semiconductor package. The semiconductor packages may include a substrate including a chip pad, a redistributed line which is electrically connected to the chip pad and includes an opening. The semiconductor packages may also include an external terminal connection portion, and an external terminal connection pad which is disposed at an opening and electrically connected to the redistributed line. The present general inventive concept can solve the problem where an ingredient of gold included in a redistributed line may be prevented from being diffused into an adjacent bump pad to form a void or an undesired intermetallic compound. In a chip on chip structure, a plurality of bumps of a lower chip are connected to an upper chip to improve reliability, diversity and functionality of the chip on chip structure.

Abstract: A method for forming an interconnect structure includes forming a recess in a dielectric layer of a substrate. An adhesion barrier layer is formed to line the recess. A first stress level is present across a first interface between the adhesion barrier layer and the dielectric layer. A stress-reducing barrier layer is formed over the adhesion barrier layer. The stress-reducing barrier layer reduces the first stress level to provide a second stress level, less than the first stress level, across a second interface between the adhesion barrier layer, the stress-reducing barrier layer, and the dielectric layer. The recess is filled with a fill layer.

Abstract: A packaged microelectronic element includes a microelectronic element having a front surface and a plurality of first solid metal posts extending away from the front surface. A substrate has a major surface and a plurality of conductive elements exposed at the major surface and joined to the first solid metal posts. In particular examples, the conductive elements can be bond pads or can be second posts having top surfaces and edge surfaces extending at substantial angles away therefrom. Each first solid metal post includes a base region adjacent the microelectronic element and a tip region remote from the microelectronic element, the base region and tip region having respective concave circumferential surfaces. Each first solid metal post has a horizontal dimension which is a first function of vertical location in the base region and which is a second function of vertical location in the tip region.

Abstract: A method for forming an interconnect structure includes forming a recess in a dielectric layer of a substrate, forming a first transition metal layer in the recess on corner portions of the recess, and forming a second transition metal layer in the recess over the first transition metal layer to line the recess. The method further includes filling the recess with a fill layer and annealing the substrate so that the first transition metal layer and the second transition metal layer form an alloy portion proximate the corner portions during the annealing, the alloy portion having a reduced wettability for a material of the fill layer than the second transition metal. Additionally, the method includes polishing the substrate to remove portions of the fill layer extending above the recess.

Abstract: A BGA package structure and a method for fabricating the same, wherein the BGA package structure comprises: a substrate having a first surface used to carry a chip and a second surface opposite to the first surface, wherein the substrate is divided into several regions according to different distances from a central point of the substrate; a plurality of contact bonding pads on the second surface electrically connected with the chip; and a plurality of bumps respectively attached to each of the contact bonding pads, wherein the contact bonding pads and bumps in a region which is closest to the central point are the smallest, while the contact bonding pads and bumps in a region which is farthest to the central point are the biggest. Therefore the situation that the bumps at the edge are liable to peel off may improved.

Abstract: A structure comprises a first semiconductor chip with a first metal bump and a second semiconductor chip with a second metal bump. The structure further comprises a solder joint structure electrically connecting the first semiconductor chip and the second semiconductor chip, wherein the solder joint structure comprises an intermetallic compound region between the first metal bump and the second metal bump, wherein the intermetallic compound region is with a first height dimension and a surrounding portion formed along exterior walls of the first metal bump and the second metal bump, wherein the surrounding portion is with a second height dimension, and wherein the second height dimension is greater than the first height dimension.

Abstract: Packaging devices, methods of manufacture thereof, and packaging methods for semiconductor devices are disclosed. In one embodiment, a packaging device includes a substrate including an integrated circuit die mounting region. An underfill material flow prevention feature is disposed around the integrated circuit die mounting region.

Abstract: An electronic apparatus includes a semiconductor substrate, a device structure supported by the semiconductor substrate, and a guard ring surrounding the device structure. The guard ring includes a plurality of conductive structures spaced apart from one another, supported by the semiconductor substrate, and coupled to a voltage source to establish an operating voltage for the guard ring.

Abstract: Electrical connection in an integrated circuit arrangement is facilitated with carbon nanotubes. According to various example embodiments, a carbon nanotube material (120, 135) is associated with another material (130, 125) such as a metal. The carbon nanotube material facilitates the electrical connection between different circuit components.

Abstract: A structure and method of making an offset-trench crackstop, which forms an air gap in a passivation layer that is adjacent to a passivated top metal layer of a metal crackstop in an integrated circuit (IC) die. The offset-trench crackstop may expose a portion of a topmost dielectric layer in the crackstop region, not expose a topmost patterned metal layer of the metal crackstop, and may be interposed between the metal crackstop and an active device region. Alternatively, the offset-trench crackstop may expose a portion of the topmost dielectric layer, which separates an outermost metal layer and an innermost metal layer of the metal crackstop, and does not expose any of the topmost patterned metal layer of the metal crackstop, where the innermost metal layer of the metal crackstop is interposed between the offset-trench crackstop in the crackstop region and the active device region of the IC die.

Abstract: A semiconductor package includes a semiconductor substrate, a contact pad overlying the semiconductor substrate, an interconnect layer overlying the contact pad, a passivation layer formed between the contact pad and the interconnect layer, a bump overlying the interconnect layer, and a protection layer overlying the interconnect layer and the passivation layer and covering a lower portion of the bump. The protection layer includes a curved surface region.

Abstract: There are provided a semiconductor device capable of accurately determining whether a semiconductor chip is bonded to a solid-state device such as the other semiconductor chip parallelly with each other, a semiconductor chip used for the semiconductor device, and a method of manufacturing the semiconductor chip. The semiconductor chip includes a functional bump projected with a first projection amount from the surface of the semiconductor chip and electrically connecting the semiconductor chip to the solid-state device, and a connection confirmation bump projected with a second projection amount, which is smaller than the first projection amount, from the surface of the semiconductor chip and used for confirming the state of the electrical connection by the functional bump.

Abstract: Among other things, a semiconductor seal ring and method for forming the same are provided. The semiconductor seal ring comprises a plurality of dielectric layers formed over a semiconductor substrate upon which a semiconductor device is formed. A plurality of conductive layers is arranged among at least some of the plurality of dielectric layers. An upper conductive layer is formed over the plurality of dielectric layers. An upper passivation layer is formed over the upper conductive layer to isolate the upper conductive layer from conductive debris resulting from a die saw process along a die saw cut line. In an example, a first columnar region comprising a first portion of the conductive layers is electrically isolated from the semiconductor device because the first columnar region is disposed relatively close to the die saw cut line and thus can be exposed to conductive debris which can cause undesired short circuits.

Abstract: A semiconductor wafer contains a plurality of semiconductor die separated by a saw street. A contact pad is formed over an active surface of the semiconductor die. A protective pattern is formed over the active surface of the semiconductor die between the contact pad and saw street of the semiconductor die. The protective pattern includes a segmented metal layer or plurality of parallel segmented metal layers. An insulating layer is formed over the active surface, contact pad, and protective pattern. A portion of the insulating layer is removed to expose the contact pad. The protective pattern reduces erosion of the insulating layer between the contact pad and saw street of the semiconductor die. The protective pattern can be angled at corners of the semiconductor die or follow a contour of the contact pad. The protective pattern can be formed at corners of the semiconductor die.

Abstract: Generally, the subject matter disclosed herein relates to repairing anomalous stiff pillar bumps that may be detected above a metallization system of a semiconductor chip or wafer. One illustrative method disclosed herein includes, among other things, forming a pillar bump above a metallization system of a semiconductor chip, and forming a plurality of notches in the pillar bump, wherein the plurality of notches are adapted to adjust a flexibility of the pillar bump when the pillar bump is exposed to a lateral force.

Abstract: A solder structure for joining an IC chip to a package substrate, and method of forming the same are disclosed. In an embodiment, a structure is formed which includes a wafer having a plurality of solder structures disposed above the wafer. A ball limiting metallurgy (BLM) layer disposed beneath each of the solder structures, above the wafer. At least one of the plurality of solder structures has a first composition, and at least another of the plurality of solder structures has a second composition.

Abstract: A system and method for preventing cracks in a passivation layer is provided. In an embodiment a contact pad has a first diameter and an opening through the passivation layer has a second diameter, wherein the first diameter is greater than the second diameter by a first distance of about 10 ?m. In another embodiment, an underbump metallization is formed through the opening, and the underbump metallization has a third diameter that is greater than the first diameter by a second distance of about 5 ?m. In yet another embodiment, a sum of the first distance and the second distance is greater than about 15 ?m.

Abstract: A semiconductor device comprises a substrate, a word line, an insulation material, and an etch stop material. The substrate comprises a pillar that may comprise an active area. The word line is formed in the substrate. The insulation material is formed on the word line. The etch stop material is formed on the insulating material and around the pillar.

Abstract: A method of patterning a metal layer is disclosed. The method includes providing a substrate and forming a material layer over the substrate. The method includes forming a second material layer over the first material layer. The method includes performing a first patterning process to the second material layer to form a trench in the second material layer. The first patterning process defines a width size of the trench, the width size being measured in a first direction. The method includes performing a second patterning process to the trench to transform the trench. The second patterning process defines a length size of the transformed trench. The length size is measured in a second direction different from the first direction. The method also includes filling the transformed trench with a conductive material.

Abstract: A device and method for fabricating a device is disclosed. An exemplary device includes a first conductive layer disposed over a substrate, the first conductive layer including a first plurality of conductive lines extending in a first direction. The device further includes a second conductive layer disposed over the first conductive layer, the second conductive layer including a second plurality of conductive lines extending in a second direction. The device further includes a self-aligned interconnect formed at an interface where a first conductive line of the first plurality of conductive lines is in electrical contact with a first conductive line of the second plurality of conductive lines. The device further includes a blocking portion interposed between a second conductive line of the first plurality of conductive lines and a second conductive line of the second plurality of conductive lines.

Abstract: Disclosed herein is a bump-on-trace interconnect with a wetted trace sidewall and a method for fabricating the same. A first substrate having conductive bump with solder applied is mounted to a second substrate with a trace disposed thereon by reflowing the solder on the bump so that the solder wets at least one sidewall of the trace, with the solder optionally wetting between at least half and all of the height of the trace sidewall. A plurality of traces and bumps may also be disposed on the first substrate and second substrate with a bump pitch of less than about 100 ?m, and volume of solder for application to the bump calculated based on at least one of a joint gap distance, desired solder joint width, predetermined solder joint separation, bump geometry, trace geometry, minimum trace sidewall wetting region height and trace separation distance.

Abstract: A system, method, and computer program product are provided for preparing a substrate post. In use, a first solder mask is applied to a substrate. Additionally, a post is affixed to each of one or more pads of the substrate. Further, a second solder mask is applied to the substrate.

Abstract: A conductive bump structure is formed on a substrate having a plurality of bonding pads and a first insulating layer thereon. The first insulating layer has a plurality of openings formed therein for exposing the bonding pads and a conductive post is formed on the bonding pads exposed through the openings. Therein, a gap is formed between the conductive post and the wall of the opening such that no contact occurs between the conductive post and the first insulating layer, thereby preventing delamination of the conductive bump structure caused by stresses concentrating on an interface of different materials as in the prior art.

Abstract: A method for manufacturing fine-pitch bumps comprises providing a silicon substrate; forming a titanium-containing metal layer having a plurality of first zones and a plurality of second zones on the silicon substrate; forming a photoresist layer on the titanium-containing metal layer; patterning the photoresist layer; forming a plurality of copper bumps having a plurality of first top surfaces and a plurality of first ring surfaces; heating the photoresist layer to form a plurality of body portions and removable portions; etching the photoresist layer; forming a plurality of bump protection layers on the titanium-containing metal layer, the first top surface and the first ring surface, each of the bump protection layers comprises a bump coverage portion; plating a plurality of gold layers at the bump coverage portion; eventually, removing the second zones to enable each of the first zones to form an under bump metallurgy layer.

Abstract: A semiconductor device has a semiconductor die and first insulating layer formed over the semiconductor die. A plurality of first micro-vias can be formed in the first insulating layer. A conductive layer is formed in the first micro-openings and over the first insulating layer. A second insulating layer is formed over the first insulating layer and conductive layer. A portion of the second insulating layer is removed to expose the conductive layer and form a plurality of second micro-openings in the second insulating layer over the conductive layer. The second micro-openings can be micro-vias, micro-via ring, or micro-via slots. Removing the portion of the second insulating layer leaves an island of the second insulating layer over the conductive layer. A bump is formed over the conductive layer. A third insulating layer is formed in the second micro-openings over the bump. The second micro-openings provide stress relief.

Abstract: Structures and methods for detecting solder wetting of pedestal sidewalls. The structure includes a semiconductor wafer having an array of integrated circuit chips, each of the integrated circuit chips having an array of chip pedestals having respective chip solder columns on top of the chip pedestals, the pedestals spaced apart a first distance in a first direction and a spaced apart second distance in second direction perpendicular to the first direction; and at least one monitor structure disposed in different regions of the wafer from the integrated circuit chips, the monitor structure comprising at least a first pedestal and a first solder column on a top surface of the first pedestal and a second pedestal and a second solder column on a top surface of the second pedestal, the first and the second pedestals spaced apart a third distance, the third distance less than the first and the second distances.