Abstract: Methods and devices for multi-chip stacks are shown. A method is shown that assembles multiple chips into stacks by stacking wafers prior to dicing into individual chips. Methods shown provide removal of defective chips and their replacement during the assembly process to improve manufacturing yield.

Abstract: Embodiments of the present disclosure provide a substrate, one of either a semiconductor die or an interposer disposed on the substrate, the semiconductor die or the interposer having a first surface attached to the substrate and a second surface that is opposite to the first surface, one or more interconnect structures formed on the second surface of the semiconductor die or the interposer, a mold compound formed to substantially encapsulate the semiconductor die or the interposer, and one or more vias formed in the mold compound to facilitate coupling the one or more interconnect structures with another component. Other embodiments may be described and/or claimed.

Abstract: Systems and methods are provided for stacked semiconductor memory devices. The stacked semiconductor memory devices can include a nonvolatile memory controller, a number of nonvolatile memory dies arranged in a stacked configuration, and a package substrate. The memory controller and the memory dies can be coupled to each other with vias that extend through the package substrate. A vertical interconnect process may be used to electrically connect the nonvolatile memory dies to each other, as well as other system components. The memory controller may be flip-chip bonded to external circuitry, such as another semiconductor device or a printed circuit board.

Abstract: This disclosure provides systems, methods and apparatus for storage capacitors. In one aspect, a device includes an array having at least a first display element and a second display element, at least one switch configured to control a flow of charge between a source and the first display element, and at least one interferometric optical mask structure disposed in a non-active area of the array between the first display element and the second display element. The optical mask structure includes a storage capacitor formed by a first conductive layer and a second conductive layer. The storage capacitor is electrically coupled to the at least one switch and the first display element.

Abstract: Methods and apparatus for a forming molded underfills. A method is disclosed including loading a flip chip substrate into a selected one of the upper mold chase and lower mold chase of a mold press at a first temperature; positioning a molded underfill material in the at least one of the upper and lower mold chases while maintaining the first temperature which is lower than a melting temperature of the molded underfill material; forming a sealed mold cavity and creating a vacuum in the mold cavity; raising the temperature of the molded underfill material to a second temperature greater than the melting point to cause the molded underfill material to flow over the flip chip substrate forming an underfill layer and forming an overmolded layer; and cooling the flip chip substrate to a third temperature substantially lower than the melting temperature of the molded underfill material. An apparatus is disclosed.

Abstract: A semiconductor device has a base substrate with first and second opposing surfaces. A first etch-resistant conductive layer is formed over the first surface of the base substrate. A second etch-resistant conductive layer is formed over the second surface of the base substrate. A first semiconductor die has bumps formed over contact pads on an active surface of the first die. The first die is mounted over a first surface of the first conductive layer. An encapsulant is deposited over the first die and base substrate. A portion of the base substrate is removed to form electrically isolated base leads between opposing portions of the first and second conductive layers. A second semiconductor die is mounted over the encapsulant and a second surface of the first conductive layer between the base leads. A height of the base leads is greater than a thickness of the second die.

Abstract: A packaging substrate structure with an electronic component embedded therein and a fabricating method thereof are disclosed. The packaging substrate structure comprises a core plate; a first built-up structure disposed on a surface of the core plate and comprising a first dielectric layer and a first circuit layer disposed on the first dielectric layer; a second built-up structure disposed on the first built-up structure, wherein a cavity is disposed in the second built-up structure to expose the first built-up structure; an electronic component disposed in the cavity, wherein the electronic component has an active surface having a plurality of electrode pads and an inactive surface facing the first built-up structure; and a solder mask disposed on the surfaces of the second built-up structure and the electronic component, and having a plurality of first openings to expose the electrode pads of the electronic component.

Abstract: An embodiment of a method of forming an on-chip RE shield on an integrated circuit chip in accordance with the present disclosure includes providing a wafer level integrated circuit component wafer having a front side and a back side before singulation; applying a resin metal layer on a back side of the wafer; and then separating the wafer into discrete RF shielded components. It is this resin metal layer on the back side that acts effectively as the RF shield, after singulation, i.e. separation of the wafer, into discrete RF shielded components.

Abstract: A plurality of semiconductor die is mounted to a temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. A portion of the encapsulant is designated as a saw street between the die, and a portion of the encapsulant is designated as a substrate edge around a perimeter of the encapsulant. The carrier is removed. A first insulating layer is formed over the die, saw street, and substrate edge. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first conductive layer and first insulating layer. The encapsulant is singulated through the first insulating layer and saw street to separate the semiconductor die. A channel or net pattern can be formed in the first insulating layer on opposing sides of the saw street, or the first insulating layer covers the entire saw street and molding area around the semiconductor die.

Abstract: There is provided a lead frame and a packaging method. The lead frame comprises a first plurality of die pads, a second plurality of leads extending from the first plurality of die pads, and a third plurality of tie elements, each of which connects one of the first plurality of die pads to another.

Abstract: Disclosed is a pH sensor comprising a carrier (10) comprising a plurality of conductive tracks and an exposed conductive area (40) defining a reference electrode connected to one of said conductive tracks; a sensing device (30) mounted on the carrier and connected at least one other of said conductive tracks; an encapsulation (20) covering the carrier, said encapsulation comprising a first cavity (22) exposing a surface (32) of the sensing device and a second cavity (24) exposing the exposed conductive area, said second cavity comprising a reference electrode material (42) and an ion reservoir material (44) sharing at least one ion type with said reference electrode material, the reference electrode material being sandwiched between the exposed conductive area and the ion reservoir material. A method of manufacturing such a pH sensor is also disclosed.

Abstract: Semiconductor devices and methods of manufacturing and packaging thereof are disclosed. In one embodiment, a semiconductor device includes an integrated circuit and a plurality of copper pillars coupled to a surface of the integrated circuit. The plurality of copper pillars has an elongated shape. At least 50% of the plurality of copper pillars is arranged in a substantially centripetal orientation.

Abstract: A semiconductor chip device includes a first semiconductor chip adapted to be stacked with a second semiconductor chip wherein the second semiconductor chip includes a side and first and second conductor structures projecting from the side. The first semiconductor chip includes a first edge, a first conductor pad, a first conductor pillar positioned on but laterally offset from the first conductor pad toward the first edge and that has a first lateral dimension and is adapted to couple to one of the first and second conductor structures, a second conductor pad positioned nearer the first edge than the first conductor pad, and a second conductor pillar positioned on but laterally offset from the second conductor pad and that has a second lateral dimension larger than the first lateral dimension and is adapted to couple to the other of the first and second conductor structures.

Abstract: In one embodiment, semiconductor die having non-rectangular shapes and die having various different shapes are formed and singulated from a semiconductor wafer.

Abstract: A method and device having chip scale MEMS packaging is described. A first substrate includes a MEMS device and a second substrate includes an integrated circuit. The frontside of the first substrate is bonded to the backside of the second substrate. Thus, the second substrate provides a cavity to encase, protect or operate the MEMS device within. The bond may provide an electrical connection between the first and second substrate. In an embodiment, a through silicon via is used to carry the signals from the first substrate to an I/O connection on the frontside of the second substrate.

Abstract: The present invention relates to a thermoelectric device, in particular an all-organic thermoelectric device, and to an array of such thermoelectric devices. Furthermore, the present invention relates to a method of manufacturing a thermoelectric device, in particular an all-organic thermoelectric device. Moreover, the present invention relates to uses of the thermoelectric device and/or the array in accordance with the present invention.

Abstract: The semiconductor module includes a plurality of memory die on a first side of a substrate and a plurality of buffer die on a second side of the substrate. Each of the memory die is disposed opposite and electrically coupled to one of the buffer die.

Abstract: Antenna switch modules and methods of making the same are provided. In certain implementations, an antenna switch module includes a package substrate, an integrated filter, and a silicon on insulator (SOI) die attached to the package substrate. The SOI die includes a capacitor configured to operate in the integrated filter and a multi throw switch for selecting amongst the RF signal paths. In some implementations, a surface mount inductor is attached to the package substrate adjacent the SOI die and is configured to operate in the integrated filter with the capacitor. In certain implementations, the inductor is formed from a conductive layer of the package substrate disposed beneath a layer of the package substrate used to attach the SOI die.

Abstract: In one embodiment, a method of forming a semiconductor device package includes: (1) providing a carrier and a semiconductor device including an active surface; (2) forming a first redistribution structure including a first electrical interconnect extending laterally within the first structure and a plurality of second electrical interconnects extending vertically from a first surface of the first interconnect, each second interconnect including a lower surface adjacent to the first surface and an upper surface opposite the lower surface; (3) disposing the device on the carrier such that the active surface is adjacent to the carrier; (4) disposing the first structure on the carrier such that the upper surface of each second interconnect is adjacent to the carrier, and the second interconnects are positioned around the device; and (5) forming a second redistribution structure adjacent to the active surface, and including a third electrical interconnect extending laterally within the second structure.

Abstract: An RFID based thermal bubble type accelerometer includes a flexible substrate, an embedded system on chip (SOC) unit, an RFID antenna formed on the substrate and coupled to a modulation/demodulation module in the SOC unit, a cavity formed on the flexible substrate, and a plurality of sensing assemblies, including a heater and two temperature-sensing elements, disposed along the x-axis direction and suspended over the cavity. The two temperature-sensing elements, serially connected, are separately disposed at two opposite sides and at substantially equal distances from the heater. Two sets of sensing assemblies can be connected in differential Wheatstone bridge. The series-connecting points of the sensing assemblies are coupled to the SOC unit such that an x-axis acceleration can be obtained by a voltage difference between the connecting points. The x-axis acceleration can be sent by the RFID antenna to a reader after it is is modulated and encoded by the modulation/demodulation module.

Abstract: A semiconductor device having stacked semiconductor chips is provided wherein alignment of even thin semiconductor chips of a large warpage is easy and thus high assembling accuracy and high reliability are ensured. Semiconductor chips having hollow through-silicon via electrodes each formed with a tapered portion are melt-joined using solder balls each having a core of a material higher in melting point than solder. When melt-joining the semiconductor chips, the temperature is raised while imparting an urging load to stacked semiconductor chips, thereby correcting warpage of the semiconductor chips. In each chip-to-chip connection thus formed, if the connection is to prevent the occurrence of stress around the electrode due to the urging load, a solder ball having a core of a smaller diameter than in the other connections is used in the connection.

Abstract: The present invention includes embodiments of a processing method, and resulting structure, for building a chip having a TSV pillar which can be used as an interconnecting structure. The process includes the deposition of a dual diffusion barrier between the TSV and the substrate the TSV is embedded within. The TSV is then exposed from the back side of the substrate so that at least a portion of the TSV protrudes from the substrate and can be used as a contact for connecting the chip to another surface. The resulting TSV is rigid, highly conductive, can be placed in a tightly pitched grid of contacts, and reduces effects of CTE mismatch.

Abstract: A semiconductor chip includes a power transistor circuit with a plurality of active transistor cells. A first load electrode and a control electrode are arranged on a first face of the semiconductor chip, wherein the first load electrode includes a first metal layer. A second load electrode is arranged on a second face of the semiconductor chip. A second metal layer is arranged over the first metal layer, wherein the second metal layer is electrically insulated from the power transistor circuit and the second metal layer is arranged over an area of the power transistor circuit that comprises at least one of the plurality of active transistor cells.

Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes an interconnect structure formed on a substrate; a landing metal trace formed on the interconnect structure and coupled to the interconnect structure, wherein the landing metal trace includes a first width T defined in a first direction; and a metal bump post formed on and aligned with the landing metal trace, wherein the metal bump post includes a second width U defined in the first direction, and the second width U is greater than the first width T.

Abstract: A layered chip package includes a main body, and wiring that includes a plurality of wires disposed on a side surface of the main body. The main body includes: a main part including a plurality of layer portions; a plurality of first terminals disposed on the top surface of the main part and connected to the wiring; and a plurality of second terminals disposed on the bottom surface of the main part and connected to the wiring. Each layer portion includes a semiconductor chip. The plurality of second terminals are positioned to overlap the plurality of first terminals as viewed in a direction perpendicular to the top surface of the main body. A plurality of pairs of first and second terminals that are electrically connected via the wires include a plurality of pairs of a first terminal and a second terminal that are positioned not to overlap each other.

Abstract: Various aspects provide for bending a bending a lead frame of a semiconductor device package into a shape of an “L” and mounting the package on a substrate. A horizontal portion of the bent lead-frame is about parallel with a surface of the package. A vertical portion of the bent lead frame is configured to extend the horizontal portion beyond the surface of the package. A device may be mounted between the substrate and the package.

Abstract: Disclosed herein is a power module package including: a first substrate; a second substrate having a pad for connection to the first substrate formed on one side or both sides of one surface thereof and having external connection terminals for connection to the outside formed on the other surface thereof; and a lead frame having one end bonded to the first substrate and the other end bonded to the pad of the second substrate to thereby vertically connect the first and second substrates to each other.

Abstract: An integrated circuit with distributed power using through-silicon-vias (TSVs) is presented. The integrated circuit has conducting pads for providing power and ground located within the peripheral region of the top surface. A number of through-silicon-vias are distributed within the peripheral region and a set of TSVs are formed within the non-peripheral region of the integrated circuit. Conducting lines on the bottom surface are coupled between each peripheral through-silicon-via and a corresponding non-peripheral through-silicon-via. Power is distributed from the conducting pads to the TSVs within the non-peripheral region through the TSVs within the peripheral region, thus supplying power and ground to circuits located within the non-peripheral region of the integrated circuit chip.

Abstract: A semiconductor device has a substrate and RF FEM formed over the substrate. The RF FEM includes an LC low-pass filter having an input coupled for receiving a transmit signal. A Tx/Rx switch has a first terminal coupled to an output of the LC filter. A diplexer has a first terminal coupled to a second terminal of the Tx/Rx switch and a second terminal for providing an RF signal. An IPD band-pass filter has an input coupled to a third terminal of the Tx/Rx switch and an output providing a receive signal. The LC filter includes conductive traces wound to exhibit inductive and mutual inductive properties and capacitors coupled to the conductive traces. The IPD filter includes conductive traces wound to exhibit inductive and mutual inductive properties and capacitors coupled to the conductive traces. The RF FEM substrate can be stacked over a semiconductor package containing an RF transceiver.

Abstract: A semiconductor die includes a semiconductive substrate layer with first and second sides, a metal layer adjacent the second side of the semiconductive substrate layer, one or more active devices in an active layer on the first side of the semiconductive substrate layer; and a passive device in the metal layer in electrical communication with the active layer. The passive device can electrically couple to the active layer with through silicon vias (TSVs).

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; attaching an integrated circuit to the substrate; attaching a vertical interconnect over the substrate; forming an encapsulation on the substrate and covering the vertical interconnect; and forming a rounded cavity, having a curved side, in the encapsulation with the vertical interconnect exposed in the rounded cavity.

Abstract: An integrated-circuit chip and external electrical connection elements are arranged on a first side of a substrate to form an assembly that is placed within a mold. The mold includes first and second opposed planar faces with a molding film made of a deformable material on the first planar face. The molding film is pressed against end faces of the external electrical connection elements. Encapsulating material then fills the mold cavity producing a semiconductor device that, when removed from the mold, includes electrical connection elements that are peripherally coated by the encapsulating material and have exposed end faces. An additional semiconductor device may be mounted over and in electrical connection with the electrical connection elements through the exposed end faces.

Abstract: Embodiments provide a method comprising providing a multi-memory die that comprises multiple individual memory dies. Each of the individual memory dies is defined as an individual memory die within a wafer of semiconductor material during production of memory dies. The multi-memory die is created by singulating the wafer of semiconductor material into memory dies where at least one of the memory dies is a multi-memory die that includes multiple individual memory dies that are still physically connected together. The method further comprises coupling a semiconductor die to the multi-memory die.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; attaching a flip chip to the substrate; attaching a heat slug to the substrate and the flip chip; and forming a moldable underfill having a top underfill surface on the substrate, the flip chip, and the heat slug, the moldable underfill having a characteristic of being liquid at room temperature and the top underfill surface over the flip chip.

Abstract: A method of bonding a semiconductor substrate having a substrate 11 formed with a MEMS sensor and a substrate 21 having a bonding portion 30b film-formed by contacting an aluminum containing layer 31 with a germanium layer 32 on either a front surface or a rear surface and formed with an integrated circuit that controls the MEMS sensor, either a front surface or a rear surface of the substrate 11 is put to contact directly on the bonding portion of the substrate 21 to bond by eutectic bonding with pressurization and heating.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a mountable assembly includes: forming an integrated circuit device having a non-horizontal device side, an active device side, and a passive device side, providing a first integrated circuit die having an active side, a passive side, and an internal interconnect on the active side, applying a die attach adhesive on the passive side, attaching the passive side to the passive device side with the die attach adhesive, and applying an underfill on the passive device side and the internal interconnect, the underfill having a non-horizontal underfill side coplanar with the non-horizontal device side; and mounting on a substrate the mountable assembly.

Abstract: A method of manufacture of an integrated packaging system includes: providing a substrate; mounting an integrated circuit on the substrate; mounting an interposer substrate having an interposer pad on the integrated circuit; covering an encapsulant over the integrated circuit and the interposer substrate; forming a hole through the encapsulant aligned over the interposer pad; and placing a conductive connector on and in direct contact with the interposer pad.

Abstract: Systems and methods according to embodiments of the invention enable flip chip packaging using high density routing while minimizing the thickness and layer count of the flip chip package. By using a photoresist layer to create very fine traces on a metallic base layer, embodiments of the present invention combine advantages of leadframe substrates and laminate substrates by supporting high-density routing while minimizing layer count and manufacturing cost. Additionally, the use of raised metallic pads in a routing layer enables embodiments of the present invention to include highly compact traces that pass over IC die bond pad connection sites without directly coupling to these bond IC die bond pad connection sites. Further, embodiments of the present invention can support multiple thin routing layers without the need for organic (e.g., laminate) material separating these routing layers.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate having a through hole; mounting an integrated circuit in the through hole, the integrated circuit having an inactive side and a vertical side; connecting a first interconnect in direct contact with the integrated circuit and the substrate; applying a wire-in-film adhesive around and above the integrated circuit leaving a portion of the vertical side and the inactive side exposed and covering a portion of the first interconnect; and mounting a chip above the integrated circuit and in direct contact with the wire-in-film adhesive.

Abstract: The present disclosure involves a semiconductor device. The semiconductor device includes a wafer containing an interconnect structure. The interconnect structure includes a plurality of vias and interconnect lines. The semiconductor device includes a first conductive pad disposed over the interconnect structure. The first conductive pad is electrically coupled to the interconnect structure. The semiconductor device includes a plurality of second conductive pads disposed over the interconnect structure. The semiconductor device includes a passivation layer disposed over and at least partially sealing the first and second conductive pads. The semiconductor device includes a conductive terminal that is electrically coupled to the first conductive pad but is not electrically coupled to the second conductive pads.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base carrier having a base carrier hole from a base carrier interconnection side to a base carrier device side; mounting a base integrated circuit over the base carrier; forming an encapsulation over the base carrier covering the base integrated circuit, the encapsulation having an encapsulation top side and having an encapsulation hole directly over the base carrier hole; and forming an interconnection structure as a single integral structure through the base carrier hole and the encapsulation hole, the interconnection structure directly on the encapsulation top side and directly on the base carrier interconnection side.

Abstract: A semiconductor device has a substrate and plurality of first semiconductor die having conductive vias formed through the first semiconductor die mounted with an active surface oriented toward the substrate. An interconnect structure, such as bumps or conductive pillars, is formed over the substrate between the first semiconductor die. A second semiconductor die is mounted to the first semiconductor die. The second semiconductor die is electrically connected through the interconnect structure to the substrate and through the conductive vias to the first semiconductor die. An underfill material is deposited between the first semiconductor die and substrate. Discrete electronic components can be mounted to the substrate. A heat spreader or shielding layer is mounted over the first and second semiconductor die and substrate. Alternatively, an encapsulant is formed over the die and substrate and conductive vias or bumps are formed in the encapsulant electrically connected to the first die.

Abstract: According to one embodiment, there is provided a semiconductor device including a wiring board, a semiconductor chip mounted on a first surface of the wiring board, first external electrodes provided on the first surface of the wiring board, second external electrodes provided on a second surface of the wiring board, and a sealing resin layer sealing the semiconductor chip together with the first external electrodes. The sealing resin layer has a recessed portion exposing a part of each of the first external electrodes. The plural semiconductor devices are stacked to form a semiconductor module with a POP structure. In this case, the first external electrodes of the lower-side semiconductor device and the second external electrodes of the upper-side semiconductor device are electrically connected.

Abstract: The invention relates to a microelectromechanical system with an electromechanical microswitch for switching an electrical signal in particular a radio frequency signal, in particular in a GHz range, comprising a multi-level conductive path layer stack arranged on a substrate, wherein conductive paths of the multi-level conductive path layer stack arranged in different conductive levels are insulated from one another through electrically insulating layers and electrically connected with one another through via contacts, an electromechanical switch which is integrated in a recess of the multi-level conductive path layer stack and which includes a contact pivot, an opposite contact and at least one drive electrode for the contact pivot, wherein the contact pivot, the opposite contact and the at least one drive electrode respectively form a portion of a conductive level of the multi-level layer stack.

Abstract: A manufacturing method of a semiconductor device includes: forming an insulating layer above a substrate; forming a recessed section in the insulating layer; forming, on the insulating layer, a mask pattern having a first opening which exposes the recessed section, and a second opening which is arranged outside the first opening and does not expose the recessed section; forming a first conductive member and a second conductive member by respectively depositing a conductive material in the first opening and the second opening; and polishing and removing the first conductive member and the second conductive member on the upper side of the insulating layer so as to leave the first conductive member in the recessed section.

Abstract: A method for forming an assembly including, stacked on each other, first and second devices with semiconductor components including opposite conductive balls, this method including the steps of: a) forming, on the first device, at least one resin pattern, close to at least some of the conductive balls by a distance smaller than or equal to half the ball diameter, and of a height greater than the ball height; and b) bonding the second device to the first device, by using said at least one pattern to guide the balls of the second device towards the corresponding balls of the first device.

Abstract: A protective modular package cover has first and second fastening sections located at opposing first and second ends with one or more subassembly receiving sections disposed thereto and is configured to fasten the protective modular package cover to a core. Each fastening section has a foot surface located on a bottom surface of a fastening section and configured to make contact with the core, a mounting hole configured to receive a fastener, and a torque element. Each subassembly receiving section is configured to receive a subassembly and has a cross member formed along the underside of the protective modular package cover. Activation of the first torque element transfers a downward clamping force generated at the fastening element to a top surface of one or more subassemblies disposed in the one or more subassembly receiving sections via the cross member of each of the one or more subassembly receiving sections.

Abstract: In a method of fabricating an integrated circuit device having a three-dimensional stacked structured, the step of fixing many chip-shaped semiconductor circuits to a support substrate or a circuit layer with a predetermined layout can be performed easily and efficiently with a desired accuracy. Temporary adhesion portions 12b of semiconductor chips 13 are temporarily adhered to corresponding temporary adhesion regions 72a of a carrier substrate 73a by way of water films 81. The carrier substrate 73a is then pressed toward a support substrate or a desired circuit layer, thereby contacting connecting portions 12 of the chips 13 on the carrier substrate 73a with corresponding predetermined positions on the support substrate or a circuit layer. Thereafter, by fixing the connecting portions 12 to the predetermined positions, the chips 13 are attached to the support substrate or the circuit layer with a desired layout.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a post of multiple plating layers having a base end with an inward protrusion, a connect riser, and a top end opposite the base end; positioning an integrated circuit device having a perimeter end facing the connect riser and the inward protrusion; attaching a bond wire directly on the inward protrusion and the integrated circuit device; and applying an encapsulation over the integrated circuit device, the bond wire, the inward protrusion, and around the post, the encapsulation exposing a portion of the base end and the top end of the post.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a pre-plated leadframe having a contact pad and a die paddle pad; forming an isolated contact from the pre-plated leadframe and the contact pad; mounting an integrated circuit die over the die paddle pad; and encapsulating with an encapsulation the integrated circuit die and the isolated contact, the encapsulation having a bottom surface which is planar and exposing in the bottom surface only the contact pad and the die paddle pad.