Assembly Of Devices Consisting Of Solid-state Components Formed In Or On A Common Substrate; Assembly Of Integrated Circuit Devices (epo) Patents (Class 257/E21.705)
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Patent number: 8916956Abstract: System and method for providing a multiple die interposer structure. An embodiment comprises a plurality of interposer studs in a molded interposer, with a redirection layer on each side of the interposer. Additionally, the interposer studs may be initially attached to a conductive mounting plate by soldering or wirebond welding prior to molding the interposer, with the mounting plate etched to form one of the redirection layers. Integrated circuit dies may be attached to the redirection layers on each side of the interposer, and interlevel connection structures used to mount and electrically connect a top package having a third integrated circuit to the interposer assembly.Type: GrantFiled: December 2, 2013Date of Patent: December 23, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Mirng-Ji Lii, Hao-Yi Tsai, Jui-Pin Hung, Chien-Hsun Lee, Kai-Chiang Wu
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Patent number: 8889487Abstract: A three-dimensional (3D) gate driver integrated circuit includes a high-side integrated circuit stacked on a low-side integrated circuit where the high-side integrated circuit and the low-side integrated circuit are interconnected using through-silicon vias (TSV). As thus formed, the high-side integrated circuit and the low-side integrated circuit can be formed without termination regions and without buried layers. The 3D gate driver integrated circuit improves ease of high voltage integration and improves the ruggedness and reliability of the gate driver integrated circuit.Type: GrantFiled: June 24, 2014Date of Patent: November 18, 2014Assignee: Alpha and Omega Semiconductor IncorporatedInventor: Shekar Mallikarjunaswamy
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Patent number: 8889482Abstract: The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the present fabrication separation of an IC structure into multiple discrete components can take advantages of dedicated IC fabrication facilities and achieve more cost effective products. The present process can fabricate multiple components separately before assembling them into a complete integrated circuit. In an aspect, the ready-for-assembling components are taken directly from processed wafers without any additional assembling processes, and/or having lateral dimensions less than 1 mm.Type: GrantFiled: June 14, 2009Date of Patent: November 18, 2014Inventor: Jayna Sheats
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Patent number: 8884419Abstract: Embodiments of the present disclosure provide a substrate, one of either a semiconductor die or an interposer disposed on the substrate, the semiconductor die or the interposer having a first surface attached to the substrate and a second surface that is opposite to the first surface, one or more interconnect structures formed on the second surface of the semiconductor die or the interposer, a mold compound formed to substantially encapsulate the semiconductor die or the interposer, and one or more vias formed in the mold compound to facilitate coupling the one or more interconnect structures with another component. Other embodiments may be described and/or claimed.Type: GrantFiled: June 21, 2013Date of Patent: November 11, 2014Assignee: Marvell International Ltd.Inventors: Shiann-Ming Liou, Albert Wu
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Patent number: 8884412Abstract: System and method for providing a multiple die interposer structure. An embodiment comprises a plurality of interposer studs in a molded interposer, with a redirection layer on each side of the interposer. Additionally, the interposer studs may be initially attached to a conductive mounting plate by soldering or wirebond welding prior to molding the interposer, with the mounting plate etched to form one of the redirection layers. Integrated circuit dies may be attached to the redirection layers on each side of the interposer, and interlevel connection structures used to mount and electrically connect a top package having a third integrated circuit to the interposer assembly.Type: GrantFiled: December 2, 2013Date of Patent: November 11, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Mirng-Ji Lii, Hao-Yi Tsai, Jui-Pin Hung, Chien-Hsun Lee, Kai-Chiang Wu
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Patent number: 8853855Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; forming a conductive post on the substrate, the conductive post includes a vertical side; attaching an integrated circuit to the substrate; and forming an encapsulant including a molded cavity, the vertical side circumscribed by and exposed within the molded cavity from the encapsulant.Type: GrantFiled: March 16, 2012Date of Patent: October 7, 2014Assignee: STATS ChipPAC Ltd.Inventors: KyungHoon Lee, DaeSik Choi, Sooyoung Lee
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Patent number: 8828802Abstract: A wafer level chip scale package includes a first dielectric layer having a first surface, a second surface, and a main through hole passing through the first dielectric layer between the first and second surfaces. A semiconductor die is disposed in the main through hole of the first dielectric layer and including a bond pad disposed away from the first surface of the first dielectric layer. A redistribution layer is electrically connected to the bond pad of the semiconductor die and extends along the second surface of the first dielectric layer. A second dielectric layer covers the first dielectric layer and the redistribution layer and has an opening exposing the redistribution layer. An under bump metal fills the opening of the second dielectric layer and is electrically connected to the redistribution layer. A solder ball is electrically connected to the under bump metal.Type: GrantFiled: November 1, 2011Date of Patent: September 9, 2014Inventors: Sung Su Park, Kyung Han Ryu, Sang Mok Lee
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Patent number: 8822266Abstract: Various apparatuses and methods for forming integrated circuit packages are described. One aspect of the invention pertains to an integrated circuit package in which one or more integrated circuits are embedded in a substrate and covered with a layer of photo-imageable epoxy. The substrate can be made of various materials, including silicon, quartz and glass. An integrated circuit is positioned within a cavity in the top surface of the substrate. The epoxy layer is formed over the top surface of the substrate and the active face of the integrated circuit. An interconnect layer is formed over the epoxy layer and is electrically coupled with the integrated circuit.Type: GrantFiled: January 25, 2011Date of Patent: September 2, 2014Assignee: National Semiconductor CorporationInventors: Peter Smeys, Peter Johnson, Peter Deane, Reda R. Razouk
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Patent number: 8809119Abstract: An integrated circuit packaging system and method of manufacture thereof including: providing a leadframe having unprocessed leads; depositing an etch mask on a top surface of the unprocessed leads, the unprocessed leads having the etch mask and an unmasked portions of the top surface; connecting an integrated circuit die to the unprocessed leads; encapsulating with a package body the leadframe, the top surface of the unprocessed leads exposed from the package body; forming side-solderable leads including forming a groove in the unprocessed leads, the groove formed under a portion of the etch mask including forming an overhang of the etch mask over the groove; removing the etch mask; and depositing a plating on the side-solderable leads.Type: GrantFiled: May 17, 2013Date of Patent: August 19, 2014Assignee: STATS ChipPAC Ltd.Inventors: Emmanuel Espiritu, Henry Descalzo Bathan, Byung Tai Do
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Patent number: 8803258Abstract: A finger sensing device may include a mounting substrate, an integrated circuit (IC) die carried by the mounting substrate and having an array of electric field-based finger sensing elements, and first electrical connections coupling the mounting substrate and the IC die. In addition, the finger sensing device may include a protective plate attached over the array of electric field-based finger sensing elements and having a dielectric constant greater than 5 in all directions and a thickness greater than 40 microns to define a capacitive lens for the array of electric field-based finger sensing elements. The finger sensing device may also include an encapsulating material adjacent the mounting substrate and the IC die and around at least the first electrical connections.Type: GrantFiled: April 14, 2011Date of Patent: August 12, 2014Assignee: Authentec, Inc.Inventors: Giovanni Gozzini, Robert H. Bond
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Patent number: 8791723Abstract: A three-dimensional (3D) gate driver integrated circuit includes a high-side integrated circuit stacked on a low-side integrated circuit where the high-side integrated circuit and the low-side integrated circuit are interconnected using through-silicon vias (TSV). As thus formed, the high-side integrated circuit and the low-side integrated circuit can be formed without termination regions and without buried layers. The 3D gate driver integrated circuit improves ease of high voltage integration and improves the ruggedness and reliability of the gate driver integrated circuit.Type: GrantFiled: August 17, 2012Date of Patent: July 29, 2014Assignee: Alpha and Omega Semiconductor IncorporatedInventor: Shekar Mallikarjunaswamy
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Patent number: 8786079Abstract: Antenna switch modules and methods of making the same are provided. In certain implementations, an antenna switch module includes a package substrate, an integrated filter, and a silicon on insulator (SOI) die attached to the package substrate. The SOI die includes a capacitor configured to operate in the integrated filter and a multi throw switch for selecting amongst the RF signal paths. In some implementations, a surface mount inductor is attached to the package substrate adjacent the SOI die and is configured to operate in the integrated filter with the capacitor. In certain implementations, the inductor is formed from a conductive layer of the package substrate disposed beneath a layer of the package substrate used to attach the SOI die.Type: GrantFiled: August 8, 2012Date of Patent: July 22, 2014Assignee: Skyworks Solutions, Inc.Inventors: Jong-Hoon Lee, Chuming Shih
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Patent number: 8779586Abstract: The present invention provides a die bond film for adhering, onto a semiconductor element that is electrically connected to an adherend with a bonding wire, another semiconductor element and that enables loading of the other semiconductor element and improvement in the manufacturing yield of a semiconductor device by preventing deformation and cutting of the bonding wire, and a dicing die bond film. The die bond film of the present invention is a die bond film for adhering, onto a semiconductor element that is electrically connected to an adherend with a bonding wire, another semiconductor element, in which at least a first adhesive layer that enables a portion of the bonding wire to pass through inside thereof by burying the portion upon press bonding and a second adhesive layer that prevents the other semiconductor element from contacting with the bonding wire are laminated.Type: GrantFiled: February 28, 2011Date of Patent: July 15, 2014Assignee: Nitto Denko CorporationInventors: Kenji Oonishi, Miki Hayashi, Kouichi Inoue, Yuichiro Shishido
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Patent number: 8780600Abstract: Systems and methods are provided for stacked semiconductor memory devices. The stacked semiconductor memory devices can include a nonvolatile memory controller, a number of nonvolatile memory dies arranged in a stacked configuration, and a package substrate. The memory controller and the memory dies can be coupled to each other with vias that extend through the package substrate. A vertical interconnect process may be used to electrically connect the nonvolatile memory dies to each other, as well as other system components. The memory controller may be flip-chip bonded to external circuitry, such as another semiconductor device or a printed circuit board.Type: GrantFiled: December 7, 2011Date of Patent: July 15, 2014Assignee: Apple Inc.Inventors: Anthony Fai, Nicholas C. Seroff
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Patent number: 8742547Abstract: A semiconductor wafer includes: a first semiconductor chip area formed with a semiconductor element; a second semiconductor chip area formed with a semiconductor element; and a scribe area sandwiched between the first and second semiconductor chip areas; wherein: the first semiconductor chip area includes a first metal ring surrounding the semiconductor element formed in the first semiconductor chip area; and the metal ring is constituted of a plurality of metal layers including a lower metal layer and an upper metal layer superposed upon the lower metal layer, and the upper metal layer is superposed upon the lower metal layer in such a manner that an outer side wall of the upper metal layer is flush with the outer side wall of the lower metal layer or is at an inner position of the first semiconductor chip area relative to the outer side wall of the lower metal layer.Type: GrantFiled: February 15, 2011Date of Patent: June 3, 2014Assignee: Fujitsu Semiconductor LimitedInventors: Kazutaka Yoshizawa, Taiji Ema
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Patent number: 8741762Abstract: A method for preparing a die for packaging is disclosed. A die having first and second major surfaces is provided. Vias and a mask layer are formed on the first major surface of the die. The mask includes mask openings that expose the vias. The mask openings are filled with a conductive material. The method includes reflowing to at least partially fill the vias and contact openings to form via contacts in the vias and surface contacts in the mask openings.Type: GrantFiled: October 21, 2013Date of Patent: June 3, 2014Assignee: United Test and Assembly Center Ltd.Inventors: Hao Liu, Yi Sheng Anthony Sun, Ravi Kanth Kolan, Chin Hock Toh
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Patent number: 8742574Abstract: Semiconductor devices are described that have a through-substrate via formed therein. In one or more implementations, the semiconductor devices include a top wafer and a bottom wafer bonded together with a patterned adhesive material. The top wafer and the bottom wafer include one or more integrated circuits formed therein. The integrated circuits are connected to one or more conductive layers deployed over the surfaces of the top and bottom wafers. A via is formed through the top wafer and the patterned adhesive material so that an electrical interconnection can be formed between the integrated circuits formed in the top wafer and the integrated circuits formed in the bottom wafer. The via includes a conductive material that furnishes the electrical interconnection between the top and bottom wafers.Type: GrantFiled: August 9, 2011Date of Patent: June 3, 2014Assignee: Maxim Integrated Products, Inc.Inventors: Arkadii V. Samoilov, Tyler Parent, Xuejun Ying
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Publication number: 20140124962Abstract: A system may include a package defining a cavity and an integrated circuit (IC) disposed within the cavity. The package may include a first electrically conductive package contact and a second electrically conductive package contact. The IC may include a first electrically conductive IC contact and a second electrically conductive IC contact. The system also may include a wire bond extending between and electrically connecting the first electrically conductive package contact and the first electrically conductive IC contact. The system further may include an electrically conductive adhesive extending between and electrically connecting the second electrically conductive package contact and the second electrically conductive IC contact. Use of wire bonds and electrically conductive adhesive may increase an interconnect density between the IC and the package, while not requiring an increase in size of the IC or a decrease in pitch between wire bonds.Type: ApplicationFiled: November 8, 2012Publication date: May 8, 2014Applicant: Honeywell International Inc.Inventor: David Scheid
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Patent number: 8715802Abstract: The invention provides a transferring apparatus for a flexible electronic device and method for fabricating a flexible electronic device. The transferring apparatus for the flexible electronic device includes a carrier substrate. A release layer is disposed on the carrier substrate. An adhesion layer is disposed on a portion of the carrier substrate, surrounding the release layer and adjacent to a sidewall of the release layer. A flexible electronic device is disposed on the release layer and the adhesion layer, wherein the flexible electronic device includes a flexible substrate.Type: GrantFiled: June 19, 2009Date of Patent: May 6, 2014Assignee: Industrial Technology Research InstituteInventors: Pao-Ming Tsai, Liang-You Jiang, Yu-Yang Chang, Hung-Yuan Li
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Patent number: 8716852Abstract: A device includes a capping substrate bonded with a substrate structure. The substrate structure includes an integrated circuit structure. The integrated circuit structure includes a top metallic layer disposed on an outgasing prevention structure. At least one micro-electro mechanical system (MEMS) device is disposed over the top metallic layer and the outgasing prevention structure.Type: GrantFiled: February 17, 2012Date of Patent: May 6, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Pao Shu, Chia-Ming Hung, Wen-Chuan Tai, Hung-Sen Wang, Hsiang-Fu Chen, Alex Kalnitsky
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Publication number: 20140103509Abstract: A semiconductor device has a semiconductor die with an encapsulant deposited over and around the semiconductor die. An opening is formed in a first surface of the encapsulant by etching or LDA. A plurality of bumps is optionally formed over the semiconductor die. A bump is recessed within the opening of the encapsulant. A conductive ink is formed over the first surface of the encapsulant, bump and sidewall of the opening. The conductive ink can be applied by a printing process. An interconnect structure is formed over a second surface of the encapsulant opposite the first surface of the encapsulant. The interconnect structure is electrically connected to the semiconductor die. A semiconductor package is disposed over the first surface of the encapsulant with a plurality of bumps electrically connected to the conductive ink layer. The semiconductor package may contain a memory device.Type: ApplicationFiled: October 16, 2012Publication date: April 17, 2014Applicant: STATS ChipPAC, Ltd.Inventors: Insang Yoon, Flynn Carson, Il Kwon Shim, SeongHun Mun
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Publication number: 20140103464Abstract: A microphone system has a package forming an interior chamber, and a MEMS microphone secured within the interior chamber. The package forms an aperture for permitting acoustic access to the interior of the chamber and thus, the MEMS microphone. The system also has two dies; namely, the system has a primary circuit die within the interior chamber, and an integrated passive device die electrically connected with the primary circuit die. The primary circuit die is electrically connected with the MEMS microphone and has at least one active circuit element.Type: ApplicationFiled: October 16, 2012Publication date: April 17, 2014Applicant: ANALOG DEVICES, INC.Inventors: David Bolognia, Alain Valentin Guery
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Publication number: 20140097526Abstract: A method of assembling a packaged integrated circuit (IC) includes printing a viscous dielectric polymerizable material onto a die pad of a leadframe having metal terminals positioned outside the die pad. An IC die having a top side including a plurality of bond pads is placed with its bottom side onto the viscous dielectric polymerizable material. Bond wires are wire bonded between the plurality of bond pads and the metal terminals of the leadframe.Type: ApplicationFiled: October 4, 2012Publication date: April 10, 2014Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: WAN MOHD MISUARI SULEIMAN, AZDHAR DAHALAN
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Publication number: 20140097535Abstract: A multi-chip integrated circuit (IC) package is provided which is configured to protect against failure due to warpage. The IC package may comprise a substrate, a level-one IC die and a plurality of level-two IC dies. The level-one IC die having a surface that is electrically coupled to the substrate. The plurality of level-two IC dies is stacked above the level-one IC die. The plurality of level-two IC dies may each have an active surface that is electrically coupled to the substrate. The plurality of level-two IC dies may be arranged side by side such that the active surfaces of the plurality of level-two IC dies are positioned substantially in a same plane. Relative to a single die configuration, the level-two IC dies are separated thereby inhibiting cracking, peeling and/or other potential failures due to warpage of the IC package.Type: ApplicationFiled: October 8, 2012Publication date: April 10, 2014Applicant: QUALCOMM INCORPORATEDInventors: Dongming He, Zhongping Bao, Zhenyu Huang
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Publication number: 20140091445Abstract: An example includes a die package including a microelectronic die having a lower die surface, an upper die surface parallel to the lower die surface, and a die side, the microelectronic die including an active region and an inactive region. The example optionally includes a heat spreader having a lower heat spreader surface, an upper heat spreader surface parallel to the lower heat spreader surface, and at least one heat spreader side, the heat spreader disposed on the upper surface of the microelectronic die in thermal communication with the inactive region of the die and electrically insulated from the active region. The example optionally includes an encapsulation material encapsulating the die side and the heat spreader side and lower heat spreader surface, the encapsulation material including a lower surface substantially parallel to the die lower surface and an upper surface substantially parallel to the die upper surface.Type: ApplicationFiled: September 28, 2012Publication date: April 3, 2014Inventors: Weng Hong Teh, Deepak Kulkarni, Chia-Pin Chiu, Tannaz Harirchian, John S. Guzek
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Publication number: 20140070999Abstract: An apparatus includes a dielectric slab having first and opposing second major surfaces. A planar antenna element is located on the first major surface. A via formed through the dielectric slab is conductively connected to the antenna element. A plurality of solder bump pads is located on the second major surface and is configured to attach the dielectric slab to an integrated circuit.Type: ApplicationFiled: September 11, 2012Publication date: March 13, 2014Applicant: Alcatel-Lucent USA, Inc.Inventors: Noriaki Kaneda, Nagesh Basavanhally, Yves Baeyens, Young-Kai Chen, Shahriar Shahramian
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Patent number: 8664755Abstract: Disclosed herein is a power module package including: a first substrate; a second substrate having a pad for connection to the first substrate formed on one side or both sides of one surface thereof and having external connection terminals for connection to the outside formed on the other surface thereof; and a lead frame having one end bonded to the first substrate and the other end bonded to the pad of the second substrate to thereby vertically connect the first and second substrates to each other.Type: GrantFiled: September 28, 2011Date of Patent: March 4, 2014Assignee: Samsung Electro-Mechanics Co., LtdInventors: Chang Hyun Lim, Young Ki Lee, Kwang Soo Kim, Seog Moon Choi
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Publication number: 20140049293Abstract: A three-dimensional (3D) gate driver integrated circuit includes a high-side integrated circuit stacked on a low-side integrated circuit where the high-side integrated circuit and the low-side integrated circuit are interconnected using through-silicon vias (TSV). As thus formed, the high-side integrated circuit and the low-side integrated circuit can be formed without termination regions and without buried layers.Type: ApplicationFiled: August 17, 2012Publication date: February 20, 2014Applicant: ALPHA & OMEGA SEMICONDUCTOR, INC.Inventor: Shekar Mallikarjunaswamy
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Publication number: 20140042601Abstract: One aspect provides an integrated circuit (IC) packaging assembly that comprises a substrate having conductive traces located thereon, wherein the signal traces are located in an IC device region and the power traces are located in a wafer level fan out (WLFO) region located lateral the IC device region. This embodiment further comprises a first IC device located on a first side of the substrate within the IC device region and that contacts the signal traces in the IC device region. A second IC device is located on a second side of the substrate opposite the first side and overlaps the IC device region and the WLFO region. The second IC device contacts a first portion of the signal traces in the IC device region and contacts a first portion of the power traces in the WLFO region.Type: ApplicationFiled: August 10, 2012Publication date: February 13, 2014Applicant: LSI CorporationInventor: Donald E. Hawk
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Publication number: 20140017852Abstract: A method for flip chip stacking includes forming a cavity wafer comprising a plurality of cavities and a pair of corner guides, placing a through-silicon-via (TSV) interposer with solder bumps coupled to a surface of the TSV interposer on the cavity wafer, such that the solder bumps are situated in the plurality of cavities and the TSV interposer is situated between the pair of corner guides, placing an integrated circuit (IC) die on another surface of the TSV interposer, such that the IC die, the TSV interposer, and the solder bumps form a stacked interposer unit, removing the stacked interposer unit from the cavity wafer, and bonding the solder bumps of the stacked interposer unit to an organic substrate such that the stacked interposer unit and the organic substrate form a flip chip.Type: ApplicationFiled: July 12, 2012Publication date: January 16, 2014Applicant: Xilinx, IncInventors: Woon-Seong Kwon, Suresh Ramalingam
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Publication number: 20140009992Abstract: Embodiments of the invention provide an integrated circuit system, which includes a first supporting substrate and a second supporting substrate, a logic chip disposed between the first supporting substrate and the second supporting substrate, and a plurality of memory stacks disposed adjacent to one another on a surface of the logic chip. The logic chip is separated from the first supporting substrate and the second supporting substrate by a distance such that at least a portion of a first memory stack in the plurality of memory stacks extending outwards past a first side edge of the logic chip is supported by the first supporting substrate, and at least a portion of a second memory stack in the plurality of memory stacks extending outwards past a second side edge of the logic chip that is opposite to the first side edge is supported by the second supporting substrate.Type: ApplicationFiled: July 6, 2012Publication date: January 9, 2014Inventor: John W. POULTON
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Publication number: 20140001567Abstract: Systems and methods are disclosed for processing radio frequency (RF) signals using one or more FET transistors disposed on or above a high-resistivity region of a substrate. The substrate may include bulk silicon, at least a portion of which has high-resistivity characteristics. For example, the bulk substrate may have a resistivity greater than 500 Ohm*cm, such as around 1 kOhm*cm. In certain embodiments, one or more of the FET devices are surrounded by a low-resistivity implant configured to reduce effects of harmonic and other interference.Type: ApplicationFiled: June 28, 2012Publication date: January 2, 2014Applicant: SKYWORKS SOLUTIONS, INC.Inventor: Michael Joseph McPartlin
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Publication number: 20140001612Abstract: System and method for providing a multiple die interposer structure. An embodiment comprises a plurality of interposer studs in a molded interposer, with a redirection layer on each side of the interposer. Additionally, the interposer studs may be initially attached to a conductive mounting plate by soldering or wirebond welding prior to molding the interposer, with the mounting plate etched to form one of the redirection layers. Integrated circuit dies may be attached to the redirection layers on each side of the interposer, and interlevel connection structures used to mount and electrically connect a top package having a third integrated circuit to the interposer assembly.Type: ApplicationFiled: June 29, 2012Publication date: January 2, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Hua Yu, Mirng-Ji Lii, Hao-Yi Tsai, Jui-Pin Hung, Chien-Hsun Lee, Kai-Chiang Wu
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Publication number: 20130328179Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a package substrate having a warpage-compensation zone with a substrate-interior layer exposed from a top substrate-cover, and the warpage-compensation zone having contiguous exposed portion of the substrate-interior layer over corner portions of the package substrate; connecting an integrated circuit die to the package substrate with an internal interconnect; and forming an encapsulation over the integrated circuit die, with the encapsulation directly on the substrate-interior layer in the warpage-compensation zone.Type: ApplicationFiled: June 7, 2012Publication date: December 12, 2013Inventors: MinJung Kim, DaeSik Choi, MinWook Yu, YiSu Park
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Patent number: 8586983Abstract: A semiconductor chip includes a semiconductor chip body having a first surface on which pad parts are formed and an opposing second surface. Through-electrodes may be connected to the pad parts and formed to pass through the semiconductor chip body. Determination units may be connected to the through-electrodes and may be enabled to determine whether the pad parts and the through-electrodes are electrically connected with each other.Type: GrantFiled: December 29, 2010Date of Patent: November 19, 2013Inventor: Kwon Whan Han
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Patent number: 8586465Abstract: A method for preparing a die for packaging is disclosed. A die having first and second major surfaces is provided. Vias and a mask layer are formed on the first major surface of the die. The mask includes mask openings that expose the vias. The mask openings are filled with a conductive material. The method includes reflowing to at least partially fill the vias and contact openings to form via contacts in the vias and surface contacts in the mask openings.Type: GrantFiled: June 5, 2008Date of Patent: November 19, 2013Assignee: United Test and Assembly Center LtdInventors: Hao Liu, Yi Sheng Anthony Sun, Ravi Kanth Kolan, Chin Hock Toh
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Patent number: 8587088Abstract: A die package having a vertical stack of dies and side-mounted circuitry and methods for making the same are disclosed, for use in an electronic device. The side-mounted circuitry is mounted to a vertical surface of the stack, as opposed to a top surface or adjacent of the stack to reduce the volume of the NVM package.Type: GrantFiled: February 17, 2011Date of Patent: November 19, 2013Assignee: Apple Inc.Inventor: Nicholas Seroff
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Publication number: 20130302935Abstract: A self-assembly apparatus for assembling a plurality of devices with a predetermined aspect ratio is provided. The self-assembly apparatus includes a guiding element, a vibration device, and a magnetic field inducing device. The guiding element has a mesh structure. The vibration device is coupled to the guiding element and configured to vibrate the guiding element. The magnetic field inducing device is disposed below the guiding element and configured to generate a time-varying magnetic field to rotate each of the devices. Through a collective effect of the vibration of the guiding element, the time-varying magnetic field, and the self-gravity of each of the devices, the devices are positioned on a plate between the guiding element and the magnetic field inducing device through the mesh structure.Type: ApplicationFiled: July 17, 2012Publication date: November 14, 2013Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Ming-Ji Dai, Chun-Kai Liu, Heng-Chieh Chien, Li-Ling Liao, Ker-Win Wang, Yen-Lin Tzeng, Yan-Bo Lin
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Patent number: 8580596Abstract: The present invention relates to a method of forming a micro cavity having a micro electrical mechanical system (MEMS) in a process, such as a CMOS process. MEMS resonators are being intensively studied in many research groups and some first products have recently been released. This type of device offers a high Q-factor, small size, high level of integration and potentially low cost. These devices are expected to replace bulky quartz crystals in high-precision oscillators and may also be used as RF filters. The oscillators can be used in time-keeping and frequency reference applications such as RF modules in mobile phones, devices containing blue-tooth modules and other digital and telecommunication devices.Type: GrantFiled: April 10, 2009Date of Patent: November 12, 2013Assignee: NXP, B.V.Inventors: Petrus H. C. Magnee, Jan Jacob Koning, Jozef T. M. Van Beek
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Publication number: 20130270682Abstract: Methods and apparatus for package on package structures having stud bump through via interconnections. A structure includes an interconnect layer having a plurality of through via assemblies each including at least one stud bump are formed on conductive pads; and encapsulant surrounding the through via assembly, a first redistribution layer formed over a surface of the encapsulant and coupled to the through via assemblies and carrying connectors, and a second redistribution layer over interconnect layer at the other end of the through via assemblies, the through via assemblies extending vertically through the interconnect layer. In an embodiment the interconnect layer is mounted using the connectors to a lower package substrate to form a package on package structure. A first integrated circuit device may be mounted on the second redistribution layer of the interconnect layer. Methods for forming the interconnect layer and the package on package structures are disclosed.Type: ApplicationFiled: April 11, 2012Publication date: October 17, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yen-Chang Hu, Ching-Wen Hsiao, Chih-Hua Chen, Chen-Shien Chen, Tin-Hao Kuo
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Patent number: 8546193Abstract: A semiconductor device has a plurality of bumps formed over a carrier. A semiconductor die is mounted to the carrier between the bumps. A penetrable film encapsulant layer having a base layer, first adhesive layer, and second adhesive layer is placed over the semiconductor die and bumps. The penetrable film encapsulant layer is pressed over the semiconductor die and bumps to embed the semiconductor die and bumps within the first and second adhesive layers. The first adhesive layer and second adhesive layer are separated to remove the base layer and first adhesive layer and leave the second adhesive layer around the semiconductor die and bumps. The bumps are exposed from the second adhesive layer. The carrier is removed. An interconnect structure is formed over the semiconductor die and second adhesive layer. A conductive layer is formed over the second adhesive layer electrically connected to the bumps.Type: GrantFiled: November 2, 2010Date of Patent: October 1, 2013Assignee: STATS ChipPAC, Ltd.Inventors: Byung Tai Do, Reza A. Pagaila, Linda Pei Ee Chua
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Publication number: 20130249065Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a leadframe having a mounting region; applying a mounting structure in the mounting region; mounting an integrated circuit die on the mounting structure; forming an encapsulation on the integrated circuit die and having an encapsulation cavity, the encapsulation cavity shaped by the mounting structure; forming a lead having a lead protrusion from the leadframe, the lead protrusion below a horizontal plane of the integrated circuit die; and removing the mounting structure for exposing the integrated circuit die.Type: ApplicationFiled: March 20, 2012Publication date: September 26, 2013Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua
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Publication number: 20130249117Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a circuit substrate having an active side opposite to an inactive portion; attaching a nonconductive cover to the active side; forming a separation-gap partially cutting into the nonconductive cover and the circuit substrate to a kerf depth; attaching a back-grinding tape to the nonconductive cover; removing a portion of the inactive portion; and exposing the nonconductive cover by removing the back-grinding tape.Type: ApplicationFiled: March 21, 2012Publication date: September 26, 2013Inventors: Hun Teak Lee, DaeWook Yang, Yeongbeom Ko
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Publication number: 20130241053Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; forming a conductive post on the substrate, the conductive post includes a vertical side; attaching an integrated circuit to the substrate; and forming an encapsulant including a molded cavity, the vertical side circumscribed by and exposed within the molded cavity from the encapsulant.Type: ApplicationFiled: March 16, 2012Publication date: September 19, 2013Inventors: KyungHoon Lee, DaeSik Choi, Sooyoung Lee
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Patent number: 8525278Abstract: A method and device having chip scale MEMS packaging is described. A first substrate includes a MEMS device and a second substrate includes an integrated circuit. The frontside of the first substrate is bonded to the backside of the second substrate. Thus, the second substrate provides a cavity to encase, protect or operate the MEMS device within. The bond may provide an electrical connection between the first and second substrate. In an embodiment, a through silicon via is used to carry the signals from the first substrate to an I/O connection on the frontside of the second substrate.Type: GrantFiled: August 19, 2011Date of Patent: September 3, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Hua Chu, Chung-Hsien Lin
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Patent number: 8518796Abstract: A system and method for connecting semiconductor dies is provided. An embodiment comprises connecting a first semiconductor die with a first width to a second semiconductor die with a larger second width and that is still connected to a semiconductor wafer. The first semiconductor die is encapsulated after it is connected, and the encapsulant and first semiconductor die are thinned to expose a through substrate via within the first semiconductor die. The second semiconductor die is singulated from the semiconductor wafer, and the combined first semiconductor die and second semiconductor die are then connected to another substrate.Type: GrantFiled: January 9, 2012Date of Patent: August 27, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Fa Chen, Chen-Hua Yu, Sen-Bor Jan
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Publication number: 20130181228Abstract: First chip main surfaces of first semiconductor chips are bonded to a heat spreader, and second chip main surfaces of the first semiconductor chips are bonded to a first electrode. First chip main surfaces of second semiconductor chips are bonded to a heat spreader, and second chip main surfaces of the second semiconductor chips are bonded to a first electrode. A plurality of electrodes are provided by a lead frame. An insulating member is provided on a side opposite to the chips when viewed from the heat spreader. An insulating substrate is provided on a side opposite to the chips when viewed from the first electrodes.Type: ApplicationFiled: September 14, 2012Publication date: July 18, 2013Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Osamu USUI, Naoki YOSHIMATSU, Masao KIKUCHI
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Patent number: 8476111Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate having a through hole; mounting an integrated circuit in the through hole, the integrated circuit having an inactive side and a vertical side; connecting a first interconnect in direct contact with the integrated circuit and the substrate; applying a wire-in-film adhesive around and above the integrated circuit leaving a portion of the vertical side and the inactive side exposed and covering a portion of the first interconnect; and mounting a chip above the integrated circuit and in direct contact with the wire-in-film adhesive.Type: GrantFiled: June 16, 2011Date of Patent: July 2, 2013Assignee: Stats Chippac Ltd.Inventors: NamJu Cho, HeeJo Chi, HanGil Shin
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Patent number: 8470642Abstract: Methods and devices for multi-chip stacks are shown. A method is shown that assembles multiple chips into stacks by stacking wafers prior to dicing into individual chips. Methods shown provide removal of defective chips and their replacement during the assembly process to improve manufacturing yield.Type: GrantFiled: July 9, 2010Date of Patent: June 25, 2013Assignee: Micron Technology, Inc.Inventor: Paul A. Farrar
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Patent number: 8471376Abstract: Embodiments of the present disclosure provide a substrate, one of either a semiconductor die or an interposer disposed on the substrate, the semiconductor die or the interposer having a first surface attached to the substrate and a second surface that is opposite to the first surface, one or more interconnect structures formed on the second surface of the semiconductor die or the interposer, a mold compound formed to substantially encapsulate the semiconductor die or the interposer, and one or more vias formed in the mold compound to facilitate coupling the one or more interconnect structures with another component. Other embodiments may be described and/or claimed.Type: GrantFiled: May 6, 2010Date of Patent: June 25, 2013Assignee: Marvell International Ltd.Inventors: Shiann-Ming Liou, Albert Wu