Abstract: Disclosed herein is a method of positioning and placing an integrated circuit on a printed circuit board. The integrated circuit comprises first geometrical elements. The first geometrical elements are of one or more predefined shapes and are located on one or more predefined surfaces of the integrated circuit. The printed circuit board comprises second geometrical elements. The second geometrical elements are shaped to accommodate the first geometrical elements. The first geometrical elements are designed to fit into the second geometrical elements. The first geometrical elements are positioned and placed over the second geometrical elements. The first geometrical elements come in contact with the second geometrical elements at two or more points. The positioning and placement of the first geometrical elements over the second geometrical elements limits displacement of connections of the integrated circuit from the printed circuit board.

Abstract: Various apparatuses and methods for forming integrated circuit packages are described. One aspect of the invention pertains to a wafer level method for packaging micro-systems. A substrate prefabricated with metal vias can be provided. The substrate can also be made by forming holes in a substrate and electroplating an electrically conductive material into the holes to form the vias. Multiple microsystems are formed on a top surface of the substrate. Each microsystem is formed to include multiple layers of planarizing, photo-imageable epoxy, one or more interconnect layers and an integrated circuit. Each interconnect layer is embedded in an associated epoxy layer. The integrated circuit is positioned within at least an associated epoxy layer. The interconnect layers of the microsystems are formed such that at least some of the interconnect layers are electrically coupled with one or more of the metal vias in the substrate.

Abstract: In one aspect, an integrated circuit package composed of a plurality of immediately adjacent stacked layers of cured, planarizing, photo-imageable dielectric is described. At least one interconnect layer is provided between a pair of adjacent dielectric layers. An integrated circuit is positioned within one or more of the dielectric layers such that at least one of the dielectric layers extends over the active surface of the integrated circuit. The integrated circuit is electrically coupled with I/O pads on a surface of the package at least in part through the interconnect layer or electrically conductive vias. In particular embodiments, the package can include thermal pipes, a heat sink, multiple integrated circuits, interconnect layers, conductive vias that electrically connect different components of the package and/or passive devices. In some specific embodiments, the dielectric layers are formed from a suitable epoxy such as SU-8 type.

Abstract: An integrated transistor module includes a lead frame that defines at least one low-side land and at least one high-side land. A stepped portion of the lead frame mechanically and electrically interconnects the low-side and high-side lands. A low-side transistor is mounted upon the low-side land with its drain electrically connected to the low-side land. A high-side transistor is mounted upon the high-side land with its source electrically connected to the high-side land.

Abstract: In a method for fabricating a flip-chip light emitting diode device, epitaxial layers are deposited on a sapphire growth substrate to produce an epitaxial wafer. A plurality of light emitting diode devices are fabricated on the epitaxial wafer. The epitaxial wafer is diced to generate a device die. The device die is flip chip bonded to a mount. The flip chip bonding includes securing the device die to the mount by bonding at least one electrode of the device die to at least one bonding pad of the mount. Subsequent to the flip chip bonding, the growth substrate of the device die is removed via the application of laser light.

Abstract: A semiconductor package includes a substrate, a chip, an interposer and a molding compound. The chip is electrically connected to the upper surface of the substrate. The interposer is disposed on the chip, and electrically connected to the upper surface of the substrate. The interposer includes an embedded component and a plurality of electric contacts, wherein the embedded component is located between the upper and lower surfaces of the interposer, and the electric contacts are located on the upper surface of the interposer. The molding compound seals the chip and covers the upper surface of the substrate and the lower surface of the interposer.

Abstract: A method of manufacture of an integrated circuit packaging system includes: conductively bonding a first surface of a transposer to an inner end of a lead separate from the transposer; conductively bonding a die to the first surface of the transposer; and encapsulating the inner end with a mold compound having a bottom mold surface that is exposed and is coplanar with a surface of the transposer opposite the first surface.

Abstract: A method for fabricating ICs including via-first through substrate vias (TSVs) and ICs and electronic assemblies therefrom. A substrate having a substrate thickness including a top semiconductor surface and a bottom surface is provided including at least one embedded TSV including a dielectric liner and an electrically conductive filler material formed on the dielectric liner. A portion of the bottom surface of the substrate is mechanically removed to approach but not reach the embedded TSV tip. A protective substrate layer having a protective layer thickness remains over the tip of the embedded TSV after the mechanical removing. Chemical etching exclusive of mechanical etching for removing the protective substrate layer is used form an integral TSV tip that has an exposed tip portion that generally protrudes from the bottom surface of the substrate. The chemical etching is generally a three step chemical etch.

Abstract: A manufacturing method of a semiconductor device comprising the steps of: affixing a die attach film and a dicing film to a back surface of a semiconductor wafer: thereafter dicing the semiconductor wafer and the die attach film to divide the semiconductor wafer into a plurality of semiconductor chips: thereafter pulling the dicing film from the center toward the outer periphery of the dicing film with a first tensile force to cut the die attach film chip by chip; and thereafter picking up the semiconductor chips together with the die attach film while pulling the dicing film from the center toward the outer periphery of the dicing film with a second tensile force smaller than the first tensile force.

Abstract: A semiconductor die package is disclosed. It includes a leadframe structure comprising a first die attach pad and a second die attach pad. A plurality of leads extend from the first and second die attach pads. The plurality of leads includes at least a first control lead and a second control lead. A first semiconductor die including a first device is mounted on the first die attach pad, and a second semiconductor die has a second device is mounted on the second die attach pad. A housing is provided in the semiconductor die package and protects the first and second dies. The housing may have an exterior surface and at least partially covers the first semiconductor die and the second semiconductor die. The first control lead and the second control lead are at opposite sides of the semiconductor die package.

Abstract: A semiconductor package includes a first semiconductor chip, a second semiconductor chip, a first substrate, a second substrate and a metal cap. The chips are electrically connected to the first substrate, the second substrate is disposed between the chips, and the chips and the second substrate are disposed within the metal cap.

Abstract: A conductive layer in an integrated circuit is formed as a sandwich having multiple sublayers, including at least one sublayer of oriented carbon nanotubes. The conductive layer sandwich preferably contains two sublayers of carbon nanotubes, in which the carbon nanotube orientation in one sublayer is substantially perpendicular to that of the other layer. The conductive layer sandwich preferably contains one or more additional sublayers of a conductive material, such as a metal. In one embodiment, oriented carbon nanotubes are created by forming a series of elongated parallel catalyst strips on a horizontal surface, and growing carbon nanotubes from the catalyst in the presence of a directional flow of reactant gases.

Abstract: A packaging assembly (30), such as a ball grid array package, is formed which distributes power across an interior region of an integrated circuit die (52) by using an encapsulated patterned leadframe conductor (59) that is disposed over the die (52) and bonded to a plurality of bonding pads (45) formed in a BGA carrier substrate (42) and in the interior die region, thereby electrically coupling the interior die region to an externally provided reference voltage.

Abstract: An integrated-circuit device is provided, which comprises a rigid substrate island having a main substrate surface with a circuit region circuit elements and at least one fold structure. The fold structure is attached to the substrate island and is unfoldable from a relaxed, folded state to a strained unfolded state. The fold structure contains at least one passive electrical component. The fold structure further has in its folded state at least one surface with an area vector that includes a non-vanishing area-vector component in a direction parallel to the main substrate surface, which area-vector component is diminished or vanishes when deforming the fold structure from the folded into the unfolded state. The fold structure provided by the present invention allows fabricating the integrated-circuit device with small lateral extensions and thus takes up a particularly small amount of chip area, which reduces the cost per device.

Abstract: A semiconductor package is disclosed for packaging two adjacent semiconductor dies atop a circuit substrate. The dies are separated from each other along their longitudinal edges with an inter-die distance. An elevation-adaptive electrical connection connects a top metalized contact of die two to the bottom surface of die one while accommodating for elevation difference between the surfaces. The elevation-adaptive electrical connection includes: a) An L-shaped circuit route that is part of the circuit substrate, extending transversely from a die one longitudinal edge and placing an intermediate contact area next to a die two transverse edge. b) An interconnection plate connecting the top metalized contact area of die two with the intermediate contact area while being formed to accommodate for elevation difference between the contact areas.

Abstract: An integrated circuit (IC) module (20) includes a ground plane (22) having adjoining cutouts (30, 32). The cutout (32) defines a critical signal pathway (38). A device (24) is positioned in the cutout (30) and a device (26) is positioned outside of the cutout (30) adjacent to the cutout (32). An electrical interconnect (56) positioned in the critical signal pathway (38) interconnects the device (24) with the device (26). A method (60) of packaging the IC module (20) entails encapsulating the ground plane (22) and devices (24, 26) in a packaging material, and forming conductive vias (92) in the packaging material (84) that extend between the ground plane (22) and an exterior surface (94) of the packaging material (84). The conductive vias (92) surround the device (24) and cutout (32) to protect again electromagnetic interference and to provide guided signal pathways for high frequency signals on electrical interconnect (56).

Abstract: The present invention discloses a multi-die package which facilitates heat dissipation for a high power consumption die. In the package, part of the lead frame is bent so as to be exposed at the surface of the package. On the opposite side of the exposed surface, a high power consumption die is attached. The other die with lower power consumption is not at the surface of the multi-die package.

Abstract: The invention concerns a method for preparing a thin layer (28) or a chip to be transferred onto another substrate, this method including the realization, above the surface of said thin layer or said chip, of at least one layer, called adhesive layer (25), and of at least one layer, called first barrier layer (22), the adhesive layer being made of a material of which etching presents selectivity in relation to the material of the barrier layer.

Abstract: In a method for fabricating a flexible pixel array substrate, first, a release layer is formed on a rigid substrate. Next, on the release layer, a polymer film is formed, the adhesive strength between the rigid substrate and the release layer being higher than that between the release layer and the polymer film. The polymer film is formed by spin coating a polymer monomer and performing a curing process to form a polymer layer. Afterwards, a pixel array is formed on the polymer film. The polymer film with the pixel array formed thereon is separated from the rigid substrate.

Abstract: An electronic package includes a first layer having a first surface, the first layer includes a first device having a first electrical node, and a first contact pad in electrical communication with the first electrical node and positioned within the first surface. The package includes a second layer having a second surface and a third surface, the second layer includes a first conductor positioned within the second surface and a second contact pad positioned within the third surface and in electrical communication with the first conductor. A first anisotropic conducting paste (ACP) is positioned between the first contact pad and the first conductor to electrically connect the first contact pad to the first conductor such that an electrical signal may pass therebetween.

Abstract: A method of forming a photovoltaic device on a substrate, especially an opaque substrate. The method includes forming a photovoltaic material on a substrate and removing the substrate. The method may include patterning the photovoltaic material to form a plurality of photovoltaic devices and configuring the devices in series to achieve monolithic integration. The method may include forming additional layers on the substrate, such as one or more of a protective material, a transparent conductor, a back conductor, an adhesive layer, and a laminate support layer. When the substrate is opaque, the method provides the option of ordering the layers so that a transparent conductor is formed before the back reflector of a photovoltaic stack. This ordering of layers facilitates monolithic integration and the ability to remove the substrate allows the earlier-formed transparent conductor to serve as the point of incidence for receiving the light that excites the photovoltaic material.

Abstract: A first semiconductor chip and a second semiconductor chip are provided with a matching pair of hydrophilic top surfaces each including a matched set of conductive contact structures. In one embodiment, the first semiconductor chip, the second semiconductor chip, or both is provided with a mesa of which the periphery coincides with the shape of a hydrophilic top surface. In another embodiment, the first semiconductor chip, the second semiconductor chip, or both is provided with a peripheral hydrophobic top surface that laterally surrounds a hydrophilic top surface. Prior to vertical stacking, a polar liquid coats the hydrophilic top surface of a first semiconductor chip. When a second semiconductor chip is placed on the polar liquid, the matching shapes of two hydrophilic surfaces are self-aligned by moving the second semiconductor chip as needed.

Abstract: A multichip discrete package with a leadframe having a plurality of leads and a first die attach pad (DAP), the first DAP having side portions that extend above the first DAP, a first discrete die bonded to the first DAP, at least a first wirebond which forms an electrical connections between the first discrete die and a first selected one of the plurality of leads, a metal plate attached to tops of the side portions forming a second DAP, a second discrete die bonded to the second DAP, at least a second wirebond which forms an electrical connections between the second discrete die and a second selected one of the leads; and encapsulating material formed around the first and second die and the first and second DAPs.

Abstract: An electronic package includes a first layer having a first surface, the first layer includes a first device having a first electrical node, and a first contact pad in electrical communication with the first electrical node and positioned within the first surface. The package includes a second layer having a second surface and a third surface, the second layer includes a first conductor positioned within the second surface and a second contact pad positioned within the third surface and in electrical communication with the first conductor. A first anisotropic conducting paste (ACP) is positioned between the first contact pad and the first conductor to electrically connect the first contact pad to the first conductor such that an electrical signal may pass therebetween.

Abstract: An apparatus comprises a first chip layer comprising a first component coupled to a first side of a first flex layer, the first component comprising a plurality of electrical pads. The first chip layer also comprises a first plurality of feed-thru pads coupled to the first side of the first flex layer and a first encapsulant encapsulating the first component, the first encapsulant having a portion thereof removed to form a first plurality of cavities in the first encapsulant and to expose the first plurality of feed-thru pads by way of the first plurality of cavities.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming an encapsulation surrounding an integrated circuit having an inactive side and an active side exposed; forming a hole through the encapsulation with the hole not exposing the integrated circuit; forming a through conductor in the hole; and mounting a substrate with the integrated circuit surrounded by the encapsulation with the active side facing the substrate.

Abstract: A manufacturing method for rigid-flexible multi-layer printed circuit board including: a flexible substrate of which circuits are formed on both sides and which is bendable; a rigid substrate which is laminated on the flexible substrate and circuits are formed on both sides and a cavity within which a semiconductor chip is mounted is formed; and a bonding sheet adhering the flexible substrate and the rigid substrate and having a insulating property. When the same numbers of the semiconductor chips are mounted or the POP is embodied, the whole thickness of the package can be lower. Also, two more semiconductor chips can be mounted using the space as the thickness of the core layer, and the structure impossible when the number of semiconductor chip mounted on the bottom substrate becomes two from one in conventional technology can be embodied.

Abstract: A method of making a package substrate includes providing a cladding sheet comprising a first metal layer, a second metal layer and an intermediate layer between the first and second metal layers; etching away a portion of the first metal layer to expose a portion of the intermediate layer thereby forming a metal island body; laminating a first copper clad on the cladding sheet comprising a first copper foil and a first insulating layer; patterning the first copper foil to form a first circuit trace; patterning the second metal layer to form a second circuit trace; removing the metal island body to form a cavity in the first insulating layer; and removing the intermediate layer from bottom of the cavity.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a base package having a base interposer; forming an intermediate package having an intermediate interposer and an intermediate package embedded link trace, the intermediate package embedded link trace being encapsulated in an intermediate package mold compound; forming a cap package having a cap interposer; and connecting the intermediate package to the cap package and the base package using the intermediate package embedded link trace.

Abstract: An apparatus for an integrated module. A silicon carrier with through-silicon vias has a plurality of die connected to a top side of the silicon carrier. In addition, a substrate is connected to a bottom side of the silicon carrier. The substrate is coupled to the plurality of die via the through-silicon vias.

Abstract: An electronic device includes a stack of electronic components and connecting elements. The component stack includes two components stacked one on top of another by their top sides. Contact areas are arranged on the top sides of the components, and the contact areas include external contact structures as connecting elements. The external contact structures on the contact areas include rib and/or trench structures oriented in such a way that the rib and/or trench structures of the contact areas of the components stacked one on top of another cross or intersect each other.

Abstract: A semiconductor device which stores a plurality of semiconductor chips, having planar sizes which differ, in the same sealing body in a state in which they are accumulated via an insulating film which has an adhesive property. In the semiconductor device, the thickness of DAF of the back surface of the uppermost semiconductor chip with which the control circuit is formed is thicker than each of DAF of the back surface of the lower layer semiconductor chip with which the memory circuit is formed.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a flip chip die, having a backside protrusion; mounting a wire bond die on the flip chip die, adjacent to the backside protrusion; and mounting an internal stacking module over the backside protrusion and the wire bond die.

Abstract: An electronic device and a method of packaging an electronic device are disclosed. In one embodiment, the electronic device can include a first die. The electronic device can also include a dielectric layer defining a first opening. The first die can be disposed within the first opening. Further, the electronic device can include an encapsulating material disposed adjacent to the first die. The encapsulating material can have a different composition as compared to the dielectric layer. In a particular embodiment, the electronic device can also include an electrically conductive carrier contacting the dielectric layer and the encapsulating material.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a first board-on-chip-structure having a first integrated circuit die mounted over a substrate and the substrate having a substrate cavity; mounting a second board-on-chip-structure over the first board-on-chip-structure, the second board-on-chip-structure having a second integrated circuit die mounted under an interposer and the interposer having an interposer cavity; connecting the first board-on-chip-structure to the second board-on-chip-structure with an internal interconnect; and encapsulating the first board-on-chip-structure, the second board-on-chip-structure, and the internal interconnect with an encapsulation.

Abstract: A panel for the production of electronic components is disclosed. The components have a substantially planar semiconductor chip with chip through-contacts which are provided with electrically conductive material. A rewiring region is subdivided into an insulating layer and also a first rewiring arranged therein, the rewiring projecting laterally beyond the side edge of the planar semiconductor chip. The rewiring has external contacts for electrical connections toward the outside. The panel provides a filling layer made of plastic, which encapsulates the semiconductor chip in a side region between the chip front side and the chip rear side and which is connected to the rewiring region.

Abstract: A semiconductor die package is provided. The semiconductor die package includes a plurality of dies arranged in a stacked configuration. Through-silicon vias are formed in the lower or intermediate dies to allow electrical connections to dies stacked above. The lower die is positioned face up and has redistribution lines electrically coupling underlying semiconductor components to the through-silicon vias. The dies stacked above the lower die may be oriented face up such that the contact pads are facing away from the lower die or flipped such that the contact pads are facing the lower die. The stacked dies may be electrically coupled to the redistribution lines via wire bonding or solder balls. Additionally, the lower die may have another set of redistribution lines on an opposing side from the stacked dies to reroute the vias to a different pin-out configuration.

Abstract: A cavity or die down ball grid array package includes an interposer substrate structure attached to the die. In an example, the interposer substrate reduces the interconnect length from a board to which the package mounts to power and ground pads on a top layer of the semiconductor or integrated circuit (IC) die. In this example, the interposer substrate also removes the requirement that power and ground pads be located on a periphery of the die. Power and ground pads can be located in an interior region on a top metal layer where they can be interconnected to the interposer substrate using electrically conductive bumps or wire bond(s).

Abstract: A layered chip package has a main body including a plurality of pairs of layer portions, and wiring disposed on a side surface of the main body. Each layer portion includes a semiconductor chip. The plurality of pairs of layer portions include at least one specific pair of layer portions consisting of a first-type layer portion and a second-type layer portion. The first-type layer portion includes a plurality of electrodes each connected to the semiconductor chip and each having an end face located at the side surface of the main body on which the wiring is disposed, whereas the second-type layer portion does not include such electrodes.

Abstract: A semiconductor package includes a substrate having contacts, and a discrete component on the substrate in electrical communication with the contacts. The package also includes a semiconductor die on the substrate in electrical communication with the contacts, and a die attach polymer attaching the die to the substrate. The die includes a recess, and the discrete component is contained in the recess encapsulated in the die attach polymer. A method for fabricating the package includes the steps of: attaching the discrete component to the substrate, placing the die attach polymer on the discrete component and the substrate, pressing the die into the die attach polymer to encapsulate the discrete component in the recess and attach the die to the substrate, and then placing the die in electrical communication with the discrete component. An electronic system includes the semiconductor package mounted to a system substrate.

Abstract: A method of manufacturing an array of semiconductor devices comprises providing a first carrier having multiple chip alignment regions. Multiple chips are placed over the multiple chip alignment regions. Then, alignment of the chips to the multiple chip alignment regions is obtained. The multiple chips are then placed on a second carrier. The first carrier is detached from the multiple chips. An encapsulation material is applied to the multiple chips to form an encapsulated array of semiconductor chips. The second carrier is then detached from the encapsulated array of semiconductor devices.

Abstract: A method and device relating the electrical interconnection of angularly disposed conductive is disclosed. Conventional wire bonding equipment is used to apply a wire ball on a first conductive surface in an electronic assembly. A conductive wire is drawn up vertically and terminated such that the central portion of the wire is proximal the second conductive surface. The electronic assembly is reoriented with respect to the travel of the capillary whereby a stitch bond is defined upon the second conductive surface to define an interconnect wire and a terminal wire portion, which terminal wire portion is removed.

Abstract: A method of fabricating a photonic device comprises the steps of providing a core pattern of waveguide core material (1) on a base layer (3) and applying a cladding layer (2) over the core material 1 and the base layer (3). The height of the surface of the cladding layer (2) over the base layer (3) varies in dependence on the pattern of core material (1). The core pattern is designed with at least two reference regions, each having a width w that is selected to provide a peak of the cladding layer (2) with a predetermined height h1 over each reference region. The core pattern is further designed such that a line between the peaks of the reference regions is higher than any intervening peaks of the cladding layer, whereby the peaks of the reference regions provide a vertical alignment reference.

Abstract: Disclosed are packages for optocouplers and methods of making the same. An exemplary optocoupler comprises a substrate having a first surface and a second surface, a plurality of optoelectronic dice for one or more optocouplers disposed on the substrate's first surface, and a plurality of optoelectronic dice for one or more optocouplers disposed on the substrate's second surface. The substrate may comprise a pre-molded leadframe, and electrical connections between optoelectronic dice on opposite surfaces of the substrate may be made via one or more leads of the leadframe.

Abstract: A semiconductor die includes a semiconductive substrate layer with first and second sides, a metal layer adjacent the second side of the semiconductive substrate layer, one or more active devices in an active layer on the first side of the semiconductive substrate layer; and a passive device in the metal layer in electrical communication with the active layer. The passive device can electrically couple to the active layer with through silicon vias (TSVs).

Abstract: A lead frame includes a welding portion to be welded to other lead frame, and a frame, wherein the welding portion has an island portion provided like an island, and a plurality of connection members which connect the island portion and the frame with each other; and one connection member is provided so that a straight line which connects a connection point of the island portion and one connection member, and a connection point of one connection member and the frame, inclines away from a portion of the outer circumference (edge, for example) of the island portion where the connection member is connected, and also from a portion of the inner circumference (edge, for example) of the frame where the connection member is connected.

Abstract: A semiconductor device of the present invention includes: a plurality of semiconductor chips each having a chip size package structure; and a substrate bonded via an adhesive material to an opposite surface in each of the plurality of semiconductor chips that is opposite to a connection surface that is provided with solder balls (external connection terminals). Thereby, the plurality of semiconductor chips are connected to each other.

Abstract: A semiconductor package and a method for manufacturing the same. The semiconductor package includes a substrate having connection pads formed on one surface thereof, a semiconductor chip having bonding pads formed on one surface thereof to correspond to the connection pads; bumps for electrically connecting the connection pads and the bonding pads with each other, a coating layer located on exposed surface portions of the bonding pads and the connection pads to prevent voids from being formed in spaces between the substrate and the semiconductor chip, and an underfill member filled in the spaces over the coating layer.

Abstract: A reconstituted electronic device including: a first face and a second face; a plurality of individual chips placed perpendicular to the faces, each individual chip carrying, on one of its surfaces, at least one component, tracks, and a connection mechanism that are flush with one or other of the faces of the reconstituted electronic device; and an encapsulant that encapsulates the individual chips.

Abstract: Methods and structures using laser bonding for stacking semiconductor substrates are described. In one embodiment, a method of forming a semiconductor device includes forming a trench in a first substrate, and a bond pad on a second substrate comprising active circuitry. A top surface of the bond pad includes a first material. The first substrate is aligned over the second substrate to align the trench over the bond pad. An electromagnetic beam is directed into the trench to form a bond between the first material on the bond pad and a second material at a bottom surface of the first substrate.