Abstract: A semiconductor device comprises a substrate provided with a doping of a first type, on which an electronic circuit is provided surrounded by a circuit portion of the substrate provided with a doping of a second type; at least one pad for connecting the electronic circuit to an external device outside the substrate, surrounded by a pad portion provided with a doping of the second type; a sensing device comprising a sensor portion of the substrate provided with a doping of the first type, for sensing a parameter forming a measure for a local electrical potential of the substrate; and an evaluation unit connected to the sensing device, for providing an evaluation signal based on a difference between the parameter and a reference value.

Abstract: The present disclosure provides a semiconductor device including: a semiconductor identifier holding portion configured to hold a semiconductor identifier for identifying a semiconductor device; and a control portion configured such that upon elapse of a predetermined time period following receipt of an externally input instruction to hold the semiconductor identifier, the control portion issues an instruction to the semiconductor device immediately downstream of the semiconductor device to hold a semiconductor identifier of the immediately downstream semiconductor device and that during the time period between the point in time at which the externally input instruction is received and the point in time at which the instruction is issued to the immediately downstream semiconductor device to hold the semiconductor identifier thereof, the control portion causes the semiconductor identifier holding portion to hold the externally input identifier.

Abstract: A programmable CMOS device includes a PFET and an NFET that have a common floating gate. Depending on the configuration, the programmable CMOS device can be programmed, erased, and re-programmed repeatedly. The programming, erasure, and/or reprogramming can be effected by injection of electrons and/or holes into the floating gate. The programmable CMOS device can be employed as a fuse or an antifuse, to program a floating gate of another device, and/or to function as a latch. The programmable CMOS device can be formed employing standard logic compatible processes, i.e., without employing any additional processing steps.

Abstract: A method for manufacturing a semiconductor device is disclosed. The method includes forming a shallow trench isolation (STI) region extending in a first direction on a semiconductor substrate, forming a mask layer extending in a second direction that intersects with the first direction on the semiconductor substrate and forming a trench on the semiconductor substrate by using the STI region and the mask layer as masks. In addition, the method includes forming a charge storage layer so as to cover the trench and forming a conductive layer on side surfaces of the trench and the mask layer. Word lines are formed from the conductive layer on side surfaces of the trench that oppose in the first direction by etching. The word lines are separated from each other and extend in the second direction.

Abstract: In one embodiment, a semiconductor device includes a substrate, and a plurality of interconnects provided in the same interconnect layer above the substrate. The device further includes a plurality of insulators provided so as to be buried between the plurality of interconnects. Moreover, the plurality of interconnects include an interconnect group in which 2N or more interconnects are successively arrayed so that correlation coefficients of line edge roughness (LER) between both side surfaces of the respective interconnects are positive, where N is an integer of 4 or more.

Abstract: A semiconductor die has multiple discontinuous conductive segments arranged around a periphery of the semiconductor die, and an electrically insulating barrier within discontinuities between the conductive segments. The conductive segments and the barriers form a mechanically continuous seal ring around the semiconductor die.

Abstract: A system or apparatus for monitoring an Integrated Circuit (IC) chip includes: a sense circuit at least partially constructed on the IC chip and configured to produce one or more sense signals each indicative of a corresponding process-dependent circuit parameter of the IC chip; and a digitizer module configured to produce, responsive to the one or more sense signals, one or more digitized signals each representative of a corresponding one of the sense signals. A controller is configured to determine a value of one or more of the process-dependent circuit parameters based on one or more of the digitized signals.

Abstract: An integrated circuit package system with laminate base includes: a base package including: a laminate substrate strip, an integrated circuit on the laminate substrate strip, a molded cover over the integrated circuit and the laminate substrate strip, and a strip test of the base package; a bare die on the base package; the bare die electrically connected to the laminate substrate strip; and the bare die and the base package encapsulated.

Abstract: A semiconductor device includes a semiconductor chip, a moisture resistant ring provided in the semiconductor chip and having a chamfered flat part in a position corresponding to a corner of the semiconductor chip, and a first monitor pattern formed inside the moisture resistant ring. At least a part of the first monitor pattern is disposed inside an n-sided polygonal area (n is a natural number which is 4 or higher than 4) situated within the moisture resistant ring, and outside a quadrangular area situated inside the n-sided polygonal area. The n-sided polygonal area has a vertex at least at each of a first end and a second end of the chamfered flat part, and the quadrangular area has a vertex at least at a middle point of the chamfered flat part.

Abstract: A wafer level integration module and method for forming are disclosed. A construction includes semiconductor functional device fabrication carried out after interconnect structures are processed on a bare wafer. Interconnect structures are formed in a first side of the wafer. An insulation layer is deposited on the first side of the wafer to insulate walls of the interconnect structures. A conductive layer is deposited on the insulation layer filling the interconnect structures so as to contact the insulation layer on the walls of the interconnect structures. The conductive layer forms interconnection contacts on the first side of the wafer and interconnection vias extending into the wafer. The first conductive layer including the interconnection contacts is exposed on the first side of the wafer and a semiconductor functional device is formed on the first side of the wafer. The semiconductor functional device is interconnected with the interconnection contacts during the fabricating.

Abstract: A packaged electronic device includes a thickness shaped IC die including a top portion, top surface, active circuitry, bottom portion and bottom surface. A cross sectional area of the bottom surface is ?5% less than a cross sectional area of the top surface to provide a protruding lip having a bottom lip surface. A package substrate includes a top substrate surface including substrate bonding sites, a bottom substrate surface, and a die support structure on the top substrate surface having a gap region. The bottom lip surface of the IC die is secured to the die support structure and the bottom surface of the IC die extends below the die support structure into the gap region. Coupling connectors couple the bonding features on the IC die to the substrate bonding sites.

Abstract: An integrated circuit (IC) includes a substrate having a top semiconductor surface and a bottom surface, and integrated circuitry including an analog subcircuit and at least one digital subcircuit formed on the top semiconductor surface. A plurality of through substrate vias (TSVs) extend through the substrate. At least one integrated Faraday shield includes a top and a bottom electrically conducting member that are coupled by the TSVs which surround the analog subcircuit and/or the digital subcircuit. At least one voltage regulator supplies a regulated power supply voltage that is coupled to the integrated Faraday shield that surrounds the analog subcircuit.

Abstract: An improved crack stop structure (and method of forming) is provided within a die seal ring of an integrated circuit die to increase crack resistance during the dicing of a semiconductor wafer. The crack stop structure includes a stack layer (of alternating insulating and conductive layers) and an anchor system extending from the stack layer to a predetermined point below the surface of the substrate. A crack stop trench is formed in the substrate and filled with material having good crack resistance to anchor the stack layer to the substrate.

Abstract: A wafer-bump structure includes a wafer-state semiconductor die, a pre-treatment layer, a first ENIG laminate and at least one pillar bump. The wafer-state semiconductor die includes at least one die pad embedded therein and a passivation layer formed on the wafer-state semiconductor die and the die pad. The passivation layer includes an aperture for allowing access to a portion of the die pad. The pre-treatment layer is formed on the un-covered portion of the die pad. The first ENIG laminate is formed on the pre-treatment layer and an annular portion of the passivation layer around the pre-treatment layer. The pillar bump includes a conductive metal layer and a second ENIG laminate. The conductive metal layer is formed on the first ENIG laminate and another annular portion of the passivation layer around the first ENIG laminate. The second ENIG laminate is formed on the conductive metal layer and another annular portion of the passivation layer around the conductive metal layer.

Abstract: An improved low-temperature absorber, amorphous carbonitride (ACN) with an extinction coefficient (k) of greater than 0.15, and an emissivity of greater than 0.8 is disclosed. The ACN film can also be characterized as having a minimum of hydrocarbon content as observed by FTIR. The ACN film can be used as an effective absorbing layer that absorbs a wide range of electromagnetic radiation from different sources including lasers or flash lamps. A method of forming such an ACN film at a deposition temperature of less than, or equal to, 450° C. is also provided.

Abstract: A multiple integrated circuit chip structure provides interchip communication between integrated circuit chips of the structure with no ESD protection circuits and no input/output circuitry. The interchip communication is between internal circuits of the integrated circuit chips. The multiple integrated circuit chip structure has an interchip interface circuit to selectively connect internal circuits of the integrated circuits to test interface circuits having ESD protection circuits and input/output circuitry designed to communicate with external test systems during test and burn-in procedures. The multiple interconnected integrated circuit chip structure has a first integrated circuit chip mounted to one or more second integrated circuit chips to physically and electrically connect the integrated circuit chips to one another.

Abstract: A semiconductor chip includes a semiconductor chip body having a first surface on which pad parts are formed and an opposing second surface. Through-electrodes may be connected to the pad parts and formed to pass through the semiconductor chip body. Determination units may be connected to the through-electrodes and may be enabled to determine whether the pad parts and the through-electrodes are electrically connected with each other.

Abstract: A semiconductor device manufacturing apparatus is provided with a drawing pattern printing part having a print head which injects a conductive solvent, an insulative solvent and an interface treatment solution. The print head is formed in such a way that desired circuit drawing pattern can be printed on a wafer based on information on the drawing pattern from a wafer testing part, information on the wafer from a storage part and coordinate information from a chip coordinate recognition part. In a semiconductor device manufacturing method according to the present invention, a semiconductor device is manufactured by using the semiconductor device manufacturing apparatus in such a manner that desired circuits are formed through printing process. In the semiconductor device, pad electrodes and so on are formed in such a way that trimming process can be conducted by printing circuit drawing patterns.

Abstract: An integrated circuit device includes a substrate having adjacent first and second regions, and a device isolation structure in the substrate between the first and second regions. The first and second regions of the substrate may respectively include transistors configured to be driven at different operational voltages, and the device isolation structure may electrically separates the transistors of the first region from the transistors of the second region. The device isolation structure includes outer portions immediately adjacent to the first and second regions and an inner portion therebetween. The outer portions of the device isolation structure comprise a material having an etching selectivity with respect to that of the inner portion. Related devices and fabrication methods are also discussed.

Abstract: Embodiments relate to a method for forming reliable interconnects by the use of a device layer that can serve as a barrier or an etch stop layer, among other applications. The device layer is UV resistant in that its dielectric constant and stress remain stable or relatively stable when subjected to UV curing.

Abstract: A package on package structure includes a lower package and an upper package. The lower package includes a first semiconductor chip disposed in a chip region of an upper surface of a first substrate. The upper package includes a second semiconductor chip disposed on an upper surface of a second substrate, and a decoupling capacitor disposed in an outer region of a lower surface of the second substrate. The lower surface of the second substrate opposes the upper surface of the second substrate and faces the upper surface of the first substrate. The plane area of the second substrate is larger than the plane area of the first substrate. The outer region of the lower surface of the second substrate extends beyond a periphery of the first substrate.

Abstract: In a replacement gate approach for forming high-k metal gate electrode structures, electronic fuses may be provided on the basis of a semiconductor material in combination with a metal silicide by using a recessed surface topography and/or a superior selectivity of the metal silicide material during the replacement gate process. For example, in some illustrative embodiments, electronic fuses may be provided in a recessed portion of an isolation region, thereby avoiding the removal of the semiconductor material when replacing the semiconductor material of the gate electrode structures with a metal-containing electrode material. Consequently, the concept of well-established semiconductor-based electronic fuses may be applied together with sophisticated replacement gate structures of transistors.

Abstract: A chip package comprises a first chip having a first side and a second side, wherein said first chip comprises a first pad, a first trace, a second pad and a first passivation layer at said first side thereof, an opening in said first passivation layer exposing said first pad, said first trace being over said first passivation layer, said first trace connecting said first pad to said second pad; a second chip having a first side and a second side, wherein said second chip comprises a first pad at said first side thereof, wherein said second side of said second chip is joined with said second side of side first chip; a substrate joined with said first side of said first chip or with said first side of said second chip; a first wirebonding wire connecting said second pad of said first chip and said substrate; and a second wirebonding wire connecting said first pad of said second chip and said substrate.

Abstract: A semiconductor amplifier is provided comprising, a substrate and one or more unit amplifying cells (UACs) formed on the substrate, wherein each UAC is laterally surrounded by a first lateral dielectric filled trench (DFT) isolation wall extending at least to the substrate and multiple UACs are surrounded by a second lateral DFT isolation wall of similar depth outside the first isolation walls, and further semiconductor regions lying between the first isolation walls when two or more unit cells are present, and/or lying between the first and second isolation walls, are electrically floating with respect to the substrate. This reduces the parasitic capacitance of the amplifying cells and improves the power added efficiency. Excessive leakage between buried layer contacts when using high resistivity substrates is avoided by providing a further semiconductor layer of intermediate doping between the substrate and the buried layer contacts.

Abstract: An object is to provide a method for manufacturing an SOI substrate including a single crystal silicon film whose plane orientation is (100) and a single crystal silicon film whose plane orientation is (110) with high yield. A first single crystal silicon substrate whose plane orientation is (100) is doped with first ions to form a first embrittlement layer. A second single crystal silicon substrate whose plane orientation is (110) is doped with second ions to selectively form a second embrittlement layer. Only part of the first single crystal silicon substrate is separated along the first embrittlement layer by first heat treatment, thereby forming a first single crystal silicon film. A region of the second single crystal silicon substrate, in which the second embrittlement layer is not formed, is removed. Part of the second single crystal silicon substrate is separated along the second embrittlement layer by second heat treatment, thereby forming a second single crystal silicon film.

Abstract: A test circuit that senses a misaligned probe during a test includes a first power control section that senses voltage levels of a plurality of sensing lines and controls power supplied to a lower circuit section provided below a part of a pad group, and a second power control section that selectively provides an internal voltage in response to a sensing result of the first power control section.

Abstract: Provided is a semiconductor chip having a double bump structure. The semiconductor chip may include a semiconductor substrate, a circuit region on a surface of the semiconductor substrate, a pad on the semiconductor substrate and connected to the circuit region, a first bump on the pad, and a second bump on the first bump.

Abstract: The present application relates to the manufacture of Wafer Level Chip Scale Packages (WLCSPs), which are a type of CSP in which the traditional wire bonding arrangements are dispensed with in favor of making direct contact by means of conductive bumps (typically solder balls) to the integrated circuitry. WLCSPs differ from fine pitch Ball Grid Array (BGA) and leadframe based Chip Scale Packages (CSPs) in that most of the packaging process steps are performed at wafer level. A package and method of manufacture are provided which prevent the ingress of light to the internal circuitry of WLCSP packages by providing a substantially opaque coating on the inactive side of the WLCSP packages and at least partially on the sides of WLCSP packages.

Abstract: An electro static discharge protection element being formed by a diode including a well region of a first conductivity type on a surface of a semiconductor substrate, and a first diffusion layer of a second conductivity type in the well region. The first diffusion layer is surrounded by a second diffusion layer of the first conductivity type in the well region. The first diffusion layer has a surface on which a first contact region connected to an input/output terminal is formed. The first diffusion layer has a surface on which a second contact region connected to a reference voltage terminal is formed.

Abstract: A semiconductor substrate capable of detecting operating current of a MOSFET and diode current in a miniaturized MOSFET such as a trench-gate type MOSFET is provided. A semiconductor substrate includes a main current region and a current sensing region in which current smaller than main current flowing in the main current region flows. The main current region has a source electrode disposed on a main surface, the source electrode being in contact with a p-type semiconductor region (body) and an n+-type semiconductor region (source), and the current sensing region has a MOSFET current detecting electrode and a diode current detecting electrode on a main surface, the MOSFET current detecting electrode being in contact with the p-type semiconductor region (body) and the n+-type semiconductor region (source), the diode current detecting electrode being in contact with the p-type semiconductor region (body).

Abstract: An active device array substrate including a substrate, a pixel array, and peripheral circuit is provided. The substrate has a display region and a peripheral region. The pixel array is disposed on the display region of the substrate, wherein the pixel array includes signal lines and pixels, each of the pixels is electrically connected to the signal lines respectively and extends from the display region to the peripheral region. The peripheral circuit is disposed on the peripheral region and includes a testing circuit electrically connected to the signal lines. Additionally, the testing circuit includes shorting bars and connecting conductors, wherein each of the signal lines is electrically connected to one of the shorting bars through one of the connecting connectors respectively, and at least two of the signal lines connected to the same shorting bar are electrically connected to each other through one of the connecting conductors.

Abstract: According to the following disclosure, disclosed is a semiconductor device including: an internal circuit configured to receive and output a signal current; a current mirror unit outputting a copied current corresponding to the signal current; and a test pad from which the copied current is taken out.

Abstract: When forming a trench in a porous low-K dielectric (such as an ILD) of a semiconductor device, a carbon-rich layer is formed in the sidewalls of the trench during trench etching. This carbon-rich layer may protect the trench from being excessively etched, which would otherwise form an undesirable hardmask undercut. The carbon-rich layer may be formed simultaneously with and during the etching process, by increasing the amount of carbon available to be absorbed by the ILD during the trench etching process. The existence of the extra available carbon may slow the etching of the carbon-enriched regions of the dielectric.

Abstract: A semiconductor device including a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls forming a closed loop in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner.

Abstract: A package substrate, a semiconductor package having the same, and a method for fabricating the semiconductor package. The semiconductor package includes a semiconductor chip, a package substrate, and a molding layer. The package substrate provides a region mounted with the semiconductor chip. The molding layer is configured to mold the semiconductor chip. The package substrate includes a first opening portion that provides an open region connected electrically to the semiconductor chip and extends beyond sides of the semiconductor chip to be electrically connected to the semiconductor chip.

Abstract: A semiconductor device includes an isolation region, a semiconductor region, a groove, and an insulating film. The semiconductor region is defined by the isolation region. The groove is in the semiconductor region. The groove has first and second ends. At least one of the first and second ends reaches the isolation region. The insulating film is in the groove.

Abstract: A method for fabricating chip package includes providing a semiconductor chip with a bonding pad, comprising an adhesion/barrier layer, connected to a pad through an opening in a passivation layer, next adhering the semiconductor chip to a substrate using a glue material, next bonding a wire to the bonding pad and to the substrate, forming a polymer material on the substrate, covering the semiconductor chip and the wire, next forming a lead-free solder ball on the substrate, and then cutting the substrate and polymer material to form a chip package.

Abstract: A semiconductor wafer includes a substrate, a first separating structure and a semiconductor stacked layer structure. The substrate has a first surface. The first separating structure is formed on the first surface to divide the first surface into a plurality of independent regions. The minimum area of each of the regions is more than or equal to one square inch. The semiconductor stacked layer structure is disposed on the first surface and the first separating structure. The semiconductor wafer can prevent bowing of the semiconductor wafer during an epitaxial growth process so as to enhance quality of the semiconductor wafer.

Abstract: A double-faced adhesive film including: a supporting film; a first adhesive layer laminated on one surface of the supporting film; and a second adhesive layer laminated on the other surface of the supporting film, wherein the glass transition temperatures, after curing, of the first adhesive layer and the second adhesive layer are each 100° C. or lower, and the first adhesive layer and the second adhesive layer are the layers capable of being formed by a method including the steps of directly applying a varnish to the supporting film and drying the applied varnish.

Abstract: The present invention provides a die bond film for adhering, onto a semiconductor element that is electrically connected to an adherend with a bonding wire, another semiconductor element and that enables loading of the other semiconductor element and improvement in the manufacturing yield of a semiconductor device by preventing deformation and cutting of the bonding wire, and a dicing die bond film. The die bond film of the present invention is a die bond film for adhering, onto a semiconductor element that is electrically connected to an adherend with a bonding wire, another semiconductor element, in which at least a first adhesive layer that enables a portion of the bonding wire to pass through inside thereof by burying the portion upon press bonding and a second adhesive layer that prevents the other semiconductor element from contacting with the bonding wire are laminated.

Abstract: The present invention provides a resinous hollow package that includes a moisture-proof island that is a planar structure disposed below a semiconductor element mounting surface of the resinous hollow package, the semiconductor element mounting surface having an area of 200 mm2 or more and the maximum wave height of a wave curve of 35 ?m or less. The resinous hollow package of the invention has an excellent moisture resistance due to the moisture-proof island included therein. Further, since the flatness of the semiconductor element mounting surface is excellent, decrease in the amount of light in a peripheral portion of an image can be suppressed in a digital single-lens reflex camera or the like with a large solid-state image sensor, even when a wide angle lens is used.

Abstract: An insert module for a test handler includes an insert body and a support frame. The insert body has a receiving space for receiving a semiconductor device. The semiconductor device having connection pads protruding externally from a surface of the semiconductor device. The support frame is formed in an inner side portion of the insert body defining the receiving space to provide a seating surface for contacting and supporting the semiconductor device. The support frame includes a fixing frame and a guide pattern. The fixing frame is inserted into and fixed with the insert body and defines an opening that exposes the semiconductor device. The guide pattern extends from the fixing frame to the inside of the opening to contact the semiconductor device and guide the connection pads.

Abstract: Embodiments of the present invention pertain to the formation of microelectronic structures. Low k dielectric materials need to exhibit a dielectric constant of less than about 2.6 for the next technology node of 32 nm. The present invention enables the formation of semiconductor devices which make use of such low k dielectric materials while providing an improved flexural and shear strength integrity of the microelectronic structure as a whole.

Abstract: Disclosed herein is a semiconductor device, including: a semiconductor substrate; an integrated circuit formed on a first main surface of the semiconductor substrate; a penetrating electrode that penetrates the semiconductor substrate in the thickness direction and has its one end electrically connected to the integrated circuit; a bump electrode formed on a second main surface of the semiconductor substrate and electrically connected to another end of the penetrating electrode; and a test pad electrode formed on the second main surface of the semiconductor substrate and electrically connected to the bump electrode.

Abstract: A positive tone photosensitive composition comprising: (A) an alkali-soluble resin having a phenolic hydroxyl group; (B) a phenol resin modified by a compound having an unsaturated hydrocarbon group containing 4 to 100 carbon atoms; (C) a compound that generates an acid by the action of light; (D) a thermal cross-linker that crosslinks the ingredient (A) and the ingredient (B) by heating; and (E) a solvent.

Abstract: A dielectric layer structure includes an interlayer dielectric (ILD) layer covering at least a metal interconnect structure and a single tensile film. The ILD layer further includes a low-k dielectric layer, and the single tensile film is positioned on the low-k dielectric layer for counteracting at least a part of a stress of the low-k dielectric layer.

Abstract: Provided is a semiconductor device that includes: a base insulating film 25 formed above a silicon substrate 10; a ferroelectric capacitor Q formed on the base insulating film 25; multiple interlayer insulating films 35, 48, and 62, and metal interconnections 45, 58, and 72 which are alternately formed on and above the capacitor Q; and conductive plugs 57 which are respectively formed inside holes 54a provided in the interlayer insulating films 48 and are electrically connected to the metal interconnections 45. In the semiconductor device, a first capacitor protection insulating film 50 is formed on an upper surface of the interlayer insulating film 48 by sequentially stacking a first insulating metal oxide film 50a, an intermediate insulating film 50b having a relative dielectric constant lower than that of the interlayer insulating film 48, and a second insulating metal oxide film 50c; and the holes 54a are also formed in the first capacitor protection insulating film 50.

Abstract: A semiconductor apparatus includes: a substrate of single crystal silicon; a first device formed in a first region of a surface of the substrate; a first interlayer insulating film formed on the substrate; a polycrystalline silicon layer formed in a second region on the first interlayer insulating film; a second device formed in the polycrystalline silicon layer; a second interlayer insulating film formed on the first interlayer insulating film, the second interlayer insulating film covering the polycrystalline silicon layer; and a pad formed in a third region on the second interlayer insulating film. The second region includes at least part of a directly overlying zone of the first region. The third region includes at least part of a region which is the directly overlying zone of the first region and a directly overlying zone of the second region.

Abstract: A semiconductor chip comprises a metal pad exposed by an opening in a passivation layer, wherein the metal pad has a testing area and a bond area. During a step of testing, a testing probe contacts with the testing area for electrical testing. After the step of testing, a polymer layer is formed on the testing area with a probe mark created by the testing probe. Alternatively, a semiconductor chip comprises a testing pad and a bond pad respectively exposed by two openings in a passivation layer, wherein the testing pad is connected to the bond pad. During a step of testing, a testing probe contacts with the testing pad for electrical testing. After the step of testing, a polymer layer is formed on the testing pad with a probe mark created by the testing probe.

Abstract: A metal substrate with an insulation layer has a metallic substrate having at least an aluminum base, and an insulation layer formed on the aluminum base of the metallic substrate. The insulation layer is a anodized film of aluminum that has a porous structure having plural pores and a Martens hardness of 1000 N/mm2 to 3500 N/mm2. A ratio of an average pore size of the plural pores to an average wall thickness of the plural pores ranges from 0.2 to 0.5.