Abstract: A semiconductor device includes a semiconductor substrate including a first surface and a second surface opposite to the first surface, and a through-via penetrating the semiconductor substrate. The through-via has a stacked structure of a first conductive film formed in a portion of the semiconductor substrate closer to the first surface, and a second conductive film formed in a portion of the semiconductor substrate closer to the second surface. An insulating layer is buried inside the semiconductor substrate. The first conductive film is electrically connected to the second conductive film in the insulating layer.

Abstract: A semiconductor device according to an embodiment of the present invention includes a substrate, isolation layers and active regions formed in the substrate, and arranged alternately along a first direction parallel to a surface of the substrate, an inter layer dielectric formed on the isolation layers and the active regions, and having holes for respective contact plugs on the respective active regions, barrier layers formed in the holes, each of the barrier layers being formed on a top surface of an active region exposed in a hole and on one of two side surfaces of the hole, the two side surfaces of the hole being perpendicular to the first direction, and plug material layers formed on the barrier layers in the holes.

Abstract: Provided is a semiconductor device in which a connection between connection terminals and land of the semiconductor device can be checked with the semiconductor device kept in a sound condition, the connection not being allowed to be checked with a semiconductor chip. The semiconductor device of the present invention includes: a package substrate; a semiconductor chip mounted on the package substrate; a first land formed in a first principal surface of the package substrate; a second land formed in a second principal surface of the package substrate; first connection terminals connected to the second land and having the connection thereto not allowed to be checked with the semiconductor chip; a connection interconnection for connecting the first land and the second land; a second connection terminal formed in the second principal surface of the package substrate; and a branch interconnection for connecting the connection interconnection and the second connection terminal.

Abstract: A semiconductor device includes an electrode pad formed above a semiconductor substrate, and being a connecting portion for an external electrical connection; a multilayer body including a plurality of first interconnect layers formed in a plurality of insulating films stacked between the semiconductor substrate and the connecting portion and including an upper interconnect connected to the connecting portion, and a via configured to connect the first interconnect layers; a ring body formed in the plurality of insulating films to surround the multilayer body without interposing space, and including a plurality of second interconnect layers and at least one line via linearly connecting the second interconnect layers; and a lead line electrically connecting the connecting portion to an internal circuit. The multilayer body is connected to the ring body by at least one of the plurality of first interconnect layers. The lead line is connected to the ring body.

Abstract: A chip includes a dummy connector disposed at a top surface of the chip. A seal ring encircles a region directly underlying the dummy connector, with the region overlapping the dummy connector.

Abstract: A stacked semiconductor device includes a first and a second semiconductor device. A first major surface of each of the first and second devices which includes the active circuitry directly face each other. The first major surface of each of the devices includes a beveled edge on at least one edge, and a probe pad which extends onto the beveled edge. A first opening is located between the beveled edges of the first and second devices on a vertical side of the stacked semiconductor device.

Abstract: A stacked semiconductor device includes a first, a second, a third, and a fourth semiconductor device. A first major surface of each of the first and second semiconductor devices which includes the active circuitry directly face each other, and a first major surface of each of the third and fourth semiconductor devices which includes the active circuitry directly face each other. A second major surface of the second semiconductor device directly faces a second major surface of the third semiconductor device. The stacked semiconductor device includes a plurality of continuous conductive vias, wherein each continuous conductive via extends from the second major surface of the first device, through the first device, second device, third device, and fourth device to the second major surface of the fourth device. Each of the semiconductor devices may include a beveled edge at the first major surface on at least one edge of the device.

Abstract: Embodiments of the present disclosure provide an apparatus comprising a substrate layer, a metal ring structure disposed on the substrate layer, the metal ring structure having an opening defined therein, and a solder mask layer coupled to (i) the metal ring structure and (ii) the substrate layer through the opening defined in the metal ring structure, the solder mask layer having a solder mask opening defined therein, wherein an edge of solder mask material defining the solder mask opening overlaps a portion of the opening defined in the metal ring structure. Other embodiments may be described and/or claimed.

Abstract: A semiconductor device includes a support plate having a hole formed therein and a conductor formed on a wall surface of the hole, a semiconductor element; and a conductive post formed by a conductor having a first end portion at one end, and a second end portion at an other end. The second end portion of the conductive post is connected to the semiconductor element, and a side surface of the conductive post is fixed to the conductor on the wall surface of the hole deformed by pressing force of the conductive post on a side closer to the first end portion than the second end portion.

Abstract: An electronic component including a wiring board having a power-source pattern and a signal pattern, a semiconductor element mounted on the wiring board and having a power-source electrode pad and a signal electrode pad, a first connection portion being made of a conductive material and connecting the signal pattern of the wiring board and the signal electrode pad of the semiconductor element, and a second connection portion being made of a conductive material and connecting the power-source pattern of the wiring board and the power-source electrode pad of the semiconductor element. The conductive material of the first connection portion and the conductive material of the second connection portion are selected such that the conductive material of the second connection portion has an electrical resistance which is lower than an electrical resistance of the conductive material of the first connection portion.

Abstract: Disclosed herein is a method for manufacturing a semiconductor package which uses a base member 120 in which a first metal layer 113, a barrier layer 115, and a second metal layer 117 are stacked on both surface thereof in sequence based on an adhesive member 111 to simultaneously manufacture two printed circuit boards through a single sheet process, thereby making it possible to improve manufacturing efficiency; electrically connects a semiconductor chip 300 to a printed circuit board through a solder bump 250, thereby making it possible to implement a high-density package substrate; and forms a metal post 140 instead of a through hole to required in an interlayer circuit connection, thereby making it possible to reduce costs required in the processing/plating of the through hole.

Abstract: A semiconductor device includes a first conductor formed over a semiconductor device; an insulation film formed over the semiconductor substrate and the first conductor and having an opening arriving at the first conductor; a first film formed in the opening and formed of a compound containing Zr; a second film formed over the first film in the opening and formed of an oxide containing Mn; and a second conductor buried in the opening and containing Cu.

Abstract: System and method for test structure on a wafer. According to an embodiment, the present invention provides a test structure for testing a chip. For example, the test structure and the chip are manufactured on a same substrate material and the testing being conducted is in a temperature-controlled environment. The test structure includes a top structure positioned above the chip. For example, the top structure can be characterized by a first surface area. The top structure includes a first metal material occupying less than 60% of the surface area. The test structure also includes a bottom structure positioned below the chip. For example, the bottom structure can be characterized by a second surface area. The second surface area is substantially equal to the first surface area. The bottom structure includes a first silicon material. The first silicon material occupies substantially all of the second surface area.

Abstract: A microelectronic package can include a microelectronic element having a face and a plurality of element contacts thereon, a substrate having first and second surfaces, and terminals on the second surface configured for connecting the package with an external component. The microelectronic element can include a plurality of stacked electrically interconnected semiconductor chips. The substrate can have contacts facing the element contacts of the microelectronic element and joined thereto. The terminals can include first terminals arranged at positions within first and second parallel grids. The first terminals of each grid can be configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations within the microelectronic element.

Abstract: A system or microelectronic assembly can include one or more microelectronic packages each having a substrate and a microelectronic element having a face and one or more columns of contacts thereon which face and are joined to corresponding contacts on a surface of the substrate. An axial plane may intersect the face along a line in the first direction and centered relative to the columns of element contacts. Columns of package terminals can extend in the first direction. First terminals in a central region of the second surface can be configured to carry address information usable to determine an addressable memory location within the microelectronic element. The central region may have a width not more than three and one-half times a minimum pitch between the columns of package terminals. The axial plane can intersect the central region.

Abstract: A microelectronic package can include a substrate and a microelectronic element having a rear face facing a first surface of the substrate, a front face, and a column of element contacts extending in a first direction. The microelectronic element can include stacked electrically interconnected semiconductor chips. Edges of the microelectronic element can define an axial plane extending in the first direction and a third direction normal to the rear face. The package can include columns of terminals extending in the first direction at a second surface of the substrate. The terminals can include first terminals exposed in a central region of the second surface and configured to carry address information usable by circuitry within the package to determine an addressable memory location. The central region may have a width not more than 3.5 times a minimum pitch between adjacent terminal columns. The axial plane can intersect the central region.

Abstract: Method form via chain and serpentine/comb test structures in kerf areas of a wafer. The via chain test structures comprise a first via chain and a second via chain in a first kerf area. The via chain test structures are formed such that geometrically shaped portions of the first via chain and geometrically shaped portions of the second via chain alternate along the length of the first kerf area. The methods perform relatively low (first) magnification testing to identify a defective geometrically shaped portion that contains a defective via structure. The methods then perform relatively high (second) magnification testing only within the defective geometrically shaped portion. The first magnification testing is performed at a lower magnification relative to the second magnification testing.

Abstract: A HEMT has a compound semiconductor layer, a protection film which has an opening and covers an upper side of the compound semiconductor layer, and a gate electrode which fills the opening and has a shape riding on the compound semiconductor layer, wherein the protection film has a stacked structure of a lower insulating film not containing oxygen and an upper insulating film containing oxygen, and the opening includes a first opening formed in the lower insulating film and a second opening formed in the upper insulating film and wider than the first opening, the first opening and the second opening communicating with each other.

Abstract: A microelectronic element having a memory storage array has a front face facing away from a substrate of a microelectronic package, and is electrically connected with the substrate through conductive structure extending above the front face. First terminals are disposed at locations within first and second parallel grids of the package. The first terminals of each grid are configured to carry address information usable to determine an addressable memory location from among all the available addressable memory locations of the memory storage array. The first terminals in the first grid have signal assignments which are a mirror image of the signal assignments of the first terminals in the second grid.

Abstract: A microelectronic package can include a microelectronic element having a face and a plurality of element contacts thereon, a substrate having first and second surfaces, and terminals on the second surface configured for connecting the package with at least one external component. The substrate can have substrate contacts on the first surface facing the element contacts of the microelectronic element and joined thereto. The terminals can include first terminals arranged at positions within first and second parallel grids. The first terminals of each grid can be configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic element. The signal assignments of the first terminals in the first grid can be a mirror image of the signal assignments of the first terminals in the second grid.

Abstract: Apparatuses having, and methods for forming, conductive features are described. A hole is formed in a substrate and a conductive material is deposited in the hole. A part of the conductive material that occupies a first lengthwise portion of the hole is removed, and a conductive feature that occupies a second lengthwise portion of the hole remains in the substrate.

Abstract: A microelectronic package can include a substrate and a microelectronic element having a rear face facing a first surface of the substrate, a front face, and a column of element contacts extending in a first direction. Edges of the microelectronic element can define an axial plane extending in the first direction and a third direction normal to the rear face. The package can include columns of terminals extending in the first direction at a second surface of the substrate. The terminals can include first terminals exposed in a central region of the second surface and configured to carry address information usable by circuitry within the package to determine an addressable memory location within the microelectronic element. The central region may have a width not more than three and one-half times a minimum pitch between any two adjacent columns of the terminals. The axial plane can intersect the central region.

Abstract: A semiconductor device includes a semiconductor element having a first surface on which an electrode terminal is formed, and a second surface located opposite to the first surface. The semiconductor device further includes a first insulating layer in which the semiconductor element is buried, and second insulating layers and wiring layers formed in such a manner that at least one insulating layer and at least one wiring layer are formed on each of both surfaces of the first insulating layer. The electrode terminal of the semiconductor element is connected to a first wiring layer located on the first surface side through a first via formed in the first insulating layer, and the first wiring layer is connected to a second wiring layer located on the second surface side through a second via formed in the first insulating layer.

Abstract: A method for forming a device is disclosed. The method includes providing a substrate prepared with first and second contact regions and a dielectric layer over the contact region. First and second vias are formed in the dielectric layer. The first via is in communication with the first contact region and the second via is in communication with the second contact region. A buried void provides a communication path between the first and second vias. The vias and buried void are at least partially filled with a dielectric filler. The partially filled buried void blocks the communication path between the first and second vias created by the buried void. The dielectric filler in the vias is removed, leaving remaining dielectric filler in the buried void to block the communication path between the first and second vias and contact plugs are formed in the vias.

Abstract: In a semiconductor device in which semiconductor chips having a number of signal TSVs are stacked, a huge amount of man-hours have been required to perform a continuity test for each of the signal TSVs. According to the present invention, no continuity test is performed directly on signal TSVs. Dummy bumps are arranged in addition to signal TSVs. The dummy bumps of the semiconductor chips are connected through a conduction path that can pass the dummy bumps between the semiconductor chips with one stroke when the semiconductor chips are stacked. A continuity test of the conduction path allows a bonding defect on bonded surfaces of two of the stacked semiconductor chips to be measured and detected.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; applying a molded under-fill on the base substrate; forming a substrate contact extender through the molded under-fill and in direct contact with the base substrate; mounting a stack device over the molded under-fill; attaching a coupling connector from the substrate contact extender to the stack device; and forming a base encapsulation on the stack device, the substrate contact extender, and encapsulating the coupling connector.

Abstract: A semiconductor device has a semiconductor die mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. A first insulating layer is formed over the encapsulant and semiconductor die. First vias are formed through the first insulating layer to expose contact pads of the semiconductor die. A first conductive layer is formed over the first insulating layer and into the first vias to electrically connect to the contact pads of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. Second vias are formed through the second insulating layer by laser direct ablation and aligned or offset with the first vias to expose the first conductive layer. A second conductive layer is formed over the second insulating layer and into the second vias. Conductive vias can be formed through the encapsulant.

Abstract: An IC device comprises a stack of contact levels, each including conductive layer and an insulation layer. A dielectric liner surrounds an interlevel conductor within an opening in the stack of contact levels. The opening passes through a portion of the stack of contact levels. The interlevel conductor is electrically insulated from the conductive layers of each of the contact levels through the dielectric liner. A portion of the conductive layer at the opening is recessed relative to adjacent insulation layers. The dielectric liner may have portions extending between adjacent insulation layers.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a dummy-die paddle having a first inactive side facing up, a second inactive side facing down; forming an insulator in a single continuous structure around and in direct contact with the first inactive side; and mounting an integrated circuit over the dummy-die paddle and the insulator, the integrated circuit and the dummy-die paddle having the same coefficient of thermal expansion as the dummy-die paddle.

Abstract: A semiconductor substrate includes a vertical conductor and an insulating layer. The vertical conductor includes a metal/alloy component of a nanocomposite crystal structure and is filled in a vertical hole formed in the semiconductor substrate along its thickness direction. The insulating layer is formed around the vertical conductor in a ring shape and includes nm-sized silica particles and a nanocrystal or nanoamorphous silica filling up a space between the silica particles to provide a nanocomposite structure along with the silica particles.

Abstract: Integrated circuits and methods of fabricating integrated circuits are disclosed herein. One embodiment of an integrated circuit includes a die having a side, wherein a conductive stud extends substantially normal relative to the side. A dielectric layer having a first side and a second side is located proximate the side of the die so that the first side of the dielectric layer is adjacent the side of the die. The conductive stud extends into the first side of the dielectric layer. A first via extends between the conductive stud and the second side of the dielectric layer. A conductive layer having a first side and a second side is located adjacent the second side of the dielectric layer, wherein the first side of the conductive layer is located adjacent the second side of the dielectric layer. At least a portion of the conductive layer is electrically connected to the first via.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate having a substrate first side and a substrate second side opposite the substrate first side; attaching a base integrated circuit to the substrate first side; attaching a mountable integrated circuit to the substrate second side; attaching a via base to the substrate second side adjacent the mountable integrated circuit; forming a device encapsulation surrounding the via base and the mountable integrated circuit; and forming a via extension through the device encapsulation and attached to the via base, the via extension exposed from the device encapsulation.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; attaching a base integrated circuit on the base substrate; forming a base encapsulation, having a base encapsulation top side, on the base substrate and around the base integrated circuit; forming a base conductive via, having a base via head, through the base encapsulation and attached to the base substrate adjacent to the base integrated circuit, the base via head exposed from and coplanar with the base encapsulation top side; mounting an interposer structure over the base encapsulation with the interposer structure connected to the base via head; and forming an upper encapsulation on the base encapsulation top side and partially surrounding the interposer structure with a side of the interposer structure facing away from the base encapsulation exposed.

Abstract: In order to achieve finer bump interconnect pitch for integrated circuit packaging, while relieving pressure-induced delamination of upper layer dielectric films, the under bump metallurgy of the present invention provides a pressure distribution pedestal upon which a narrower copper pillar is disposed. A solder mini-bump is disposed on the upper exposed portion of the copper pillar, wherein the solder is softer than the copper pillar. The radius of the copper pillars is selected such that lateral deformation of the solder mini-bumps during final assembly does not form undesired conductive bridges between adjacent pillars.

Abstract: A semiconductor device is free from degradation of characteristics attributable to a manufacturing process thereof and its characteristics are hardly affected by changes in electric potentials of bonding pads. The semiconductor device 10 includes an active region 12, a first insulating layer 13 covering the active region 12, a floating conductor 14 formed on the first insulating layer 13, a second insulating layer 15 formed on the first insulating layer 13 and the floating conductor 14, a bonding pad 18 formed on the second insulating layer 17 and interconnection vias 19, 20 for electrically connecting the active region 12 and the bonding pad 18.

Abstract: A component including a via for electrical connection between a first and a second plane of a substrate is provided. The substrate has a borehole having an inner wall that is coated with a conductive layer made of an electrically conductive material, an intermediate layer being disposed between the inner wall and the conductive layer. The intermediate layer includes electrically insulating SiC.

Abstract: A semiconductor substrate has a front surface and a back surface, and a TSV structure is formed to extend through the semiconductor substrate. The TSV structure includes a metal layer, a metal seed layer surrounding the metal layer, a barrier layer surrounding the metal seed layer, and a block layer formed in a portion sandwiched between the metal layer and the metal seed layer. The block layer includes magnesium (Mg), iron (Fe), cobalt (Co), nickel (Ni), titanium (Ti), chromium (Cr), tantalum (Ta), tungsten (W), cadmium (Cd), or combinations thereof.

Abstract: Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor substrate. A top region of the metal interconnect is located vertically below a horizontal plane containing a metal routing layer. Method of fabricating the semiconductor device can include etching a via into a semiconductor substrate, filling the via with a metal material, forming a metal routing layer subsequent to filling the via, and removing a portion of a bottom of the semiconductor substrate to expose a bottom region of the metal filled via.

Abstract: A semiconductor package structure includes: a substrate comprising a plurality of power supply balls on a first surface of the substrate, a first metal conductor on a second surface of the substrate and at least one via coupling a power supply ball to the first metal conductor of the substrate; a die, comprising a plurality of bond pads on a first surface of the die, a first metal conductor on a second surface of the die and at least one via coupling a bond pad to the first metal conductor of the die; and a plurality of first wire bonds for coupling the first metal conductor of the substrate to the first metal conductor of the die.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a first stack layer including a first device over a first substrate, the first device including a through silicon via; configuring a second stack layer over the first stack layer, the second stack layer including an analog device; configuring a third stack layer over the second stack layer; and encapsulating the integrated circuit packaging system.

Abstract: Disclosed is a multi-layer via structure, comprising a metal layer, a first via metal layer formed on a first open of a first dielectric layer and a second via metal layer formed on a second open of a second dielectric layer. The first and second via metal layers comprise first and second bottoms, first and second top portions, first and second inclined walls, respectively. The first and second inclined walls comprise first and second top edges, first and second bottom edges respectively. The second top edge has a point closest to a geometric center of the first bottom. A vertical projection of the point falls on the first inclined wall. Alternatively, a point of the second bottom edge, which is closest to the geometric center, has a vertical projection. The vertical projection is vertical to the metal layer and falls on the first inclined wall.

Abstract: A semiconductor package includes a set of stud bumps, which can be formed by wire bonding technology and can be bonded or joined to a semiconductor element to form a stacked package assembly. Since the process of bonding the semiconductor element to the stud bumps can be carried out without reflow, an undesirable deformation resulting from high temperatures can be controlled or reduced.

Abstract: A semiconductor package includes a first semiconductor chip including a target circuit surface and a side surface, a first sealing insulating layer including a first surface positioned toward the target circuit surface and a second surface positioned opposite to the first surface, the first sealing insulating layer sealing the target circuit surface and the side surface, a wiring layer formed on the first surface of the first sealing insulating layer, an insulating layer formed on the wiring layer, a second semiconductor chip mounted on the second surface of the first sealing insulating layer, and a second sealing insulating layer formed on the second surface and sealing the second semiconductor chip.

Abstract: A semiconductor device has a first insulating layer formed over a carrier. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first conductive layer. Vias are formed through the second insulating layer. A second conductive layer is formed over the second insulating layer and extends into the vias. A semiconductor die is mounted to the second conductive layer. A bond wire is formed between a contact pad on the semiconductor die and the second conductive layer. The second conductive layer extends to a mounting site of the semiconductor die to minimize the bond wire span. An encapsulant is deposited over the semiconductor die. A portion of the first insulating layer is removed to expose the second conductive layer. A portion of the first conductive layer is removed to electrically isolate remaining portions of the first conductive layer.

Abstract: Disclosed is a flash memory card without a substrate, primarily comprising a memory chip component, a controller chip disposed on the memory chip, and an encapsulant encapsulating both chips. Formed on an active surface and a back surface of the memory chip component are a first RDL (redistribution layer) and a second RDL respectively. A plurality of TSVs (through silicon vias) penetrate from the active surface to the back surface to electrically connect both RDLs. A plurality of contacting fingers are disposed on the back surface of the memory chip component and electrically connected with the second RDL. Additionally, the encapsulant has a card appearance with one surface of each contacting finger to be exposed. Accordingly, the flash memory card can save conventional substrate structure with better reliability and efficiency for packaging processes.

Abstract: Methods of forming an integrated circuit structure utilizing a selectively formed and at least partially oxidized metal cap over a gate, and associated structures. In one embodiment, a method includes providing a precursor structure including a transistor having a metal gate; forming an etch stop layer over an exposed portion of the metal gate; at least partially oxidizing the etch stop layer; and forming a dielectric layer over the at least partially oxidized etch stop layer.

Abstract: A first wiring is disposed over a semiconductor substrate. A first via is disposed over the first wiring. Further, the bottom surface of the first via is in contact with the first wiring. A first insulation layer is disposed over the semiconductor substrate, and is in contact with at least the top surface of the first wiring and the side surface of the first via. At least a part of each side surface of the first wiring and the first via cuts off each metal crystal grain.

Abstract: A semiconductor device structure for a three-dimensional integrated circuit has a semiconductor substrate having a plurality of through-substrate vias provided in the substrate, wherein three or more of the plurality of through-substrate vias are arranged in a hexagonal packing array with respect to their design-rule circle.

Abstract: A semiconductor device has a semiconductor wafer with a plurality of contact pads. A first insulating layer is formed over the semiconductor wafer and contact pads. A portion of the first insulating layer is removed, exposing a first portion of the contact pads, while leaving a second portion of the contact pads covered. An under bump metallization layer and a plurality of bumps is formed over the contact pads and the first insulating layer. A second insulating layer is formed over the first insulating layer, a sidewall of the under bump metallization layer, sidewall of the bumps, and upper surface of the bumps. A portion of the second insulating layer covering the upper surface of the bumps is removed, but the second insulating layer is maintained over the sidewall of the bumps and the sidewall of the under bump metallization layer.

Abstract: One embodiment of the present disclosure provides an apparatus comprising a flex circuit substrate having a core, a first solder mask and first traces disposed on the core on a first side of the flex circuit substrate, and a second solder mask and second traces disposed on the core on a second side of the flex circuit substrate. The first side is opposite to the second side. The apparatus further includes vias formed through the core to electrically couple the first traces to the second traces, and a stiffening structure coupled to the first side of the flex circuit substrate to increase structural rigidity of the flex circuit substrate. The stiffening structure provides structural, support to allow attachment of an integrated circuit die to the first side of the flex circuit substrate.