Abstract: Circuits for shielding devices from electromagnetic coupling with through-silicon vias are shown that include a substrate having a through via, which provides access to a device layer on a first surface of the circuit to a device layer on a second surface of the circuit; a conductive layer on the first side of the substrate; a contact point on one of the device layers; and a grounded buried interface tie on the conductive layer, adjacent to the contact point, to isolate the contact point from coupling noise.

Abstract: A flip chip package includes a carrier coupled to a die. The carrier includes: at least a via, for coupling the surface of the carrier to electrical traces in the carrier; and at least a capture pad electrically coupled to the via, wherein the capture pad is plated over the via. The die includes: at least a bond pad formed on the surface of the die; and at least a copper column, formed on the bond pad for coupling the die to the capture pad on the carrier, wherein the copper column is disposed on one side of the capture pad about the via opening only.

Abstract: A semiconductor device includes a substrate, at least one via hole provided on the substrate, a through silicon via provided in the at least one via hole, and an interface chip that is electrically connected to the core chips through the through silicon via. The via hole includes a bowing shaped portion in which a diameter of a center portion is larger than diameters of both edges.

Abstract: A chip stacking structure including a carrier, a first redistribution layer, a second redistribution layer, at least one first chip, at least one second chip, and at least one conductor is provided. The carrier has a first surface and a second surface opposite to each other. The carrier has at least one through hole. The first and second redistribution layers are disposed on the first and second surfaces of the carrier, respectively. The first and second chips are disposed on the first and second surfaces of the carrier and electrically connected with the first and second redistribution layers, respectively. The conductor is disposed on one of the first and second chips. The conductor is disposed in the through hole. The first and second chips are electrically connected by the conductor. A gap is formed between the conductor and an inner wall of the carrier which surrounds the through hole.

Abstract: A TSV structure includes a through via connecting a first side and a second side of a wafer, a conductive layer which fills up the through via, a through via dielectric ring surrounding and directly contacting the conductive layer, a first conductive ring surrounding and directly contacting the through via dielectric ring as well as a first dielectric ring surrounding and directly contacting the first conductive ring and surrounded by the wafer.

Abstract: A silicon substrate has a conductive via extending from a first surface of the silicon substrate through the silicon substrate to a second surface of the silicon substrate. A dielectric via extends from the second surface of the silicon substrate toward the first surface of the silicon substrate.

Abstract: The present invention relates to a through silicon via (TSV). The TSV is disposed in a substrate including a via opening penetrating through a first surface and a second surface of the substrate. The TSV includes an insulation layer, a barrier layer, a buffer layer and a conductive electrode. The insulation layer is disposed on the surface of the via opening. The barrier layer is disposed on the surface of the insulation layer. The conductive electrode is disposed on the surface of the buffer layer and fills the via opening. The buffer layer further covers a surface of the conductive electrode at the side of the second surface. The present invention further discloses a method of forming the TSV.

Abstract: Provided is a method of manufacturing a metal interconnect of a semiconductor device including: forming a interconnect hole by patterning an interlayer insulating film formed on a substrate; performing a nitriding treatment on a surface of the interlayer insulating film by injecting a gas including nitrogen into a deposition apparatus in which the substrate is disposed; forming a diffusion preventing film by injecting the gas including nitrogen and a metal source gas into the deposition apparatus together; filling the interconnect hole with a metal; and removing the metal formed on a part other than the interconnect hole by a chemical mechanical polishing (CMP) process. Accordingly, the mechanical strength of the interlayer insulating film is increased, thereby preventing scratches or defects that are generated during the chemical mechanical polishing process.

Abstract: An integrated circuit including a first portion of a first cell library including a first plurality of rows, each of the first plurality of rows having a first row height and the first portion having a first portion height, a second portion of a second cell library including a second plurality of rows, each of the second plurality of rows having a second row height and the second portion having a second portion height, wherein the first portion height is equal to the second portion height and the first row height is different from the second row height, and a connector to electrically connect the first portion of the first cell library to the second portion of the second cell library.

Abstract: A device includes a package component, and a die over and bonded to the package component. The die includes a substrate. A heat sink is disposed over and bonded to a back surface of the substrate through direct bonding.

Abstract: An interface substrate is disclosed which includes an interposer having through-semiconductor vias. An upper and a lower organic substrate are further built around the interposer. The disclosed interface substrate enables the continued use of low cost and widely deployed organic substrates for semiconductor packages while providing several advantages. The separation of the organic substrate into upper and lower substrates enables the cost effective matching of fabrication equipment. By providing an opening in one of the organic substrates, one or more semiconductor dies may be attached to exposed interconnect pads coupled to through-semiconductor vias of the interposer, enabling the use of flip chips with high-density microbump arrays and the accommodation of dies with varied bump pitches. By providing the opening specifically in the upper organic substrate, a package-on-package structure with optimized height may also be provided.

Abstract: The present application discloses various implementations of a semiconductor package including an organic substrate and one or more interposers having through-semiconductor vias (TSVs). Such a semiconductor package may include a contiguous organic substrate having a lower substrate segment including first and second pluralities of lower interconnect pads, the second plurality of lower interconnect pads being disposed in an opening of the lower substrate segment. The contiguous organic substrate may also include an upper substrate segment having an upper width and including first and second pluralities of upper interconnect pads. In addition, the semiconductor package may include at least one interposer having TSVs for electrically connecting the first and second pluralities of lower interconnect pads to the first and second pluralities of upper interconnect pads. The interposer has an interposer width less than the upper width of the upper substrate segment.

Abstract: Disclosed is a semiconductor device that is capable of preventing impurities such as moisture from being introduced into an active region at the time of dicing and at the time of bonding and that is capable of being easily miniaturized. The semiconductor device includes a cylindrical dummy wire having an opening for allowing a wire interconnecting a semiconductor element and an external connection terminal to pass therethrough, extending in an insulation film provided on a semiconductor layer having the semiconductor element to surround the semiconductor element, and disposed inside the external connection terminal.

Abstract: The present invention relates to a through silicon via (TSV) for 3D packaging to integrate a semiconductor device and a method for manufacturing the same, and more particularly, to a through silicon via (TSV) for 3D packaging of a semiconductor device that is capable of improving production efficiency, having very high electric conductivity, and minimizing electrical signal delay, without using a carrier wafer by self-aligning substrates in a low temperature state and sequentially bonding a plurality of semiconductor dies (or semiconductor chips), and a method of manufacturing the same.

Abstract: A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) bonded to the substrate contact. The through wire interconnect (TWI) includes a via through the substrate contact and the substrate, a compressed wire in the via bonded to the substrate contact, and a contact on the wire. A stacked semiconductor component includes the semiconductor substrate, and a second semiconductor substrate stacked on the substrate and bonded to a through wire interconnect on the substrate.

Abstract: Structures are provided with raised buffer pads for solder bumps. Methods are also provided for forming the raised buffer pads for solder bumps. The method includes forming a raised localized buffer pad structure on a tensile side of a last metal layer of a solder bump connection. The raised localized buffer pad structure increases a height of a portion of a pad structure of the solder bump connection with respect to a compressive side of the last metal layer.

Abstract: A device includes a dielectric layer, a metal line in the dielectric layer, and a via underlying and connected to the metal line. Two dummy metal patterns are adjacent to the metal line, and are aligned to a straight line. A dummy metal line interconnects the two dummy metal patterns. A width of the dummy metal line is smaller than lengths and widths of the two dummy metal patterns, wherein the width is measure in a direction perpendicular to the straight line. Bottoms of the two dummy metal patterns and the dummy metal line are substantially level with a bottom surface of the metal line.

Abstract: Embodiments of the present invention relate to a semiconductor chip comprising a plurality of contact pads, which are arranged in an edge area on a surface of the semiconductor chip. In a semiconductor area of the semiconductor chip, every contact pad of the plurality of contact pads has an associated pad cell provided, which includes at least one of a driver or a receiver and is configured to drive output signals or receive input signals on its associated contact pad, if the driver or receiver is connected to the contact pad. Additionally, for a contact pad which is used as a supply contact pad, the driver or receiver of the associated pad cell is not connected to the contact pad or any other contact pad for driving output signals or receiving input signals on the same.

Abstract: Wafer-scale packaging structures and methods are provided for integrally packaging antenna structures with semiconductor RFIC (radio frequency integrated circuit) chips to form compact integrated radio/wireless communications systems for millimeter wave (mmWave) and Terahertz (THz) applications. For example, a chip package includes an RFIC chip, an antenna structure and an interface layer. The RFIC chip includes a semiconductor substrate having an active surface and an inactive surface, and a BEOL (back end of line) structure formed on the active surface of the semiconductor substrate. The antenna structure includes an antenna substrate and a planar antenna radiator formed on a surface of the antenna substrate, wherein the antenna substrate is formed of a low loss semiconductor material. The interface layer connects the antenna structure to the BEOL structure of the RFIC chip.

Abstract: Disclosed herein are various methods of forming device level conductive contacts to improve device performance and various semiconductor devices with such improved deice level contact configurations. In one example, a device disclosed herein includes a first device level conductive contact positioned in a first layer of insulating material, wherein the first device level conductive contact is conductively coupled to a semiconductor device, a second device level conductive contact positioned above and conductively coupled to the first device level contact, wherein the second device level contact is positioned in a second layer of insulating material, and a first wiring layer for the device that is positioned above and conductively coupled to the second device level conductive contact.

Abstract: A semiconductor device and a manufacturing method thereof are disclosed. The method comprises: providing a substrate with a first dielectric layer and a gate, wherein the gate is embedded in the first dielectric layer and an upper portion of the gate is an exposed first metal; and covering only the exposed first metal with a conductive material that is harder to be oxidized than the first metal by a selective deposition. An advantage of the present invention is that the metal of the upper surface of the gate is prevented from being oxidized by covering the metal gate with the conductive material that is relatively harder to be oxidized, thereby facilitating the formation of an effective electrical connection to the gate.

Abstract: A semiconductor device has a substrate having a plurality of metal traces. A die is electrically attached to a first surface of the substrate. A first plurality of segmented metal traces is formed around a perimeter of the first surface of the substrate, wherein an end section of the first plurality of segmented metal traces is exposed. A mold compound is used for encapsulating the semiconductor device. A first metal plating is formed on a top terminal end section of the first plurality of segmented metal traces. The first metal plating is spread to at least one of the mold compound or the exposed end sections of the first plurality of segmented metal traces. A conductive coating is applied to the mold compound, the exposed end sections of the first plurality of segmented metal traces and to the first metal plating.

Abstract: According to an embodiment, a chip package is provided, which includes: a substrate having a first surface and a second surface; a device region formed in the substrate; a passivation layer formed overlying the first surface of the substrate; at least a polymer planarization layer formed overlying the passivation layer; a package substrate disposed overlying the first surface of the substrate; and a spacer layer disposed between the package substrate and the passivation layer, wherein the spacer layer and the package substrate surround a cavity overlying the substrate, wherein the polymer planar layer does not extends to an outer edge of the spacer layer.

Abstract: A wiring substrate includes a wiring pattern in an uppermost layer that includes pads. A solder resist layer covers the wiring pattern. A recess exposes part of the wiring pattern from the solder resist layer to form pads. The solder resist layer includes a portion formed in a region corresponding to the recess, a portion formed outward from the recess, and a portion formed inward from the recess. The upper surface of the solder resist layer at the portion corresponding to the recess is higher than the upper surface of the pads but lower than the upper surfaces of the other portions of the solder resist layer.

Abstract: An integrated circuit structure includes a semiconductor substrate; a gate stack overlying the semiconductor substrate; a gate spacer on a sidewall of the gate stack; a first contact plug having an inner edge contacting a sidewall of the gate spacer, and a top surface level with a top surface of the gate stack; and a second contact plug over and contacting the first contact plug. The second contact plug has a cross-sectional area smaller than a cross-sectional area of the first contact plug.

Abstract: A semiconductor device containing: a semiconductor element; a support substrate; an insulating material layer for sealing the semiconductor element and a periphery thereof; a metal thin film wiring layer provided in the insulating material layer, with a part thereof being exposed on an external surface; and metal vias provided in the insulating material layer and electrically connected to the metal thin film wiring layer. The semiconductor element is provided in a plurality of units and the respective semiconductor elements are stacked via an insulating material such that a circuit surface of each semiconductor element faces the metal thin film wiring layer, and electrode pads of each semiconductor element are exposed without being hidden by the semiconductor element stacked thereabove.

Abstract: The mechanisms of using an interposer frame to form a PoP package are provided in the disclosure. The interposer frame is formed by using a substrate with one or more additives to adjust the properties of the substrate. The interposer frame has openings lined with conductive layer to form through substrate vias (TSVs) with solder balls on adjacent packages. The interposer frame enables the reduction of pitch of TSVs, mismatch of coefficients of thermal expansion (CTEs), shorting, and delamination of solder joints, and improve mechanical strength of the package.

Abstract: The present invention relates to a method of fabricating a through silicon via (TSV) structure, in which, a dielectric layer is disposed to cover surface of each of a device region of a substrate and a sidewall and a bottom of a via hole in a TSV region of the substrate, and the via hole having the dielectric layer covering the sidewall and the bottom is filled with a conductive material. The present invention also relates to a TSV structure, in which, a dielectric layer disposed in the device region of a substrate extends to the via hole in a TSV region of the substrate to cover surface of the sidewall of the via hole to serve as a dielectric liner, and a conductive material is filled into the via hole having the dielectric layer covering the sidewall.

Abstract: An integrated circuit structure includes an interconnect structure that includes a plurality of metal layers, wherein the interconnect structure is under a semiconductor substrate. A metal pad is formed in one of the plurality of metal layers. A dielectric pad extends from a bottom surface of the semiconductor substrate up into the semiconductor substrate. An opening extends from a top surface of the semiconductor substrate down to penetrate through the semiconductor substrate and the dielectric pad. An edge of the semiconductor substrate in the opening is vertically aligned to an edge of the dielectric pad in the opening. The opening stops on a top surface of the metal pad. A dielectric spacer is disposed in the opening, wherein the dielectric spacer is formed on the edge of the semiconductor substrate and the edge of the dielectric pad.

Abstract: A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.

Abstract: Structure and methods of forming stacked semiconductor chips are described. In one embodiment, a method of forming a semiconductor chip includes forming an opening for a through substrate via from a top surface of a first substrate. The sidewalls of the opening are lined with an insulating liner and the opened filled with a conductive fill material. The first substrate is etched from an opposite bottom surface to form a protrusion, the protrusion being covered with the insulating liner. A resist layer is deposited around the protrusion to expose a portion of the insulating liner. The exposed insulating liner is etched to form a sidewall spacer along the protrusion.

Abstract: A semiconductor package includes a body having a first surface and a second surface facing away from the first surface, and formed with a groove in the first surface. First connection parts may electrically connect a portion of the first surface to a portion of the second surface of the body. Second connection parts may electrically connect a portion of a bottom portion of the groove to a portion of the second surface of the body. A lower device may be disposed in the groove of the body, and have third connection parts that are electrically connected with the second connection parts. An upper device may be disposed on the body and the lower device, and have fourth connection parts that are electrically connected with the first connection parts and the third connection parts.

Abstract: A semiconductor device has an insulating film, serving as low-porosity regions low in porosity, formed on a substrate and high-porosity regions higher in porosity than the low-porosity regions, and also includes copper interconnects formed to fill interconnect grooves in the insulating film. The insulating film is present under the interconnect grooves, and present in portions neighboring the sidewalls of the interconnect grooves.

Abstract: A method of fabricating a through silicon via (TSV) structure, in which, a patterned mask is formed on a substrate, the patterned mask has an opening, a spacer-shaped structure is formed on a sidewall of the opening, and a via hole having a relatively enlarged opening is formed by etching the spacer-shaped structure and the substrate through the opening after the spacer-shaped structure is formed. A TSV structure, in which, a via hole has an opening portion and a body portion, the opening portion is a relatively enlarged opening and has a tapered shape having an opening size of an upper portion greater than an opening size of a lower portion.

Abstract: Disclosed is a chip with a power divider/combiner, a module incorporating the chip and associated methods. The divider/combiner comprises first and second metal layers on opposite sides of a substrate. Interconnects extend through the substrate and comprise: a first interconnect, second interconnects annularly arranged about the first interconnect and third interconnects annularly arranged about the second interconnects. Each interconnect comprises one or more through silicon vias lined/filled with a conductor. For a power divider, an opening in the first metal layer at the first interconnect comprises an input port for receiving power and openings in the first or second metal layer at the second interconnects comprise output ports for applying power to other devices. For a power combiner, openings in the first or second metal layer at the second interconnects comprise the input ports and an opening in the first metal layer at the first interconnect comprises an output port.

Abstract: Embodiments of a method for manufacturing an integrated circuit are provided. In one embodiment, a partially-fabricated integrated circuit is produced including a semiconductor substrate having source/drain regions, and a plurality of transistors including a plurality of gate conductors formed over the semiconductor substrate and between the source/drain regions. Device-level contacts are formed in ohmic contact with the gate conductors and with the source/drain regions. The device-level contacts terminate at substantially the same level above the semiconductor substrate. Copper interconnect lines are then formed in a level above the device-level contacts and in ohmic contact therewith to locally interconnect the plurality of transistors.

Abstract: Systems, apparatuses, and methods related to the design, fabrication, and manufacture of gallium arsenide (GaAs) integrated circuits are disclosed. Copper can be used as the contact material for a GaAs integrated circuit. Metallization of the wafer and through-wafer vias can be achieved through copper plating processes disclosed herein. To improve the copper plating, a seed layer formed in the through-wafer vias can be modified to increase water affinity, rinsed to remove contaminants, and activated to facilitate copper deposition. GaAs integrated circuits can be singulated, packaged, and incorporated into various electronic devices.

Abstract: A method of forming a semiconductor device includes forming a first conductive layer over the substrate. A dielectric layer, having a first opening, is formed over the first conductive layer. A seed layer is deposited over the first dielectric layer and in the first opening. A layer is formed of conductive nanotubes from the seed layer over the first dielectric layer and over the first opening. A second dielectric is formed over the layer of conductive nanotubes. An opening is formed in the second dielectric layer over the first opening. Conductive material is deposited in the second opening.

Abstract: The subject matter disclosed herein relates to structures formed on semiconductor chips that are used for at least partially addressing the thermally induced stresses and metallization system cracking problems in a semiconductor chip that may be caused by the presence of through-silicon vias (TSV's), and which may be due primarily to the significant differences in thermal expansion between the materials of the TSV's and the semiconductor-based materials that generally make up the remainder of the semiconductor chip. One device disclosed herein includes a substrate and a crack-arresting structure positioned above the substrate, the crack-arresting structure comprising a plurality of crack-arresting elements and having a perimeter when viewed from above.

Abstract: A fabrication method of a semiconductor package includes the steps of: providing a carrier having a concave portion and a releasing layer formed on a surface thereof; disposing a chip on the releasing layer in the concave portion; forming an encapsulant on the chip and the releasing layer; removing the releasing layer and the carrier; and forming a circuit structure on the encapsulant and the chip. The design of the concave portion facilitates alignment of the chip to prevent it from displacement, thereby improving the product reliability. A semiconductor package fabricated by the fabrication method is also provided.

Abstract: A low cost and high performance flip chip package is disclosed. By assembling the package using a substrate panel level process, a separate fabrication of a substrate is avoided, thus enabling the use of a coreless substrate. The coreless substrate may include multiple stacked layers of laminate dielectric films having conductive traces and vias. As a result, electrical connection routes may be provided directly from die contact pads to package contact pads without the use of conventional solder bumps, thus accommodating very high density semiconductor dies with small feature sizes. The disclosed flip chip package provides lower cost, higher electrical performance, and improved thermal dissipation compared to conventional fabricated substrates with solder bumped semiconductor dies.

Abstract: A method for forming passivated through wafer vias, passivated through wafer via structures, and passivated through wafer via design structures. The method includes: forming a through wafer via in a semiconductor substrate, the through wafer via comprising an electrical conductor extending from a top of the semiconductor substrate to a bottom surface of the semiconductor substrate; and forming a doped layer abutting all sidewalls of the electrical conductor, the doped layer of a same dopant type as the semiconductor substrate, the concentration of dopant in the doped layer greater than the concentration of dopant in the semiconductor substrate, the doped layer intervening between the electrical conductor and the semiconductor substrate.

Abstract: An IC including first metal layer having wiring running in a first direction; a second metal layer having wiring running in a second direction perpendicular to the first direction; and a first via layer between the first metal layer and the second metal layer, the first via layer including a viabar interconnecting the first metal layer to the second metal layer at a first location where the first metal layer vertically coincides with the second metal layer and, at a second location, connecting to wiring of the first metal layer but not wiring of the second metal layer.

Abstract: An electric device with vias that include dielectric structures to prevent conductive material in the vias from electrically connecting conductive structures on a top of the vias with conductive structures on the bottom of the vias. The dielectric structures are formed in selected vias where other vias do not include the dielectric structures.

Abstract: An embodiment is a method for forming a microelectromechanical system (MEMS) device. The method comprises forming a MEMS structure over a first substrate, wherein the MEMS structures comprises a movable element; forming a bonding structure over the first substrate; and forming a support structure over the first substrate, wherein the support structure protrudes from the bonding structure. The method further comprises bonding the MEMS structure to a second substrate; and forming a through substrate via (TSV) on a backside of the second substrate, wherein the overlying TSV is aligned with the bonding structure and the support structure.

Abstract: A semiconductor package may include a substrate, and a semiconductor interposer having a cavity and a plurality of through semiconductor vias. The semiconductor interposer is situated over the substrate. An intra-interposer die is disposed within the cavity of the semiconductor interposer. A thermally conductive adhesive is disposed within the cavity and contacts the intra-interposer die. Additionally, a top die is situated over the semiconductor interposer. In one implementation, the semiconductor interposer is a silicon interposer. In another implementation, the semiconductor interposer is flip-chip mounted to the substrate such that the intra-interposer die disposed within the cavity faces the substrate. In yet another implementation, the cavity in the semiconductor interposer may extend from a top surface of the semiconductor interposer to a bottom surface of the semiconductor interposer and a thermal interface material may be disposed between the intra-interposer die and the substrate.

Abstract: A semiconductor device package structure includes a substrate with a via contact pad on top surface of the substrate, a terminal pad on bottom surface of the substrate and a conductive through hole through the substrate, wherein the conductive through hole electrically couples the via contact pad and the terminal pad on the substrate; a die having bonding pads thereon, wherein the die is formed on the top surface of the substrate; a slanting structure formed adjacent to at least one side of the die for carrying conductive traces; and a conductive trace formed on upper surface of the slanting structure to offer path between the bonding pads and the via contact pad.

Abstract: Provided are a method of growing carbon nanotubes laterally, including forming catalyst dots to grow carbon nanotubes on a substrate, forming a sacrificial layer including a plurality of nanochannels including regions having the catalyst dots formed therein, and growing carbon nanotubes through the nanochannels, and a field effect transistor using the method.

Abstract: A luminous body comprises a transparent plastic moulding with indentations, and LED DIEs disposed within the indentations. One side of each LED DIE lies approximately flush with an upper side of the moulding, and each LED DIE is connected to an electricity supply via electrical conductors disposed on the moulding. A method for producing such a luminous body is also disclosed.

Abstract: A semiconductor device and a manufacturing method thereof are provided. In one embodiment of the manufacturing method of the semiconductor device, a through electrode is formed on a semiconductor die, and a dielectric layer such as a photopolymer is coated on the through electrode to cover the through electrode. Under exposure is performed on the dielectric layer, thereby partially removing the dielectric layer by development. As a result, a top end of the through electrode is exposed to the outside or protrudes through the dielectric layer. The dielectric layer remaining on the top end of the through electrode may be removed by performing a plasma descum process, if needed.