Abstract: A silicon structure includes a silicon substrate having an electric element; a wiring conductor and a bonding pad, connecting the electric element and an external circuit; a protective layer disposed on the silicon substrate; and a pad opening pattern provided in the protective layer to exposed the bonding pad, wherein a probe mark position and a wire bonding position differ, without increasing the size of the bonding pad in plan view. A substrate exposure part, which is not covered with the protective layer, is provided at part of an outer edge of the bonding pad disposed inside the pad opening pattern in the protective film, and the wiring conductor is not exposed through substrate exposure part.

Abstract: A semiconductor device includes: an insulating layer formed on a substrate; a plurality of interlayer insulating films which are formed on the insulating layer and comprise an opening window; a multilayer wiring which is formed with a plurality of wiring layers and a plurality of vias formed in the plurality of interlayer insulating films; a metal pad connected with the multilayer wiring, an upper surface part of the metal pad being a bottom part of the opening window, the metal pad formed closer to the substrate than a wiring layer of a lowermost layer of the plurality of wiring layers and is; and a pad ring provided on the metal pad, the pad ring penetrating the plurality of interlayer insulating films and the pad ring surrounding the opening window.

Abstract: An embodiment of the invention provides a chip package, which includes: a substrate having an upper surface and a lower surface; a passivation layer located overlying the upper surface of the substrate; a plurality of conducting pad structures disposed overlying the upper surface of the substrate, wherein at least portions of upper surfaces of the conducting pad structures are exposed; a plurality of openings extending from the upper surface towards the lower surface of the substrate; and a plurality of movable bulks located between the openings and connected with the substrate, respectively, wherein each of the movable bulks is electrically connected to one of the conducting pad structures.

Abstract: The reliability of the semiconductor device which has the structure which stores a plurality of semiconductor chips with which plane sizes differ in the same sealing body in the state where they are accumulated via the insulating film which has adhesive property is improved. In the semiconductor device which has the structure which stores a plurality of semiconductor chips with which plane sizes differ in the same sealing body in the state where they are accumulated via DAF, thickness of DAF of the back surface of the uppermost semiconductor chip with which the control circuit was formed was made thicker than each of DAF of the back surface of the lower layer semiconductor chip with which the memory circuit was formed. Hereby, the defect that the bonding wire which connects the uppermost semiconductor chip and a wiring substrate contacts the main surface corner part of a lower layer semiconductor chip can be reduced.

Abstract: An electronic device package includes a substrate and wire columns arranged in groups about a neutral stress point of the substrate. The height of the wire columns is substantially uniform for the plural groups of wire columns, and a length of at least one of the wire columns is greater than the uniform height. A method of fabricating an electronic device package having a column grid array includes applying two templates on wire columns of the column grid array and bending at least one wire column to increase its length while maintaining a uniform height for the column grid array. In another aspect, an electronic device package substrate includes wire columns having at least one non-uniformity in lengths of the columns, and the length of a wire column corresponds to a distance of that wire column from the neutral stress point of the substrate.

Abstract: According to an embodiment, a chip package is provided, which includes: a substrate having a first surface and a second surface; a device region formed in the substrate; a passivation layer formed overlying the first surface of the substrate; at least a polymer planarization layer formed overlying the passivation layer; a package substrate disposed overlying the first surface of the substrate; and a spacer layer disposed between the package substrate and the passivation layer, wherein the spacer layer and the package substrate surround a cavity overlying the substrate, wherein the polymer planar layer does not extends to an outer edge of the spacer layer.

Abstract: A semiconductor device has a plurality of stacked semiconductor dice mounted on a substrate. Each die has similar dimensions. Each die has a first plurality of bonding pads arranged along a bonding edge of the die. A first group of the dice are mounted to the substrate with the bonding edge oriented in a first direction. A second group of the dice are mounted to the substrate with the bonding edge oriented in a second direction opposite the first direction. Each die is laterally offset in the second direction relative to the remaining dice by a respective lateral offset distance such that the bonding pads of each die are not disposed between the substrate and any portion of the remaining dice in a direction perpendicular to the substrate. A plurality of bonding wires connects the bonding pads to the substrate. A method of manufacturing a semiconductor device is also disclosed.

Abstract: A semiconductor device includes a first bonding pad, a second bonding pad, a wire bonded to a selected one of the first and second bonding pads, a power supply line electrically connected to the first bonding pad, and a voltage converter circuit coupled to the second bonding pad, the voltage converter circuit being activated when the wire is bonded to the second pad to produce an internal power voltage, which is different from a voltage received by the voltage converter circuit through the wire and the second bonding pad, and supply the internal power voltage to the power supply line, and the voltage converter circuit being deactivated when the wire is connected to the first bonding pad to allow the power supply line to receive a power voltage through the wire and the first bonding pad.

Abstract: A semiconductor device includes an integrated circuit die on a substrate. A first subset of wire bonds is between the substrate and the die. A second subset of wire bonds is between the substrate and the die. A dielectric material coats the first subset of the wire bonds along a majority of length of the first subset of the wire bonds. A medium is in contact with the second subset of the wire bonds along a majority of length of the second subset of the wire bonds.

Abstract: A quad flat non-leaded package including a first patterned conductive layer, a second patterned conductive layer, a chip, bonding wires and a molding compound is provided. The first patterned conductive layer defines a first space, and the second patterned conductive layer defines a second space, wherein the first space overlaps the second space and a part of the second patterned conductive layer surrounding the second space. The chip is disposed on the second patterned conductive layer. The bonding wires are connected between the chip and the second patterned conductive layer. The molding compound encapsulates the second patterned conductive layers, the chip and the bonding wires. In addition, a method of manufacturing a quad flat non-leaded package is also provided.

Abstract: A light emitting device package is disclosed. The light emitting device package includes a light emitting device disposed on a first lead frame, the light emitting device having an electrode pad on an upper surface thereof, a first wire to electrically interconnect a second lead frame spaced apart from the first lead frame and the electrode pad, and a first bonding ball disposed on the second lead frame, the first bonding ball spaced apart from a first contact point, which is in contact with the first wire and the second lead frame, wherein the first bonding ball is disposed between the first wire and the second lead frame to electrically interconnect the first wire and the second lead frame.

Abstract: An integrated circuit assembly is fabricated on a metal substrate strip in an array format that has raised circuitry pattern formed by photolithographic and metal etching processes. The circuitry pattern is formed on one side of the metal substrate only. The raised circuitry's etch depth extends partially through the metal substrate. Die attachment can be performed using a non-conductive material applied directly onto and around the raised circuitry features directly under the die. After wirebond and molding processes, the molded metal substrate strip assembly is processed through a metal etching process to remove the metal substrate portion that is exposed beyond the mold cap. A solder mask coating can be applied to protect the metal circuitry and to define the package pad opening to form Land-Grid-Array (LGA) packages. Solder balls can also be attached to form Ball-Grid-Array (BGA) packages.

Abstract: A method of assembling an integrated circuit package is disclosed. The method comprises placing a die on a substrate of the integrated circuit package; coupling a plurality of wire bonds from a plurality of bond pads on the die to corresponding bond pads on the substrate; applying a non-conductive material to the plurality of wire bonds; and encapsulating the die and the plurality of wire bonds. An integrated circuit package is also disclosed.

Abstract: Provided is a semiconductor device and a method of manufacturing the semiconductor device, in which the semiconductor device has a semiconductor element having a plurality of wires bonded to the semiconductor element with sufficient bonding reliability and has a good heat dissipation property. A semiconductor device in which a first wire is ball bonded on an electrode, and a second wire is further bonded on the ball-bonded first wire, and the first wire or an end of the second wire defines a space between itself and the ball portion of the first wire.

Abstract: An integrated circuit assembly is fabricated on a metal substrate strip in an array format that has raised circuitry pattern formed by photolithographic and metal etching processes. The circuitry pattern is formed on one side of the metal substrate only. The raised circuitry's etch depth extends partially through the metal substrate. Die attachment can be performed using a non-conductive material applied directly onto and around the raised circuitry features directly under the die. After wirebond and molding processes, the molded metal substrate strip assembly is processed through a metal etching process to remove the metal substrate portion that is exposed beyond the mold cap. A solder mask coating can be applied to protect the metal circuitry and to define the package pad opening to form Land-Grid-Array (LGA) packages. Solder balls can also be attached to form Ball-Grid-Array (BGA) packages.

Abstract: A semiconductor chip (101) with bond pads (110) on a substrate (103) with rows and columns of regularly pitched metal contact pads (131). A zone comprises a first pair (131a, 131b) and a parallel second pair (131c, 131d) of contact pads, and a single contact pad (131e) for ground potential; staggered pairs of stitch pads (133) connected to respective pairs of adjacent contact pads by parallel and equal-length traces (132a, 132b, etc.). Parallel and equal-length bonding wires (120a, 120b, etc.) connect bond pad pairs to stitch pad pairs, forming differential pairs of parallel and equal-length conductor lines. Two differential pairs in parallel and symmetrical position form a transmitter/receiver cell for conducting high-frequency signals.

Abstract: A low profile semiconductor package is disclosed including at least first and second stacked semiconductor die mounted to a substrate. The first and/or second semiconductor die may be fabricated with a plurality of redistribution pads formed over and electrically coupled to a plurality of bond pads. After the semiconductor die are formed and diced from the wafer, the die may be mounted to the substrate using a low profile reverse wire bond according to the present invention. In particular, a wedge bond may be formed between the wire and the redistribution pad without having to use a second wire bond ball on the die bond pad as in conventional reverse ball bonding processes.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base substrate having a base substrate top side; mounting a base integrated circuit over the base substrate top side, the base integrated circuit having an active side opposite an inactive side with the inactive side facing the base substrate top side; attaching a peripheral interconnect to the base substrate top side and a device peripheral pad of the base integrated circuit at the active side; mounting an interposer over the base integrated circuit and the peripheral interconnect, the interposer having an interposer top side and a window; and attaching a central interconnect to the interposer top side and a device central pad of the base integrated circuit at the active side, the central interconnect through the window.

Abstract: A semiconductor device may include: first and second wiring boards separated from each other via a gap; a semiconductor chip; first and second groups of electrode pads; and first and second groups of connection pads. The semiconductor chip is fixed to upper surfaces of the first and second wiring boards, and has a first portion adjacent to the gap. The first and second groups of electrode pads are disposed on the first portion. The first and second groups of electrode pads are aligned adjacent to side surfaces of the first and second wiring boards, respectively. The side surfaces of the first and second wiring boards face each other. The first and second groups of connection pads are disposed on lower surfaces of the first and second wiring boards, respectively. The first and second groups of connection pads are aligned adjacent to the side surfaces of the first and second wiring boards, respectively.

Abstract: In a method for producing a power semiconductor arrangement, an insulation carrier with a top side, a metallization, and a contact pin with a first end are provided. The metallization is attached to the top side and a target section of the metallization is determined. After the metallization is attached to the top side of the insulation carrier, the first end of the contact pin is pressed into the target section such that the first end is inserted in the target section. Thereby, an interference fit and an electrical connection are established between the first end of the contact pin and the target section of the metallization.

Abstract: A microelectronic package can include wire bonds having bases bonded to respective ones of conductive elements exposed at a surface of a substrate. The wire bonds may have exterior edge surfaces disposed at an angle between 25° and 92° relative to the bases, and ends remote, e.g., opposite, from the bases, and remote from the ends which are connected to the bases. A dielectric encapsulation layer extends from the substrate and covers portions of the wire bonds such that covered portions of the wire bonds are separated from one another by the encapsulation layer, wherein unencapsulated portions of the wire bonds are defined by portions of the wire bonds that are uncovered by the encapsulation layer, the unencapsulated portions including the ends of the wire bonds.

Abstract: In an embodiment, a die package may be provided. The die package may include at least one first height adjusting structure, the at least one first height adjusting structure may include a first adjusting height relative to a common plane; at least one second height adjusting structure may be positioned adjacent to the at least one first height adjusting structure, the at least one second height adjusting structure may include a second adjusting height relative to the common plane; wherein the second adjusting height may be different from the first adjusting height relative to the common plane; a first die may be positioned on the at least one first height adjusting structure; and a mold housing substantially surrounding the at least one first height adjusting structure, the at least one second height adjusting structure and the first die.

Abstract: Primarily disclosed is a wafer-level chip-scale-package (WLCSP) for wire-bonding connection. A first encapsulating layer is formed over a passivation layer of a chip. An RDL (redistribution wiring layer) is formed on the first encapsulating layer. A plurality of wire-bonding pads are stacked on the wiring terminals of the RDL on the first encapsulating layer. Each wire-bonding pad has a top surface and a sidewall. A surface plated layer completely covers the top surfaces of the wire-bonding pads. A second encapsulating layer is formed over the first encapsulating layer to encapsulate the RDL and the sidewalls of the wire-bonding pads. The openings of the second encapsulating layer are smaller than the top surfaces of the corresponding wire-bonding pads to partially encapsulate the surface plated layer. Accordingly, it can resolve the issue of die crack when wire-bonding on thinned chips.

Abstract: A semiconductor device includes a substrate, an insulating substrate mounted on the substrate, a metal pattern formed on the insulating substrate, an electronic part mounted on the metal pattern across a bond, and a wire member, separate from a wiring wire, which contains a material repellent to the bond and is formed on the metal pattern and around the electronic part.

Abstract: In a method of manufacturing a semiconductor package including a wire binding process, a first end of the bonding wire is bonded to a first pad so as to form a first bond portion. A second end of the bonding wire is bonded to a second pad, wherein an interface surface between the bonding wire and the second pad has a first connecting area. The bonded second end of the bonding wire is scrubbed so as to form a second bond portion, wherein a new interface surface between the bonding wire and the second pad has a second connecting area larger than the first connecting area. A remainder of the bonding wire is separated from the second bond portion.

Abstract: An improved system and method for assigning power and ground pins and single ended or differential signal pairs for a ball grid array semiconductor package. In certain embodiments, the system uses a hexagonal pattern where the grid may be represented by a multiplicity of nested hexagonal patterns.

Abstract: In accordance with one or more embodiments, a flange package comprises a flange and an interposer having two or more fingers disposed in an interposer trench. The flange has a mold lock formed about a periphery of the interposer trench. A dielectric ring comprising a dielectric material is formed in the interposer trench, and in and around the periphery of the mold lock. A semiconductor die is disposed within the dielectric ring having gate pads and source pads formed on a first side, and having drain pads disposed on a second side of the die. The gate pads are coupled to the interposer and the source pads are coupled to the flange. A gate lead is coupled to the interposer and a drain lead is coupled to the drain pads. Other embodiments are disclosed.

Abstract: Microelectronic devices having intermediate contacts, and associated methods of packaging microelectronic devices with intermediate contacts, are disclosed herein. A packaged microelectronic device configured in accordance with one embodiment of the invention includes a microelectronic die attached to an interconnecting substrate. The microelectronic die includes an integrated circuit electrically coupled to a plurality of terminals. Each of the terminals is electrically coupled to a corresponding first contact on the die with an individual wire-bond. Each of the first contacts on the die is electrically coupled to a corresponding second contact on the interconnecting substrate by a conductive coupler such as a solder ball.

Abstract: A semiconductor device according to the present invention includes a substrate, a semiconductor element which is mounted on the substrate, a protecting film which covers at least a part of the semiconductor element, and an encapsulation resin which encapsulates the semiconductor element and the protecting film, wherein between the protecting film and the encapsulation resin, there is at least one gap in which the protecting film does not stick to the encapsulation resin. According to the above mentioned configuration, it is possible to provide a semiconductor device having a superior stress-relief performance.

Abstract: A stack package includes a first package having a first semiconductor chip and a first encapsulation member which seals the first semiconductor chip. A second package is stacked on the first package, and includes a second semiconductor chip and a second encapsulation member which seals the second semiconductor chip. Flexible conductors are disposed within the first encapsulation member of the first package in such a way as to electrically connect the first package and the second package.

Abstract: A multi-die package includes a first semiconductor die and a second semiconductor die each having an upper surface with a plurality of bond pads disposed thereon. The upper surface of the second semiconductor die may be substantially coextensive with the upper surface of the first semiconductor die and extend substantially along a plane. The multi-die package also includes a plurality of bonding wires each coupling one of the bond pads on the upper surface of the first semiconductor die to a corresponding one of the bond pads on the upper surface of the second semiconductor die. A bonding wire of the plurality of bonding wires has a kink disposed at a height above the plane, a first hump disposed between the first semiconductor die and the kink, and a second hump disposed between the second semiconductor die and the kink.

Abstract: A surface mount semiconductor device has a semiconductor die encapsulated in a molding compound. Electrical contact elements of an intermediate set are disposed on the molding compound. A set of coated wires electrically connect bonding pads of the semiconductor die and the electrical contact elements of the intermediate set. A layer of insulating material covers the coated wires, the die and the electrical contact elements of the intermediate set. Electrically conductive elements are exposed at an external surface of the layer of insulating material and contact respective electrical contact elements of the intermediate set through the layer of insulating material.

Abstract: The semiconductor device includes: a semiconductor substrate; an insulating film provided on a surface of the semiconductor substrate; a porous metal film provided on the insulating film; a protective film provided on the porous metal film, and having an opening portion for defining a pad region; and a wire wire-bonded to the porous metal film in the pad region. The stress generated by the impact of wire-bonding is mostly absorbed in the porous metal film owing to the distortion of the porous metal film, preventing generation of cracks in the insulating film.

Abstract: An integrated circuit device including a substrate, a first internal bonding pad, a second internal bonding pad, an external bonding pad and a bonding wire is provided. A first circuit, a second circuit, at least one interconnect line and an electrostatic discharge protection circuit are embedded in the substrate. The first internal bonding pad is disposed on a surface of the substrate and electrically connected to the first circuit. The second internal bonding pad is disposed on the surface of the substrate and electrically connected to the second circuit. The first internal bonding pad is electrically connected to the second internal bonding pad via the bonding wire. The first internal bonding pad is electrically connected to the electrostatic discharge protection circuit via the interconnect line. The electrostatic discharge protection circuit is electrically connected to the external bonding pad which is used for electrically connecting an external package lead.

Abstract: A semiconductor device includes a plurality of electrodes formed on a semiconductor chip, and a plurality of wires each connecting each of the electrodes to an inner lead, and each having a plurality of bending points. A first wire of the plurality of the wires has a slope extending upwardly from a first bending point toward a second bending point, where the first bending point is being located at an upper end of a rising portion. The second bending point of the first wire is the highest bending point in the first wire. A second wire of the plurality of the wires has a slope extending downwardly from a first bending point toward a second bending point, where the first bending point is located at an upper end of a rising portion. The second bending point of the second wire is the lowest bending point in the second wire.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a pre-plated leadframe having a contact pad and a die paddle pad; forming an isolated contact from the pre-plated leadframe and the contact pad; mounting an integrated circuit die over the die paddle pad; and encapsulating with an encapsulation the integrated circuit die and the isolated contact, the encapsulation having a bottom surface which is planar and exposing in the bottom surface only the contact pad and the die paddle pad.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; connecting an integrated circuit die to the substrate, with the integrated circuit die having peripheral sides; molding a step mold covering one of the peripheral sides; attaching an intermediate die directly over the integrated circuit die, offset to one of the peripheral sides adjacent to the step mold; and directly connecting the intermediate die to the substrate.

Abstract: A semiconductor device has a single unit capable of improving adhesion to a cooling body and a heat dissipation performance, and an aggregate of the single units is capable of configuring any circuit at a low cost. A single unit (101) includes copper blocks (1, 8), an insulating substrate (6) with a conductive pattern, an IGBT chip (10), a diode chip (13), a collector terminal pin (15), implant pins (17) fixed to the chips (10) by solder (11), a printed circuit board (16) having the implant pins (17) fixed thereto, an emitter terminal pin (19), a control terminal pin (20), a collector terminal pin (15), and a resin case (21) having the above-mentioned components sealed therein. The copper blocks (1, 8) make it possible to improve adhesion to a cooling body and the heat dissipation performance. A plurality of single units (101) can be combined with an inter-unit wiring board to form any circuit.

Abstract: A semiconductor package has a semiconductor die disposed on a substrate. A bond wire is connected between a first bonding site on the semiconductor die and a second bonding site on the substrate. The first bonding site is a die bond pad; the second bonding site is a stitch bond. The second bonding site has a bond finger formed on the substrate, a conductive layer in direct physical contact with the bond finger, and a bond stud coupled to the bond wire and in direct physical contact with the conductive layer to conduct an electrical signal from the semiconductor die to the bond finger. The bond finger is made of copper. The conductive layer is made of copper or gold. The bond stud is made of gold and overlies a side portion and top portion of the copper layer.

Abstract: A semiconductor package having dual parallel wires is disclosed. A chip is attached on a substrate where the chip and the substrate are electrically connected by a bonding wire. The bonding wire consists of a first metal wire, a second metal wire, and an insulating body where the insulating body encapsulates the first and the second metal wires to make both metal wires parallel to each other. The insulating body forms a constant gap between the first and the second metal wires so that both metal wires do not contact to each other. Therefore, the electrical performance of the package can greatly be enhanced with the same productivity.

Abstract: An integrated circuit comprises a semiconductor die including N bond pad pairs each including a first bond pad and a second bond pad that is spaced from the first bond pad. N bond wires are associated with a respective one of the N bond pad pairs. Each of the bond wires have opposite ends that communicate with the first and second bond pads of a respective one of the N bond pad pairs. The first and second bond pads of the N bond pad pairs are connected to a reference potential and create a shielded area between the N bond pad pairs.

Abstract: A microelectronic assembly can include a microelectronic device, e.g., semiconductor chip, connected together with an interconnection element, e.g., substrate, the latter having signal contacts and reference contacts. The reference contacts can be connectable to a source of reference potential such as ground or a voltage source other than ground such as a voltage source used for power. Signal conductors, e.g., signal wirebonds can be connected to device contacts exposed at a surface of the microelectronic device. Reference conductors, e.g., reference wirebonds can be provided, at least one of which can be connected with two reference contacts of the interconnection element. The reference wirebond can have a run which extends at an at least substantially uniform spacing from a signal conductor, e.g., signal wirebond that is connected to the microelectronic device over at least a substantial portion of the length of the signal conductor.

Abstract: A bonding pad structure is provided that includes two conductive layers and a connective layer interposing the two conductive layers. The connective layer includes a contiguous, conductive structure. In an embodiment, the contiguous conductive structure is a solid layer of conductive material. In other embodiments, the contiguous conductive structure is a conductive network including, for example, a matrix configuration or a plurality of conductive stripes. At least one dielectric spacer may interpose the conductive network. Conductive plugs may interconnect a bond pad and one of the conductive layers.

Abstract: There is provided a bump structure for a semiconductor device, comprising a metal post formed on and electrically connected to an electrode pad on a substrate, a solder post formed on the top surface of the metal post, said solder post having the same horizontal width as the metal post and the top surface of the solder post being substantially rounded, and an intermetallic compound layer disposed at the interface between the metal post and the solder post. An oxide layer formed on the solder post prevents solder post under reflow from being changed into a spherical shape. An intermetallic compound layer may be formed by an aging process at the interface between the metal post and the solder post. The bump structure can realize fine pitch semiconductor package without a short between neighboring bumps.

Abstract: Disclosed are: a semiconductor device that comprises a semiconductor element to which a plurality of wires are bonded, wherein bonding strength of the wires is high and sufficient bonding reliability is achieved; and a method for manufacturing the semiconductor device. Specifically disclosed is a semiconductor device which is characterized by comprising a first wire that has one end bonded onto an electrode and the other end bonded to a second bonding point that is out of the electrode, and a second wire that has one end bonded onto the first wire on the electrode and the other end bonded to a third bonding point that is out of the electrode. The semiconductor device is also characterized in that the bonded portion of the first-mentioned end of the second wire covers at least apart of the upper surface and the lateral surface of the first wire.

Abstract: A semiconductor chip is mounted on a heat sink disposed inside a through-hole of a wiring board, electrodes of the semiconductor chip and connecting terminals of the wiring board are connected by bonding wires, a sealing resin is formed to cover the semiconductor chip and the bonding wires, and solder balls are formed on the lower surface of the wiring board, thereby constituting the semiconductor device. The heat sink is thicker than the wiring board. The heat sink has a protruded portion protruding to outside from the side surface of the heat sink, the protruded portion is located on the upper surface of the wiring board outside the through-hole, and the lower surface of the protruded portion contacts to the upper surface of the wiring board. When the semiconductor device is manufactured, the heat sink is inserted from the upper surface side of the wiring board.

Abstract: A system-in-package (SiP) package is provided. In one embodiment, the SiP package comprises a substrate having a first surface and a second surface opposite the first surface, the substrate having a set of bond wire studs on bond pads formed on the second surface thereof; a first semiconductor chip having a first surface and a second surface opposite the first surface, wherein the first surface of the first semiconductor chip is mounted to the second surface of the substrate by means of solder bumps; an underfill material disposed between the first semiconductor chip and the substrate, encapsulating the solder bumps; a second semiconductor chip having a first surface and a second surface opposite the first surface, wherein the first surface of the second semiconductor chip is mounted to the second surface of the first semiconductor chip; and a set of bond wires electrically coupled from the second semiconductor chip to the set of bond wire studs on the substrate.

Abstract: In one embodiment, a semiconductor device includes a printed wiring board provided with a connection pad, a semiconductor chip provided with an electrode pad and a conductive wire. One end of the conductive wire is connected to the connection pad of the printed wiring board and the other end of the conductive wire is connected to the electrode pad of the semiconductor chip. The semiconductor chip is mounted on the printed wiring board so that the first surface of the semiconductor chip provided with the electrode pad is oriented opposite to the printed wiring board. A first insulating layer is formed on the first surface of the semiconductor chip oriented opposite to the printed wiring board. A thermoplastic second insulating layer is formed on the first insulating layer. Part of the conductive wire between one end and the other end is buried in the second insulating layer.

Abstract: Optical structures having an array of protuberances between two layers having different refractive indices are provided. The array of protuberances has vertical and lateral dimensions less than the wavelength range of lights detectable by a photodiode of a CMOS image sensor. The array of protuberances provides high transmission of light with little reflection. The array of protuberances may be provided over a photodiode, in a back-end-of-line interconnect structure, over a lens for a photodiode, on a backside of a photodiode, or on a window of a chip package.

Abstract: According to one embodiment, there is provided a semiconductor package including: a semiconductor chip; a resin portion formed to cover the semiconductor chip; a wiring structure formed on the resin portion and electrically connected to the semiconductor chip; and a warpage preventing member provided above the resin portion to have a thermal expansion coefficient closer to that of the semiconductor chip than to that of the wiring structure.