Abstract: There is provided a semiconductor device including a first electrode including a first plate portion, the first plate portion including a first surface and a second surface facing the first surface, a plurality of semiconductor chips provided above the second surface, and a second electrode including a second plate portion provided above the semiconductor chips, the second plate portion including a third surface facing the second surface and a fourth surface facing the third surface, the second plate portion including a plurality of protrusion portions provided between the semiconductor chips and the third surface, the protrusion portions being connected to the third surface, each of the protrusion portions including a top surface including the same shape as a shape of each of the semiconductor chips in a plane parallel to the second surface, the second plate portion including a second outer diameter larger than a first diameter of a smallest circle circumscribing the protrusion portions provided on an outerm

Abstract: A mounted structure includes an electrode of a substrate, an electrode of a semiconductor element, and a mounted layers for bonding the electrode of the substrate and the electrode of the semiconductor element, and the mounted layers includes: a first intermetallic compound layer containing a CuSn-based intermetallic compound; a Bi layer; a second intermetallic compound layer containing a CuSn-based intermetallic compound; a Cu layer; and a third intermetallic compound layer containing a CuSn-based intermetallic compound, and the above layers are sequentially arranged from the electrode of the substrate toward the electrode of the semiconductor element to configure the mounted layers.

Abstract: A semiconductor package includes a first package and a second package, a connection terminal disposed between the first and second packages and including a first solder ball and a second solder ball that are vertically stacked, a solder passivation layer with which a surface of at least one of the first and second solder balls is coated, and a ring-shaped short prevention part surrounding a coupling portion between the first and second solder balls.

Abstract: Embodiments of the present disclosure are directed towards flux materials for heated solder placement and associated techniques and configurations. In one embodiment, a method includes depositing a flux material on one or more pads of a package substrate, the flux material including a rosin material and a thixotropic agent and depositing one or more solder balls on the flux material disposed on the one or more pads, wherein depositing the one or more solder balls on the flux material is performed at a temperature greater than 80° C., and wherein the rosin material and the thixotropic agent are configured to resist softening at the temperature greater than 80° C. Other embodiments may be described and/or claimed.

Abstract: A solder interconnect structure is provided with non-wettable sidewalls and methods of manufacturing the same. The method includes forming a nickel or nickel alloy pillar on an underlying surface. The method further includes modifying the sidewall of the nickel or nickel alloy pillar to prevent solder wetting on the sidewall.

Abstract: A package structure, a method of fabricating the package structure, and a package-on-package device are provided, where the package structure includes a metal sheet having perforations and a semiconductor chip including an active surface having electrode pads thereon, where the semiconductor chip is combined with the metal sheet via an inactive surface thereof. Also, a protective buffer layer is formed on the active surface to cover the conductive bumps, and the perforations are arranged around a periphery of the inactive surface of the semiconductor chip. Further, an encapsulant is formed on the metal sheet and in the perforations, for encapsulating the semiconductor chip and exposing the protective buffer layer; and a circuit fan-out layer is formed on the encapsulant and the protective buffer layer and having conductive vias penetrating the protective buffer layer and electrically connecting to the conductive bumps.

Abstract: A junction body has a first member and a second member each of which is provided with a joining surface whose main component is copper. A solder member containing, in a tin-base solder material, a three-dimensional web structure whose main component is copper is provided between the first member and the second member. A copper-tin alloy whose average thickness is 2 ?m or more but 20 ?m or less is provided between the joining surfaces and the three-dimensional web structure.

Abstract: The semiconductor device according to the present invention includes a semiconductor chip, a solid plate to which the semiconductor chip is bonded, and a bonding member made of a BiSn-based material interposed between the semiconductor chip and the solid plate, while the bonding member has a heat conduction path made of Ag for improving heat conductivity between the semiconductor chip and the solid plate.

Abstract: Disclosed herein is an electronic package system utilizing a module having a liquid contact material to prevent mechanically and thermally induced strains in an electrical joint. The conductivity of the liquid contact material provides electrical communication between the required electronic components of the package system. The ability of the liquid contact material to flow prevents the creation of stresses and affords an electronic package design tolerant of small displacements or torsions. Thus, the liquid contact material enables a floating contact with high electrical reliability.

Abstract: One exemplary disclosed embodiment comprises a semiconductor package including multiple transistors having a common drain coupled to an exposed conductive clip. A driver integrated circuit (IC) may control the transistors for various power applications. By exposing a top surface of the exposed conductive clip outside of a mold compound of the package, enhanced thermal performance is provided. Additionally, the conductive clip provides a short distance, high current carrying route between transistors of the package, providing higher electrical performance and reduced form factor compared to conventional designs with individually packaged transistors.

Abstract: A first Sn absorption layer is formed on a principal surface of a first substrate, the first Sn absorption layer being made of metal absorbing Sn from AuSn alloy and lowering a relative proportion of Sn in the AuSn alloy. A second Sn absorption layer is formed on a principal surface of a second substrate, the second Sn absorption layer being made of metal absorbing Sn from AuSn alloy and lowering a relative proportion of Sn in the AuSn alloy. A solder layer made of AuSn alloy is formed at least on one Sn absorption layer of the first and second Sn absorption layers. The first and second substrates are bonded together by melting the solder layer in a state that the first and second substrates are in contact with each other, with the principal surfaces of the first and second substrates facing each other.

Abstract: A bump contact electrically connects a conductor on a substrate and a contact pad on a semiconductor device mounted to the substrate. The first end of an electrically conductive pillar effects electrical contact and mechanical attachment of the pillar to the contact pad with the pillar projecting outwardly from the semiconductor device. A solder crown reflowable at a predetermined temperature into effecting electrical contact and mechanical attachment with the conductor is positioned in axial alignment with the second end of the pillar. A diffusion barrier electrically and mechanically joins the solder bump to the second end of the pillar and resists electro-migration into the first end of the solder crown of copper from the pillar. One diffusion barrier takes the form of a 2-20 micron thick control layer of nickel, palladium, titanium-tungsten, nickel-vanadium, or tantalum nitride positioned between the pillar and the solder crown.

Abstract: A light emitting diode structure is disclosed that includes a light emitting active portion formed of epitaxial layers and carrier substrate supporting the active portion. A bonding metal system that predominates in nickel and tin joins the active portion to the carrier substrate. At least one titanium adhesion layer is between the active portion and the carrier substrate and a platinum barrier layer is between the nickel-tin bonding system and the titanium adhesion layer. The platinum layer has a thickness sufficient to substantially prevent tin in the nickel tin bonding system from migrating into or through the titanium adhesion layer.

Abstract: According to one embodiment, a semiconductor substrate, a metal film, a surface modifying layer, and a redistribution trace are provided. On the semiconductor substrate, a wire and a pad electrode are formed. The metal film is formed over the semiconductor substrate. The surface modifying layer is formed on a surface layer of the metal film and improves the adhesion with a resist pattern. The redistribution trace is formed on the metal film via the surface modifying layer.

Abstract: A method for fabricating a semiconductor device having a GaN-based semiconductor layer on a first surface of a substrate made of SiC, a pad being provided on the GaN-based layer, includes: forming a first via hole in the substrate by etching, with fluorine based gas, from a second surface of the substrate opposite to the first surface, the etching being carried out with the GaN-based layer being used as an etch stopper; and forming a second via hole in the GaN-based semiconductor layer, with chlorine based gas, from a bottom surface of the first via hole, the etching being carried out with the pad being used as an etching stopper, the chlorine based gas being an etchant different from the fluorine based gas.

Abstract: A light emitting diode structure is disclosed that includes a light emitting active portion formed of epitaxial layers and carrier substrate supporting the active portion. A bonding metal system that predominates in nickel and tin joins the active portion to the carrier substrate. At least one titanium adhesion layer is between the active portion and the carrier substrate and a platinum barrier layer is between the nickel-tin bonding system and the titanium adhesion layer. The platinum layer has a thickness sufficient to substantially prevent tin in the nickel tin bonding system from migrating into or through the titanium adhesion layer.

Abstract: An integrated circuit device comprises a first semiconductor chip on a first substrate and a second semiconductor chip on a second substrate. A side surface of the first semiconductor chip is facing a side surface of the second semiconductor chip. At least one electric cable is provided to be connecting the first substrate to the second substrate.

Abstract: A chip structure comprising a silicon substrate, a MOS device, dielectric layers, a metallization structure, a passivation layer, a plurality of metal layers and a polymer layer. The metallization structure comprises a first circuit layer and a second circuit layer over the first circuit layer, and comprises a damascene electroplated copper. The passivation layer is over the metallization structure and dielectric layers, the passivation layer including a first opening exposing a contact point of the metallization structure. The polymer layer is disposed over the passivation layer and the first metal layer, a second opening in the polymer layer being over a second contact point of the first metal layer, the polymer layer covering a top surface and sidewall of the first metal layer. The second contact point is connected to the first contact point through the first opening, the second opening not being vertically over the first opening.

Abstract: Each second electrode formed on a second main surface of a compound semiconductor layer of a light emitting device has an alloyed contact layer disposed contacting the second main surface, aimed at reducing contact resistance with the compound semiconductor layer, and a solder layer connecting the alloyed contact layer to the conductive support. The solder layer forms therein a Sn-base solder layer disposed on the alloyed contact layer side having a melting point lower than the alloyed contact layer, and a Au—Sn-base solder layer disposed contacting the Sn-base solder layer opposed to the alloyed contact layer side, containing total Au and Sn of 80% or more, and having a melting point higher than the Sn-base solder layer. This configuration can provide excellent reliability of bonding between the Au—Sn-base solder layer and the alloyed contact layer, and consequently less causative of delamination of the Au—Sn-base solder layer.

Abstract: Techniques and structures have been developed for providing lead-free column grid array interconnect structures. An exemplary interconnect has a body, a first joint, and a second joint, all having compositions off the eutectic composition in a ternary alloy system, the first joint having a ternary composition distinct from the body composition, and the second joint having a ternary composition distinct from the body composition and the first joint composition. The interconnect may be formed by solidifying a solder, having a Sn-poor ternary composition in the Sn—Ag—Cu alloy system, in contact with a column, having a Ag-rich Cu-deficient composition in the same system, and a bonding pad or bare substrate. A second solder, having a Sn-rich ternary composition, may be solidified in contact with the column and a second bonding pad or bare substrate. In some embodiments joints may be severed and reformed by remelting and resolidifying the lower-liquidus solder.

Abstract: A method of manufacturing a semiconductor device in which a semiconductor element 10 is mounted on a substrate 20 through a flip-chip connection, includes the steps of cladding gallium as a bonding material 30 to a connecting pad 22 formed on a surface of the substrate 20, diffusing copper from the connecting pad 22 formed of the copper into the bonding material 30 through heating under vacuum, thereby bringing a state of a solid solution of the gallium and the copper, and aligning a connecting bump 12 formed on the semiconductor element 10 with the connecting pad 22 and bonding the connecting bump 12 to the connecting pad 22 through the bonding material 30 in a state of a solid solution under heating.

Abstract: A semiconductor device having bonding pads on a semiconductor substrate includes: an upper copper layer that is formed on the lower surface of the bonding pads with a barrier metal interposed and that has a copper area ratio that is greater than layers in which circuit interconnects are formed; and a lower copper layer that is electrically insulated from the upper copper layer and that is formed closer to the semiconductor substrate than the upper copper layer.

Abstract: A foamed bulk metallic glass electrical connection is formed on a substrate of an integrated circuit package. The foamed bulk metallic glass electrical connection exhibits a low modulus that resists cracking during shock and dynamic loading. The foamed bulk metallic glass electrical connection is used as a solder bump for communication between an integrated circuit device and external structures. A process of forming the foamed bulk metallic glass electrical connection includes mixing bulk metallic glass with a blowing agent.

Abstract: A semiconductor chip packaging on a flexible substrate is disclosed. The chip and the flexible substrate are provided with corresponding raised and indented micron-scale contact pads with the indented contact pads partially filled with a liquid amalgam. After low temperature amalgam curing, the chip and the substrate form a flexible substrate IC packaging with high conductivity, controllable interface layer thickness, micron-scale contact density and low process temperature. Adhesion between the chip and the substrate can be further enhanced by coating other areas with non-conducting adhesive.

Abstract: An integrated circuit device comprises a first semiconductor chip on a first substrate and a second semiconductor chip on a second substrate. A side surface of the first semiconductor chip is facing a side surface of the second semiconductor chip. At least one electric cable is provided to be connecting the first substrate to the second substrate.

Abstract: A method of creating an electrical connection involves providing a pair of contacts each on one of two different chips, the pair of contacts defining a volume therebetween, the volume containing at least two compositions each having melting points, the compositions having been selected such that heating to a first temperature will cause a change in at least one of the at least two compositions such that the change will result in a new composition having a new composition melting point of a second temperature, greater than the first temperature and the melting point of at least a first of the at least two compositions, and heating the pair of contacts and the at least two compositions to the first temperature.

Abstract: There is disclosed a method of making an electronic package (10) by: forming a metal base (50) on which to build the components of an electronic package; applying a mask layer (60) on the base to an area that is not to be occupied by interconnection pads (200) or die attachment pads (201) of the package; plating layers of metal on the un-masked areas of the base to form the interconnection and die attachment pads (200, 201); removing the mask layer; mounting a semiconductor die (302) to at least one die attachment pad (201); electrically connecting the semiconductor die (302) to one or more interconnection pads (200); embedding the components on the base in an encapsulation material (300) to form a package; removing the metal base (50) to leave a package panel; and cutting the panel into discrete package units.

Abstract: An electronic device has a substrate that has first and second peripheral portions. The first peripheral portion provides a shearing position for separation. The electronic device has a plurality of wiring layers one of which forms a functional surface wiring on the substrate, an electronic element mounted on the substrate, and an encapsulation member formed over the substrate and the electronic element. The surface wiring is selectively disposed under the encapsulation member and in an area adjacent to the second peripheral portion.

Abstract: A solder, in particular a thin-film solder, for joining microelectromechanical components, wherein the solder is a eutectic mixture of gold and bismuth. Components and devices joined by a solder of this type are also disclosed, in addition to processes for producing such components or devices.

Abstract: The invention relates to a layer sequence on a substrate made from copper, a copper-based alloy, a copper-plated substrate or a nickel or a nickel-based alloy for production of a composite material, in which a covering layer, consisting of tin or a tin-based alloy, which is arranged at least over part of the substrate, a barrier layer, which is located between the substrate and the covering layer and is in direct contact with the substrate, the barrier layer consisting of at least one element selected from the group consisting of Fe, Co, Nb, Mo or Ta, and an intermediate layer and a reaction layer, which is located between the barrier layer and the covering layer, the intermediate layer consisting of at least one element selected from the group consisting of Cu and Ni. The reaction layer required between covering layer and intermediate layer consists of Ag, an Ag alloy or Pt and Pd and its alloys.