Assembly Of Semiconductor Devices On Lead Frame (epo) Patents (Class 257/E23.052)
  • Patent number: 10096572
    Abstract: A power semiconductor module that comprises plural arrangements of power semiconductor elements comprising a power semiconductor bare chip which one electrode portion thereof is connected to a metal plate which at least one external connecting terminal is formed and other external connecting terminals which are electrically connected to other electrode portions of the power semiconductor bare chip, and that are contained in a same package, comprises wherein the power semiconductor elements are basically same outline, electrodes of the bare chip of the power semiconductor elements are mutually connected between the power semiconductor elements with a metal connector or a wiring, and the package is a resin mold package that seals the power semiconductor elements with an electrical insulating resin.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: October 9, 2018
    Assignee: NSK LTD.
    Inventors: Shigeru Shimakawa, Takashi Sunaga, Takaaki Sekine
  • Patent number: 9035441
    Abstract: A semiconductor device of the present invention includes a resin package, a semiconductor chip sealed in the resin package, and having first and second pads on a front surface, a lead integrated island sealed in the resin package, to one surface of which a back surface of the semiconductor chip is bonded, and the other surface of an opposite side to the one surface of which is partially exposed from a bottom surface of the resin package as a first pad connecting terminal for electrical connection between the first pad and outside and a back connecting terminal for electrical connection between the back surface of the semiconductor chip and outside separately from each other, and a lead formed separately from the lead integrated island, sealed in the resin package, one surface of which is connected with the second pad by a wire, and the other surface of an opposite side to the one surface of which is exposed from a bottom surface of the resin package as a second pad connecting terminal for electrical connectio
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: May 19, 2015
    Assignee: ROHM CO., LTD.
    Inventors: Akihiro Koga, Toichi Nagahara
  • Patent number: 9024420
    Abstract: Some exemplary embodiments of a multi-chip module (MCM) power quad flat no-lead (PQFN) semiconductor package utilizing a leadframe for electrical interconnections have been disclosed. One exemplary embodiment comprises a PQFN semiconductor package comprising a leadframe, a driver integrated circuit (IC) coupled to the leadframe, a plurality of vertical conduction power devices coupled to the leadframe, and a plurality of wirebonds providing electrical interconnects, including at least one wirebond from a top surface electrode of one of the plurality of vertical conduction power devices to a portion of the leadframe, wherein the portion of the leadframe is electrically connected to a bottom surface electrode of another of the plurality of vertical conduction power devices. In this manner, efficient multi-chip circuit interconnections can be provided in a PQFN package using low cost leadframes.
    Type: Grant
    Filed: November 11, 2013
    Date of Patent: May 5, 2015
    Assignee: International Rectifier Corporation
    Inventors: Dean Fernando, Roel Barbosa
  • Patent number: 8987877
    Abstract: A semiconductor device of the present invention comprises: an outer package; a first lead frame including a first relay lead, a first die pad with a power element mounted thereon, and a first external connection lead which has an end protruding from the outer package; and a second lead frame including a second relay lead, a second die pad with a control element mounted thereon, and a second external connection lead which has an end protruding from the outer package, wherein the first die pad and the second die pad or the first external connection lead and the second relay lead are joined to each other at a joint portion, and an end of the second relay lead extending from a joint portion with the first relay lead is located inside the outer package.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: March 24, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Masanori Minamio, Zyunya Tanaka, Shin-ichi Ijima
  • Patent number: 8981542
    Abstract: A semiconductor power module according to the present invention includes a base member, a semiconductor power device having a surface and a rear surface with the rear surface bonded to the base member, a metal block, having a surface and a rear surface with the rear surface bonded to the surface of the semiconductor power device, uprighted from the surface of the semiconductor power device in a direction separating from the base member and employed as a wiring member for the semiconductor power device, and an external terminal bonded to the surface of the metal block for supplying power to the semiconductor power device through the metal block.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: March 17, 2015
    Assignee: Rohm Co., Ltd.
    Inventor: Toshio Hanada
  • Patent number: 8981540
    Abstract: A package structure is disclosed, which includes: a carrier having a recessed portion formed on a lower side thereof and filled with a dielectric material; a semiconductor element disposed on an upper side of the carrier and electrically connected to the carrier; and an encapsulant formed on the upper side of the carrier for encapsulating the semiconductor element. Therein, the dielectric material is exposed from the encapsulant. As such, when the carrier is disposed on a circuit board, the dielectric material is sandwiched between the lower side of the carrier and the circuit board to form a decoupling capacitor, thereby improving the power integrity.
    Type: Grant
    Filed: June 20, 2013
    Date of Patent: March 17, 2015
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Cheng-Yu Chiang, Wen-Jung Chiang, Hsing-Hung Lee
  • Patent number: 8969137
    Abstract: Embodiments described herein relate to a method of manufacturing a packaged circuit having a solder flow-impeding plug on a lead frame. The method includes partially etching an internal surface of a lead frame at dividing lines between future sections of the lead frame as first partial etch forming a trench. A non-conductive material that is adhesive to the lead frame is applied in the trench, such that the non-conductive material extends across the trench to form the solder flow-impeding plug. One or more components are attached to the internal surface of the lead frame and encapsulated. An external surface of the lead frame is etched at the dividing lines to disconnect different sections of lead frame as a second partial etch.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: March 3, 2015
    Assignee: Intersil Americas LLC
    Inventors: Randolph Cruz, Loyde M. Carpenter, Jr.
  • Patent number: 8921986
    Abstract: A semiconductor power chip, may have a semiconductor die having a power device fabricated on a substrate thereof, wherein the power device has at least one first contact element, a plurality of second contact elements and a plurality of third contact elements arranged on top of the semiconductor die; and an insulation layer disposed on top of the semiconductor die and being patterned to provide openings to access the plurality of second and third contact elements and the at least one first contact element.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 30, 2014
    Assignee: Microchip Technology Incorporated
    Inventors: Gregory Dix, Roger Melcher
  • Patent number: 8907437
    Abstract: A current sensor packaged in an integrated circuit package to include a magnetic field sensing circuit, a current conductor and an insulator that meets the safety isolation requirements for reinforced insulation under the UL 60950-1 Standard is presented. The insulator is provided as an insulation structure having at least two layers of thin sheet material. The insulation structure is dimensioned so that plastic material forming a molded plastic body of the package provides a reinforced insulation. According to one embodiment, the insulation structure has two layers of insulating tape. Each insulating tape layer includes a polyimide film and adhesive. The insulation structure and the molded plastic body can be constructed to achieve at least a 500 VRMS working voltage rating.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: December 9, 2014
    Assignee: Allegro Microsystems, LLC
    Inventors: Shaun D. Milano, Weihua Chen
  • Patent number: 8901580
    Abstract: A package includes: a leadframe made of conductive material and on which the plurality of electronic components are to be mounted, the leadframe including a first surface and a second surface opposite to the first surface and including a plurality of elongate portions arranged in parallel to each other with a gap interposed between the adjacent elongate portions; a heat sink including a first surface and a second surface opposite to the first surface, wherein the leadframe is disposed above the heat sink such that the second surface of the leadframe faces the first surface of the heat sink; and a resin portion, wherein the leadframe and the heat sink are embedded in the resin portion such that the first surface of the leadframe and the second surface of the heat sink are exposed from the resin portion, respectively.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: December 2, 2014
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Tadashi Arai, Yasuyuki Kimura, Toshio Kobayashi, Kazutaka Kobayashi
  • Patent number: 8896108
    Abstract: The invention enhances resistance to a surge in a semiconductor device having a semiconductor die mounted on a lead frame. An N type embedded layer, an epitaxial layer and a P type semiconductor layer are disposed on the front surface of a P type semiconductor substrate forming an IC die. A metal thin film is disposed on the back surface of the semiconductor substrate, and a conductive paste containing silver particles and so on is disposed between the metal thin film and a metal island. When a surge is applied to a pad electrode disposed on the front surface of the semiconductor layer, the surge current flowing from the semiconductor layer into the semiconductor substrate runs toward the metal island through the metal thin film.
    Type: Grant
    Filed: September 9, 2011
    Date of Patent: November 25, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Yuichi Watanabe, Akira Yamane, Yasuo Oishibashi
  • Patent number: 8878348
    Abstract: A semiconductor device has a die support and external leads formed integrally from a single sheet of electrically conductive material. A die mounting substrate is mounted on the die support, with bonding pads coupled to respective external connection pads on an external connector side of the substrate. A die is attached to the die mounting substrate with die connection pads. Bond wires selectively electrically couple the die connection pads to the external leads and the bonding pads and electrically conductive external protrusions are mounted to the external connection pads. An encapsulant covers the die and bond wires. The external protrusions are located at a central region of a surface mounting side of the package and the external leads project outwardly from locations near the die support towards peripheral edges of the package.
    Type: Grant
    Filed: April 1, 2013
    Date of Patent: November 4, 2014
    Assignee: Freescale Semicondustor, Inc.
    Inventors: Meiquan Huang, Huan Wang, Jinsheng Wang, Naikuo Zhou
  • Patent number: 8860071
    Abstract: In one embodiment, a semiconductor module includes a leadframe having a first side and an opposite second side. A semiconductor chip is disposed over the first side of the leadframe. A switching element is disposed under the second side of the leadframe. In another embodiment, a method of forming a semiconductor module includes providing a semiconductor device having a leadframe. A semiconductor chip is disposed over a first side of the leadframe. A switching element is attached at an opposite second side of the leadframe.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: October 14, 2014
    Assignee: Infineon Technologies AG
    Inventor: Ralf Otremba
  • Patent number: 8810013
    Abstract: An integrated circuit for implementing a switch-mode power converter is disclosed. The integrated circuit comprises at least a first semiconductor die having an electrically quiet surface, a second semiconductor die for controlling the operation of said first semiconductor die stacked on said first semiconductor die having said electrically quiet surface and a lead frame structure for supporting said first semiconductor die and electrically coupling said first and second semiconductor dies to external circuitry.
    Type: Grant
    Filed: May 9, 2013
    Date of Patent: August 19, 2014
    Assignee: Monolithic Power Systems, Inc.
    Inventors: Eric Yang, Jinghai Zhou, Hunt Hang Jiang
  • Patent number: 8803303
    Abstract: In a QFP with a chip-stacked structure in which a lower surface of a die pad is exposed from a lower surface of a sealing member, a semiconductor chip having a BCB film, which is made of a polymeric material containing at least benzocyclobutene in its backbone as an organic monomer and formed on its surface, is mounted at a position (second stage) that is away from the die pad. As a result, even when moisture invades through the interface between the die pad and the sealing member, it is possible to prolong the time required for the moisture to reach the semiconductor chip, and subsequently to make moisture absorption defect less likely to occur.
    Type: Grant
    Filed: December 25, 2013
    Date of Patent: August 12, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Koichi Kanemoto
  • Patent number: 8796832
    Abstract: A wiring device for a semiconductor device, a composite wiring device for a semiconductor device and a resin-sealed semiconductor device are provided, each of which is capable of mounting thereon a semiconductor chip smaller than conventional chips and being manufactured at lower cost. The wiring device connects an electrode on a semiconductor chip with an external wiring device, and has an insulating layer, a metal substrate and a copper wiring layer. The wiring device has a semiconductor chip support portion provided on the side of the copper wiring layer with respect to the insulating layer. The copper wiring layer includes a first terminal, a second terminal and a wiring portion. The first terminal is connected with the electrode. The second terminal is connected with the external wiring device. The wiring portion connects the first terminal with the second terminal.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: August 5, 2014
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Susumu Baba, Masachika Masuda, Hiromichi Suzuki
  • Patent number: 8779568
    Abstract: An integrated circuit package system includes an external interconnect having a lead tip and a lead body, including a recess in the lead body including a first recess segment, having an orientation substantially parallel to the lengthwise dimension of the lead body, and a second recess segment intersecting and perpendicular to the first recess segment along a lead body top surface of the lead body, the first recess segment at a bottom portion of the second recess segment; an internal interconnect between an integrated circuit die and the external interconnect; and an encapsulation to cover the external interconnect with the recess filled.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: July 15, 2014
    Assignee: STATS ChipPAC Ltd.
    Inventors: Byung Tai Do, Sung Uk Yang
  • Patent number: 8779569
    Abstract: A semiconductor device 100 includes a first insulating material 110 attached to a second main surface 106b of a semiconductor chip 106, and a second insulating material 112 attached to side surfaces of the semiconductor chip 106, the first insulating material 110 and an island 102. The semiconductor chip 106 is fixed to the island 102 via the first insulating material 110 and the second insulating material 112. The first insulating material 110 ensures a high dielectric strength between the semiconductor chip 106 and the island 102. Though the second insulating material 112 having a modulus of elasticity greater than that of the first insulating material 110, the semiconductor chip 106 is firmly attached to the island 102.
    Type: Grant
    Filed: January 17, 2011
    Date of Patent: July 15, 2014
    Assignee: Rohm Co., Ltd.
    Inventors: Akihiro Kimura, Tsunemori Yamaguchi
  • Patent number: 8772914
    Abstract: A first semiconductor chip and a second semiconductor chip are overlapped with each other in a direction in which a first multilayer interconnect layer and a second multilayer interconnect layer are opposed to each other. When seen in a plan view, a first inductor and a second inductor are overlapped. The first semiconductor chip and the second semiconductor chip have non-opposed areas which are not opposed to each other. The first multilayer interconnect layer has a first external connection terminal in the non-opposed area, and the second multilayer interconnect layer has a second external connection terminal in the non-opposed area.
    Type: Grant
    Filed: January 15, 2013
    Date of Patent: July 8, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Yasutaka Nakashiba, Kenta Ogawa
  • Patent number: 8766419
    Abstract: Provided are a power module having a stacked flip-chip and a method of fabricating the power module. The power module includes a lead frame; a control device part including a control device chip; a power device part including a power device chip and being electrically connected to the lead frame; and an interconnecting substrate of which the control and power device parts are respectively disposed at upper and lower portions, and each of the control and power device chips may be attached to one of the lead frame and the interconnecting substrate using a flip-chip bonding method.
    Type: Grant
    Filed: December 21, 2009
    Date of Patent: July 1, 2014
    Assignee: Fairchild Korea Semiconductor, Ltd.
    Inventors: Seung-won Lim, O-Seob Jeon, Joon-seo Son, Keun-kyuk Lee, Yun-hwa Choi
  • Patent number: 8766420
    Abstract: A semiconductor device is configured that two or more semiconductor elements are stacked and mount on a lead frame, the aforementioned lead frame is electrically joined to the semiconductor element with a wire, and the semiconductor element, the wire and an electric junction are encapsulated with a cured product of an epoxy resin composition for encapsulating semiconductor device, and that the epoxy resin composition for encapsulating semiconductor device contains (A) an epoxy resin; (B) a curing agent; and (C) an inorganic filler, and that the (C) inorganic filler contains particles having particle diameter of equal to or smaller than two-thirds of a thinnest filled thickness at a rate of equal to or higher than 99.9% by mass.
    Type: Grant
    Filed: August 27, 2010
    Date of Patent: July 1, 2014
    Assignee: Sumitomo Bakelite Co., Ltd.
    Inventor: Shingo Itoh
  • Patent number: 8766421
    Abstract: A semiconductor power module according to the present invention includes a base member, a semiconductor power device having a surface and a rear surface with the rear surface bonded to the base member, a metal block, having a surface and a rear surface with the rear surface bonded to the surface of the semiconductor power device, uprighted from the surface of the semiconductor power device in a direction separating from the base member and employed as a wiring member for the semiconductor power device, and an external terminal bonded to the surface of the metal block for supplying power to the semiconductor power device through the metal block.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: July 1, 2014
    Assignee: Rohm Co., Ltd.
    Inventor: Toshio Hanada
  • Patent number: 8759955
    Abstract: Conventional semiconductor devices have a problem that it is difficult to prevent the short circuit between chips and to improve accuracy in temperature detection with the controlling semiconductor chips. In a semiconductor device of the present invention, a first mount region to which a driving semiconductor chip is fixedly attached and a second mount region to which a controlling semiconductor chip is fixedly attached are formed isolated from each other. A projecting area is formed in the first mount region, and the projecting area protrudes into the second mount region. The controlling semiconductor chip is fixedly attached to the top surfaces of the projecting area and the second mount region by use of an insulating adhesive sheet material. This structure prevents the short circuit between the two chips, and improves accuracy in temperature detection with the controlling semiconductor chip.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: June 24, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Hideyuki Iwamura, Isao Ochiai
  • Patent number: 8759956
    Abstract: Embodiments provide provides a chip package. The chip package may include a leadframe having a die pad and a plurality of lead fingers; a first chip attached to the die pad, the first chip being bonded to one or more of the lead fingers via a first set of wire bonds; a second chip bonded to one or more of the lead fingers via flip chip; and a heat slug attached to the second chip.
    Type: Grant
    Filed: July 5, 2012
    Date of Patent: June 24, 2014
    Assignee: Infineon Technologies AG
    Inventor: Tyrone Jon Donato Soller
  • Patent number: 8742555
    Abstract: A semiconductor device lead frame having enhanced mold locking features is provided. The lead frame has a flag with bendable edge features along the edge of the flag. Each edge feature is shaped to resist movement against encapsulating mold material in a plane of the edge feature. By bending a portion of the edge feature, improved mold locking of the flag is provided in multiple planes.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: June 3, 2014
    Inventors: Jian Wen, Darrel R. Frear, William G. McDonald
  • Patent number: 8736077
    Abstract: Disclosed herein is a semiconductor package substrate including a base substrate, a mounting member mounted on an upper portion of the base substrate, and an adhesive layer formed between the base substrate and the mounting member, wherein the adhesive layer includes a thermally conductive adhesive and a ductile adhesive formed at the outer circumference of the thermally conductive adhesive.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: May 27, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jong Man Kim, Young Hoon Kwak, Kyu Hwan Oh, Seog Moon Choi, Tae Hoon Kim
  • Patent number: 8716069
    Abstract: A semiconductor device comprises an aluminum alloy lead-frame with a passivation layer covering an exposed portion of the aluminum alloy lead-frame. Since aluminum alloy is a low-cost material, and its hardness and flexibility are suitable for deformation process, such as punching, bending, molding and the like, aluminum alloy lead frame is suitable for mass production; furthermore, since its weight is much lower than copper or iron-nickel material, aluminum alloy lead frame is very convenient for the production of semiconductor devices.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: May 6, 2014
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Yan Xun Xue, Yueh-Se Ho, Yongping Ding
  • Patent number: 8698289
    Abstract: The semiconductor device is high in both heat dissipating property and connection reliability in mounting. The semiconductor device includes a semiconductor chip, a resin sealing member for sealing the semiconductor chip, a first conductive member connected to a first electrode formed on a first main surface of the semiconductor chip, and a second conductive member connected to a second electrode formed on a second main surface opposite to the first main surface of the semiconductor chip, the first conductive member being exposed from a first main surface of the resin sealing member, and the second conductive member being exposed from a second main surface opposite to the first main surface of the resin sealing member and also from side faces of the resin sealing member.
    Type: Grant
    Filed: August 24, 2011
    Date of Patent: April 15, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Yukihiro Satou, Takeshi Otani, Hiroyuki Takahashi, Toshiyuki Hata, Ichio Shimizu
  • Patent number: 8692387
    Abstract: A semiconductor package and method of assembling a semiconductor package includes encapsulating a first pre-packaged semiconductor die stacked on top of and interconnected with a second semiconductor die. The first packaged semiconductor die is positioned and fixed relative to a lead frame with a temporary carrier such as tape. The second semiconductor die is attached and interconnected directly to the first packaged semiconductor die and lead frame. The interconnected first packaged die and second semiconductor die, and lead frame are encapsulated to form the semiconductor package. Different types of semiconductor packages such as quad flat no-lead (QFN) and ball grid array (BGA) may be formed, which provide increased input/output (I/O) count and functionality.
    Type: Grant
    Filed: June 6, 2012
    Date of Patent: April 8, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Shunan Qiu, Guoliang Gong, Xuesong Xu, Xingshou Pang, Beiyue Yan, Yinghui Li
  • Patent number: 8686547
    Abstract: Embodiments of the present disclosure describe a packaged semiconductor device that reduces stress on a semiconductor device caused by thermal expansion of the insulating material used in the packaged semiconductor device. In one embodiment, an inactive semiconductor device is coupled to the top of active semiconductor device. Both the inactive and active devices are encapsulated by the insulating material. The configuration of the inactive device is selected based on its ability to absorb the expansion of the insulating material at operating temperature.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: April 1, 2014
    Assignee: Marvell International Ltd.
    Inventors: Huahung Kao, Thomas Ngo, Shiann-Ming Liou
  • Patent number: 8686550
    Abstract: A pressure sensor package is provided that reduces the occurrence of micro gaps between molding material and metal contacts that can store high-pressure air. The present invention provides this capability by reducing or eliminating interfaces between package molding material and metal contacts. In one embodiment, a control die is electrically coupled to a lead frame and then encapsulated in molding material, using a technique that forms a cavity over a portion of the control die. The cavity exposes contacts on the free surface of the control die that can be electrically coupled to a pressure sensor device using, for example, wire bonding techniques. In another embodiment, a region of a substrate can be encapsulated in molding material, using a technique that forms a cavity over a sub-portion of the substrate that includes contacts. A pressure sensor device can be electrically coupled to the exposed contacts.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: April 1, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: William G. McDonald, Alexander M. Arayata, Philip H. Bowles, Stephen R. Hooper
  • Patent number: 8680659
    Abstract: A semiconductor device of the present invention includes a resin package, a semiconductor chip sealed in the resin package, and having first and second pads on a front surface, a lead integrated island sealed in the resin package, to one surface of which a back surface of the semiconductor chip is bonded, and the other surface of an opposite side to the one surface of which is partially exposed from a bottom surface of the resin package as a first pad connecting terminal for electrical connection between the first pad and outside and a back connecting terminal for electrical connection between the back surface of the semiconductor chip and outside separately from each other, and a lead formed separately from the lead integrated island, sealed in the resin package, one surface of which is connected with the second pad by a wire, and the other surface of an opposite side to the one surface of which is exposed from a bottom surface of the resin package as a second pad connecting terminal for electrical connectio
    Type: Grant
    Filed: May 13, 2010
    Date of Patent: March 25, 2014
    Assignee: Rohm Co., Ltd.
    Inventors: Akihiro Koga, Toichi Nagahara
  • Patent number: 8674487
    Abstract: A semiconductor package with a die pad, a die disposed on the die pad, and a first lead disposed about the die pad. The first lead includes a contact element, an extension element extending substantially in the direction of the die pad, and a concave surface disposed between the contact element and the extension element. A second lead having a concave surface is also disposed about the die pad. The first lead concave surface is opposite in direction to the second lead concave surface.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: March 18, 2014
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Lin-Wang Yu, Ping-Cheng Hu, Che-Chin Chang, Yu-Fang Tsai
  • Patent number: 8674486
    Abstract: Systems and methods pertaining to a digital signal isolator device are described. In one embodiment, the device includes an isolation barrier and two metal support paddles. The isolation barrier contains an organic and/or a semi-organic insulating material with at least one capacitor embedded inside. One of the two metal support paddles is located below a first portion of a bottom surface of the isolation barrier to provide support to the isolation barrier, while the other metal support paddle is located below a second portion of a bottom surface of the isolation barrier to provide support to the isolation barrier.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: March 18, 2014
    Assignee: Samsung Electro-Mechanics
    Inventors: Geoffrey T Haigh, Matthew Kuhn, Patrick Melet, Romain Pelard, Jae Joon Chang, Youngsik Hur
  • Publication number: 20140070380
    Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for a bridge interconnect assembly that can be embedded in a package assembly. In one embodiment, a package assembly includes a package substrate configured to route electrical signals between a first die and a second die and a bridge embedded in the package substrate and configured to route the electrical signals between the first die and the second die, the bridge including a bridge substrate, one or more through-hole vias (THVs) formed through the bridge substrate, and one or more traces disposed on a surface of the bridge substrate to route the electrical signals between the first die and the second die. Routing features including traces and a ground plane of the bridge interconnect assembly may be separated by an air gap. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 11, 2012
    Publication date: March 13, 2014
    Inventors: Chia-Pin Chiu, Zhiguo Qian, Mathew J. Manusharow
  • Patent number: 8653636
    Abstract: A contactless communication medium which can prevent invasion of static electricity and has an outer surface which can satisfy requirements on the flatness thereof. The contactless communication medium has a sealing member including an insulating layer and a conductive layer provided in a stacked manner and having a shape covering an IC module is located such that the insulating layer is on the IC module side. Owing to this, static electricity coming from outside is diffused by the conductive layer and blocked by the insulating layer. Thus, adverse influence of the static electricity on the IC module is prevented. The contactless communication medium can also satisfy the requirements on the flatness of an outer surface thereof.
    Type: Grant
    Filed: August 25, 2010
    Date of Patent: February 18, 2014
    Assignee: Toppan Printing Co., Ltd.
    Inventors: Junsuke Tanaka, Yoshiyuki Mizuguchi
  • Patent number: 8648449
    Abstract: According to example configurations herein, a leadframe includes a connection interface. The connection interface can be configured for attaching an electrical circuit to the leadframe. The leadframe also can include a conductive path. The conductive path in the leadframe provides an electrical connection between a first electrical node of the electrical circuit and a second electrical node of the electrical circuit. Prior to making the connection between the electrical circuit and the leadframe, the first electrical node and the second electrical node can be electrically isolated from each other. Subsequent to making connection of the electrical circuit with the leadframe, the conductive path of the leadframe electrically connects the first electrical node and the second electrical node together. Accordingly, the leadframe provides connectivity between nodes of an electrical circuit in lieu of having to provide such connectivity at, for example, a metal interconnect layer of an integrated circuit device.
    Type: Grant
    Filed: July 20, 2009
    Date of Patent: February 11, 2014
    Assignee: International Rectifier Corporation
    Inventors: Gary D. Polhemus, Robert T. Carroll, Donald J. Desbiens
  • Publication number: 20140027892
    Abstract: A system and method for manufacturing an electric device package are disclosed. An embodiment comprises comprising a first carrier contact, a first electric component, the first electric component having a first top surface and a first bottom surface, the first electric component comprising a first component contact disposed on the first top surface, the first bottom surface being connected to the carrier and an connection element comprising a second electric component and an interconnect element, the connection element having a connection element top surface and a connection element bottom surface, wherein the connection element bottom surface comprises a first connection element contact and a second connection element contact, and wherein the first connection element contact is connected to the first component contact and the second connection element contact is connected to the first carrier contact. The packaged device further comprises an encapsulant encapsulating the first electric component.
    Type: Application
    Filed: July 30, 2012
    Publication date: January 30, 2014
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Joachim Mahler, Edward Fuergut, Khalil Hosseini, Georg Meyer-Berg
  • Patent number: 8637966
    Abstract: In a QFP with a chip-stacked structure in which a lower surface of a die pad is exposed from a lower surface of a sealing member, a semiconductor chip having a BCB film, which is made of a polymeric material containing at least benzocyclobutene in its backbone as an organic monomer and formed on its surface, is mounted at a position (second stage) that is away from the die pad. As a result, even when moisture invades through the interface between the die pad and the sealing member, it is possible to prolong the time required for the moisture to reach the semiconductor chip, and subsequently to make moisture absorption defect less likely to occur.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: January 28, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Koichi Kanemoto
  • Publication number: 20140001582
    Abstract: A semiconductor device package having a cavity formed using film-assisted molding techniques is provided. Through the use of such techniques the cavity can be formed in specific locations in the molded package, such as on top of a device die mounted on the package substrate or a lead frame. In order to overcome cavity wall angular limitations introduced by conformability issues associated with film-assisted molding, a gel reservoir feature is formed so that gel used to protect components in the cavity does not come in contact with a lid covering the cavity or the junction between the lid and the package attachment region. The gel reservoir is used in conjunction with a formed level setting feature that controls the height of gel in the cavity. Benefits include decreased volume of the cavity, thereby decreasing an amount of gel-fill needed and thus reducing production cost of the package.
    Type: Application
    Filed: June 28, 2012
    Publication date: January 2, 2014
    Inventors: Shun Meen Kuo, Li Li
  • Publication number: 20140001612
    Abstract: System and method for providing a multiple die interposer structure. An embodiment comprises a plurality of interposer studs in a molded interposer, with a redirection layer on each side of the interposer. Additionally, the interposer studs may be initially attached to a conductive mounting plate by soldering or wirebond welding prior to molding the interposer, with the mounting plate etched to form one of the redirection layers. Integrated circuit dies may be attached to the redirection layers on each side of the interposer, and interlevel connection structures used to mount and electrically connect a top package having a third integrated circuit to the interposer assembly.
    Type: Application
    Filed: June 29, 2012
    Publication date: January 2, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, Mirng-Ji Lii, Hao-Yi Tsai, Jui-Pin Hung, Chien-Hsun Lee, Kai-Chiang Wu
  • Patent number: 8604627
    Abstract: The present invention aims at providing a semiconductor device capable of reliably preventing a wire bonded to an island from being disconnected due to a thermal shock, a temperature cycle and the like in mounting and capable of preventing remarkable increase in the process time. In the semiconductor device according to the present invention, a semiconductor chip is die-bonded to the surface of an island, one end of a first wire is wire-bonded to an electrode formed on the surface of the semiconductor chip to form a first bonding section and the other end of the first wire is wire-bonded to the island to form a second bonding section, while the semiconductor device is resin-sealed. A double bonding section formed by wire-bonding a second wire is provided on the second bonding section of the first wire wire-bonded onto the island.
    Type: Grant
    Filed: April 14, 2006
    Date of Patent: December 10, 2013
    Assignee: Rohm Co., Ltd.
    Inventors: Hideki Hiromoto, Sadamasa Fujii, Tsunemori Yamaguchi
  • Patent number: 8598694
    Abstract: Various embodiments provide a chip-carrier including, a chip-carrier surface configured to carry a first chip from a first chip bottom side, wherein a first chip top side of the first chip is configured above the chip-carrier surface; and at least one cavity extending into the chip-carrier from the chip-carrier surface; wherein the at least one cavity is configured to carry a second chip from a second chip bottom side, wherein a second chip top side of the second chip is substantially level with the first chip top side. The second chip is electrically insulated from the chip-carrier by an electrical insulation material inside the cavity.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: December 3, 2013
    Assignee: Infineon Technologies AG
    Inventors: Khalil Hosseini, Joachim Mahler, Anton Prueckl
  • Patent number: 8586422
    Abstract: A semiconductor device is made by providing a semiconductor die having an optically active area, providing a leadframe or pre-molded laminated substrate having a plurality of contact pads and a light transmitting material disposed between the contact pads, attaching the semiconductor die to the leadframe so that the optically active area is aligned with the light transmitting material to provide a light transmission path to the optically active area, and disposing an underfill material between the semiconductor die and leadframe. The light transmitting material includes an elevated area to prevent the underfill material from blocking the light transmission path. The elevated area includes a dam surrounding the light transmission path, an adhesive ring, or the light transmission path itself can be the elevated area. An adhesive ring can be disposed on the dam. A filler material can be disposed between the light transmitting material and contact pads.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: November 19, 2013
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Zigmund R Camacho, Henry D Bathan, Lionel Chien Hui Tay, Amel Senosa Trasporto
  • Patent number: 8587101
    Abstract: Some exemplary embodiments of a multi-chip module (MCM) power quad flat no-lead (PQFN) semiconductor package utilizing a leadframe for electrical interconnections have been disclosed. One exemplary embodiment comprises a PQFN semiconductor package comprising a leadframe, a driver integrated circuit (IC) coupled to the leadframe, a plurality of vertical conduction power devices coupled to the leadframe, and a plurality of wirebonds providing electrical interconnects, including at least one wirebond from a top surface electrode of one of the plurality of vertical conduction power devices to a portion of the leadframe, wherein the portion of the leadframe is electrically connected to a bottom surface electrode of another of the plurality of vertical conduction power devices. In this manner, efficient multi-chip circuit interconnections can be provided in a PQFN package using low cost leadframes.
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: November 19, 2013
    Assignee: International Rectifier Corporation
    Inventors: Dean Fernando, Roel Barbosa
  • Patent number: 8575738
    Abstract: In an embodiment, a semiconductor memory card includes a lead frame including external connection terminals, a lead portion, a chip component mounting portion and a semiconductor chip mounting portion, a chip component mounted on the chip component mounting portion, a memory chip disposed on the semiconductor chip mounting portion, and a controller chip. A rewiring layer is formed on a surface of the memory chip. The lead frame is resin-sealed. An electric circuit of the controller chip and the memory chip on the lead frame is formed by the lead portion, the rewiring layer and a metal wire connected to electrode pad of the chips, the lead portion, and the rewiring layer.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: November 5, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuhide Doi, Naohisa Okumura, Taku Nishiyama, Katsuyoshi Watanabe, Takeshi Ikuta
  • Publication number: 20130264693
    Abstract: A lead finger of a lead frame has a number of channels or grooves in a portion of its top surface that provide a locking mechanism for securing a bond wire to the lead finger. The bond wire may be attached to the lead finger by stitch bonding.
    Type: Application
    Filed: April 9, 2012
    Publication date: October 10, 2013
    Applicant: FREESCALE SEMICONDUCTOR, INC
    Inventors: Wai Keong WONG, Kok Leong CHAN, Wei Kee CHAN
  • Publication number: 20130256852
    Abstract: A method of making a stacked semiconductor package having at least a leadframe, a first die mounted above and soldered to the lead frame and a first clip mounted above and soldered to the first die. The method includes positioning the leadframe, first die and first clip in a vertically stacked relationship and nonsolderingly locking the first clip in laterally nondisplaceble relationship with the leadframe. A stacked semiconductor package and an intermediate product produced in making a stacked semiconductor package are also disclosed.
    Type: Application
    Filed: March 27, 2012
    Publication date: October 3, 2013
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Michael Todd Wyant, Patricia Sabran Conde, Vikas Gupta, Rajiv Dunne, Emerson Mamaril Enipin
  • Publication number: 20130249069
    Abstract: A circuit package is provided, the circuit package including: an electronic circuit; a metal block next to the electronic circuit; encapsulation material between the electronic circuit and the metal block; a first metal layer structure electrically contacted to at least one first contact on a first side of the electronic circuit; a second metal layer structure electrically contacted to at least one second contact on a second side of the electronic circuit, wherein the second side is opposite to the first side; wherein the metal block is electrically contacted to the first metal layer structure and to the second metal layer structure by means of an electrically conductive medium; and wherein the electrically conductive medium includes a material different from the material of the first and second metal layer structures or has a material structure different from the material of the first and second metal layer structures.
    Type: Application
    Filed: March 21, 2012
    Publication date: September 26, 2013
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Khalil Hosseini, Joachim Mahler, Edward Fuergut
  • Patent number: 8535987
    Abstract: A manufacturing method of a substrate for a semiconductor element, wherein a first step includes: forming a first and second photosensitive resin layer on a first and second surface of a metal plate, respectively; forming a first and second resist pattern on the first and second surface, for forming a connection post and a wiring pattern, respectively. A second step includes: forming the connection post and wiring pattern; filling in a premold liquid resin to the first surface which was etched; forming a premold resin layer by hardening the premold liquid resin; performing a grinding operation on the first surface, and exposing an upper bottom surface of the connection post from the premold resin layer. A groove structure is formed by the first and second steps, wherein a depth of the groove is up to an intermediate part in a thickness direction of the metal plate.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: September 17, 2013
    Assignee: Toppan Printing Co., Ltd.
    Inventors: Susumu Maniwa, Takehito Tsukamoto, Junko Toda