Abstract: The invention relates to a pressure sensor including: a sensitive element including a mounting substrate, said mounting substrate including a top surface and a bottom surface, the sensitive element also including a deformable diaphragm that is connected to the top surface of the mounting substrate; a housing, in which the sensitive element is placed, said housing including a base; an intermediate structure placed between the base of the housing and the mounting substrate, said intermediate structure including a base, the base including a top surface and a bottom surface that is connected to the base of the housing, said intermediate structure being configured such as to keep the mounting substrate at a predetermined distance from the top surface of the intermediate structure; and an adhesive layer extending onto the top surface of the intermediate structure.

Abstract: A display device includes a printed circuit board (PCB), two sides of the PCB extending in first and second directions, respectively, the first and second directions crossing each other, pad group areas being defined in the PCB and arranged along the first direction; and a display panel electrically connected to the PCB through the pad group areas, the PCB including: first pads in each of the pad group areas and arranged along a third direction crossing the first and second directions; and second pads in each of the pad group areas, arranged along the third direction, and spaced apart from the first pads, wherein a portion of the first pads is in the first pad area, an other portion of the first pads and a portion of the second pads are in the second pad area, and an other portion of the second pad is in the third pad area.

Abstract: A method for manufacturing a printed wiring board with conductive posts includes forming on a first foil provided on carrier a first conductive layer including mounting pattern to connect electronic component via conductive posts, forming on the first foil a laminate including an insulating layer and a second foil to form the laminate on the first conductive layer, removing the carrier, forming a metal film on the laminate and first film, forming resist on the metal film to have pattern exposing portion of the metal film corresponding to the mounting pattern and portion of the second foil for a second conductive layer, forming an electroplating layer on the portion of the metal film not covered by the resist, removing the resist, and applying etching to remove the first and second foils below the metal film exposed by the removing the resist and to form the posts on the mounting pattern.

Abstract: A stretchable organic light-emitting display device includes a stretchable base plate including a stretchable substrate, first metal electrodes that are separated from each other and located in a plurality of rows on a the stretchable substrate, and first power wirings electrically coupling respective ones of the metal electrodes of each row, a light-emitting layer on the stretchable base plate, second metal electrodes located in a plurality of rows on the light-emitting layer and corresponding to the first metal electrodes, second power wirings for electrically coupling respective ones of the second metal electrodes of each row, and an encapsulation substrate covering the second power wiring.

Abstract: Provided are a chip on film (COF) package and semiconductor having the same. The COF package can include a flexible film having first and second surfaces opposite to and facing each other and including a conductive via penetrating from the first surface to the second surface, first and second conductive patterns respectively is on the first surface and the second surface and electrically connected to each other through the conductive via, an integrated circuit (IC) chip is on the first surface and electrically connected to the first conductive pattern, a test pad overlaps the conductive via and is electrically connected to at least one of the first conductive pattern and the second conductive pattern, and an external connection pattern is on the second surface spaced apart from the conductive via and electrically connected to the second conductive pattern.

Abstract: A semiconductor device includes a wiring board that has a conductive pattern formed on at least one principal surface, and an IC chip that is mounted on the wiring board. The IC chip includes a plurality of electrodes to make conductor connection with the wiring board. The conductive pattern includes a lead line pattern and a heat dissipation pattern. The lead line pattern is connected with at least one of the plurality of electrodes through a conductor. The heat dissipation pattern is physically spaced from the IC chip and the lead line pattern and has a larger surface area than the lead line pattern. Further, the lead line pattern and the heat dissipation pattern are placed opposite to each other with a gap therebetween, and their opposite parts respectively have interdigitated shapes and are arranged with the respective interdigitated shapes engaging with each other with the gap therebetween.

Abstract: A light-emitting surface element includes a connection device, a light-generating element having at least two electrical connections electrically conductively connected to assigned connection lines on the connection device, and at least one planar light-guiding element formed by injection-molding in a manner at least partly embedding an arrangement composed of connection device and light-generating element in the planar light-guiding element.

Abstract: A lead carrier provides support for an integrated circuit chip and associated leads during manufacture as packages containing such chips. The lead carrier includes a temporary support member with multiple package sites. Each package site includes a die attach pad surrounded by a plurality of terminal pads. The pads are formed of a sintered electrically conductive material. A chip is mounted upon the die attach pad and wire bonds extend from the chip to the terminal pads. The pads, chip and wire bonds are all encapsulated within a mold compound. The temporary support member can be peeled away and then the individual package sites can be isolated from each other to provide completed packages including multiple surface mount joints for mounting within an electronics system board. Edges of the pads are contoured to cause the pads to engage with the mold compound to securely hold the pads within the package.

Abstract: A liquid crystal display device (100) includes a glass substrate (110) having an LSI chip (130) and an FPC board (140) mounted thereon. A component ACF (150a) made of a single sheet is used to further mount discrete electronic components such as stabilizing capacitors (150) on the glass substrate (110). The component ACF (150a) has a size that covers not only a region where the discrete electronic components are to be mounted, but also the top surfaces of the LSI chip (130) and the FPC board (140) which are mounted first. By thus using the large component ACF (150a), a positional constraint upon adhering the component ACF (150a) to the glass substrate (110) is eliminated, reducing the area of a region where the discrete electronic components are mounted. By this, a board module miniaturized by reducing the area of a region where discrete electronic components are mounted is provided.

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, forming dielectric material surrounding the die, forming buildup layers in the dielectric material to form a coreless bumpless buildup package structure, and patterning the carrier material to form microchannel structures on the package structure.

Abstract: A semiconductor device includes a wiring board that has a conductive pattern formed on at least one principal surface, and an IC chip that is mounted on the wiring board. The IC chip includes a plurality of electrodes to make conductor connection with the wiring board. The conductive pattern includes a lead line pattern and a heat dissipation pattern. The lead line pattern is connected with at least one of the plurality of electrodes through a conductor. The heat dissipation pattern is physically spaced from the IC chip and the lead line pattern and has a larger surface area than the lead line pattern. Further, the lead line pattern and the heat dissipation pattern are placed opposite to each other with a gap therebetween, and their opposite parts respectively have interdigitated shapes and are arranged with the respective interdigitated shapes engaging with each other with the gap therebetween.

Abstract: A tape wiring substrate may have dispersion wiring patterns. The dispersion wiring patterns may be provided between input/output wiring pattern groups to compensate for the intervals therebetween. Connecting wiring patterns may be configured to connect the dispersion wiring patterns to a first end of the adjacent input/output wiring pattern.

Abstract: Provided is a semiconductor package including: a semiconductor chip mounted on a die pad; at least one lead connected electrically to the semiconductor chip; and a flexible film substrate including a metal wiring, which electrically connects the semiconductor chip and the at least one lead, wherein the semiconductor chip is electrically connected to the film substrate through a first connection member which contacts the semiconductor chip and the metal wiring; and the film substrate is electrically connected to the at least one lead through a second connection member which contacts the metal wiring and the at least one lead.

Abstract: A component includes a first semiconductor chip attached to a first carrier and second semiconductor chip attached to a second carrier. The first carrier has a first extension, which forms a first external contact element. The second carrier has a second extension, which forms a second external contact element. The first and the second carriers are arranged in such a way that the first and the second extension point in different directions.

Abstract: A COF package having a tape substrate including external input terminals and external output terminals provided in a chip non-mounting area, input wirings connected to the external input terminals respectively, output wirings connected to the external output terminals respectively, internal input wirings which are provided from the chip non-mounting area to a chip mounting area and provided between the input wirings and which are connected to the external input terminals, respectively, and a dummy wiring provided from the chip non-mounting area to the chip mounting area and provided between the internal input wirings; and a semiconductor chip including input electrodes connected to the input wirings respectively, output electrodes connected to the output wirings respectively, internal input electrodes connected to the internal input wirings respectively, and a dummy electrode provided spaced from each input electrode along one side of the chip surface, and connected to the dummy wiring.

Abstract: A light emitting diode lamp is disclosed that includes a resin package that defines a recess in the shape of a solid polygon or another three-dimensional solid. The recess includes a floor, two side walls along the respective longer sides of the floor, and two end walls along the respective shorter sides of the floor. The two side walls define an angle therebetween greater than 3°, and the two end walls define an angle therebetween greater than 40°. A light emitting diode chip is positioned on the rectangular floor of the package.

Abstract: An assembly for producing partially packaged semiconductor devices is provided. In one embodiment, the assembly includes a magnetic plate; a flexible substrate disposed adjacent the magnetic plate and having two surfaces; a nonstick coating disposed on one surface of the flexible substrate thereby exposing a nonstick surface; and a tape layer having two surfaces. The tape layer is adhesively attached to the nonstick surface to expose a surface of the tape layer. A frame is disposed on the exposed surface of the tape layer, and a plurality of integrated circuit (IC) die is positioned within the frame and supported by the tape layer. A panel is formed within the frame that at least partially surrounds the plurality of IC die and that contacts the tape layer.

Abstract: Example embodiments provide tape structures including a base layer, a neutralizing layer and an adhesive layer. The base layer may support an object. The neutralizing layer may be arranged on the base layer. The neutralizing layer may be grounded to neutralize charges between the base layer and the object. The adhesive layer may be arranged on the neutralizing layer. The object may be attached to the adhesive layer. Example embodiments also provide methods of manufacturing the tape structures, methods of separating a wafer, and apparatuses for separating a wafer.

Abstract: A tape wiring substrate may have dispersion wiring patterns. The dispersion wiring patterns may be provided between input/output wiring pattern groups to compensate for the intervals therebetween. Connecting wiring patterns may be configured to connect the dispersion wiring patterns to a first end of the adjacent input/output wiring pattern.

Abstract: A device is provided in which a glass panel having beveled edge is flexibly connected to a TAB package. The outer lead portions of the TAB package include an end portion of first width connected to a connection pattern on the glass panel, a terminal portion having a second width greater than the first width, and a transition portion having a width that varies between the first and second widths. When the TAB package is connected the transition portion of the respective outer lead portions are disposed over the beveled edge of the glass panel.

Abstract: A packaged electronic device includes a die, a flexible circuit structure, and a barrier film disposed on the die. The die includes die circuitry and electrical contacts. The flexible circuit structure is bonded directly to the die, and includes electrical conductors encapsulated by structural layers. Each electrical conductor contacts a respective electrical contact. The electronic device is encapsulated by the barrier film and one or more of the structural layers.

Abstract: A chip-on-film package may include a tape wiring substrate, a semiconductor chip mounted on the tape wiring substrate, and a molding compound provided between the semiconductor chip and the tape wiring substrate. The tape wiring substrate may include a film having upper and lower surfaces. Vias may penetrate the film. An upper metal layer may be provided on the upper surface of the film and include input terminal patterns and/or output terminal patterns. The input terminal patterns may include ground terminal patterns and/or power terminal patterns. A lower metal layer may be provided on the lower surface of the film and include a ground layer and/or a power layer. The ground layer and the power layer may cover at least a chip mounting area.

Abstract: A semiconductor component (1) has a semiconductor chip (5) and a semiconductor component carrier (3) with external connection strips (12, 13, 15). The semiconductor chip (5) has a first electrode (6) and a control electrode (7) on its top side (8) and a second electrode (9) on its rear side (10). The semiconductor chip (5) is fixed by its top side (8) in flip-chip arrangement (11) on a first and a second external connection strip (12, 13) for the first electrode (6) and the control electrode (7). The second electrode (9) is electrically connected to at least one third external connection strip (15) via a bonding tape (14).

Abstract: Provided are a tape substrate for a smart card, a method of fabricating the same, and a semiconductor module and a smart card using the tape substrate. The tape substrate includes at least one tape unit. The at least one tape unit includes a chip mounting unit defining a region on which a semiconductor chip is to be mounted, a plurality of pin electrode units arranged around the chip mounting unit and separated from one another, a border unit encircling the chip mounting unit and the pin electrode units, and a cutting unit disposed between the chip mounting unit and the border unit and between the pin electrode units and the border unit. The cutting unit includes a plurality of connection lines connecting the chip mounting unit and the pin electrode units to the border unit.

Abstract: A device is disclosed which includes a flexible material including at least one conductive wiring trace, a first die including at least an integrated circuit, the first die being positioned above a portion of the flexible material, and an encapsulant material that covers the first die and at least a portion of the flexible material. A method is disclosed which includes positioning a first die above a portion of a flexible material, the first die including an integrated circuit and the flexible material including at least one conductive wiring trace, and forming an encapsulant material that covers the first die and at least a portion of the flexible material, wherein at least a portion of the flexible material extends beyond the encapsulant material.

Abstract: A semiconductor chip package including a film substrate and a semiconductor chip loaded on the semiconductor chip is provided. The semiconductor chip includes a plurality of input pads and a plurality of output pads. A power supply input pad of the input pads is formed at a different edge from an edge of the semiconductor chip where other input pads are formed. The film substrate includes input lines and output lines. The input lines of the film substrate are connected to the corresponding input pads of the semiconductor chip, and the output lines thereof are connected to the corresponding output pads of the semiconductor chip.

Abstract: A method for manufacturing an electronic part, including: cutting a wiring substrate, which contains a base substrate, a wiring pattern provided on a first surface of the base substrate, and a reinforcing member provided on a second surface of the base substrate, along a line intersecting with an outer circumference of the reinforcing member; wherein a wire, out of a plurality of wires composing the wiring pattern, arranged closest to an intersecting point of the outer circumference of the reinforcing member and the line has a widest width.

Abstract: A semiconductor device (1700), which comprises a workpiece (1201) with an outline (1711) and a plurality of contact pads (1205) and further an external part (1701) with a plurality of terminal pads (1702). This part is spaced from the workpiece, and the terminal pads are aligned with the workpiece contact pads, respectively. A reflow element (1203) interconnects each of the contact pads with its respective terminal pad. Thermoplastic material (1204) fills the space between the workpiece and the part; this material adheres to the workpiece, the part and the reflow elements. Further, the material has an outline (1711) substantially in line with the outline of the workpiece, and fills the space (1707) substantially without voids. Due to the thermoplastic character of the filling material, the finished device can be reworked, when the temperature range for reflowing the reflow elements is reached.

Abstract: A punch type substrate strip includes a plurality of substrate units, a plurality of slots and at least one plating-trace collecting hole. The slots are formed around the substrate units. The plating-trace collecting hole is located outside the substrate units. The substrate strip is provided with a plurality of connecting pads, a plurality of first plating traces and at least one second plating trace. The connecting pads are disposed in each substrate unit, and the first plating traces and the second plating trace are electrically connected to the connecting pads. The first plating traces have a plurality of first broken ends located in the slots. The second plating trace is extended across a region located between the slots, and has a second broken end located in the plating-trace collecting hole. Accordingly, more extensive space for plating traces can be provided.

Abstract: A device is provided in which a glass panel having beveled edge is flexibly connected to a TAB package. The outer lead portions of the TAB package include an end portion of first width connected to a connection pattern on the glass panel, a terminal portion having a second width greater than the first width, and a transition portion having a width that varies between the first and second widths. When the TAB package is connected the transition portion of the respective outer lead portions are disposed over the beveled edge of the glass panel.

Abstract: Provided is a device, an assembly comprising said device, a sub-assembly and an element suitable for use in the assembly. The device comprises a body of an electrically insulating material having a first side and an opposite second side, the body being provided with conductors according to a desired pattern, said conductors being anchored in the body. The body is provided with a through-hole extending from the first side to the second side of the body and having a surfacial area which is smaller on the first side than on the second side. Such a device can very suitably be used in an assembly comprising an element which is a sensor, preferably a chemical sensor, and particularly a biosensor.

Abstract: A leadless semiconductor package mainly includes a plurality of inner leads, a chip pad, a semiconductor chip and a molding compound. A non-conductive ink is filled between every two of the inner leads, and couples the inner leads to the chip pad so as to be in replacement of the conventional tie bars. The semiconductor chip is disposed on the chip pad and electrically connected to the inner leads. Moreover, the molding compound is formed on the inner leads and the non-conductive ink for encapsulating the semiconductor chip. The non-conductive ink prevents the exposed bottom surfaces of the inner leads from contamination by the molding compound without attaching an external tape during molding. Also the inner leads can be in a multi-row arrangement and the chip pad can be disposed in an optional location.

Abstract: A wired circuit board is provided having a high-reliability conductive pattern formed thereon and mounting an electronic component thereon with high accuracy, and a method is provided for manufacturing the wired circuit board and mounting the electronic component thereon. An insulating layer including a mounting portion is formed on a metal supporting layer having a specular gloss of 150 to 500% at an incidence angle of 45°. A conductive pattern is formed on the insulating layer. By a reflection-type optical sensor, a defective shape of the conductive pattern is inspected. Then, an opening is formed by etching the portion of the metal supporting layer which is overlapping the mounting portion such that the mounting portion of the insulating layer exposed by etching has a haze value of 20 to 50%, whereby a TAB tape carrier is obtained.

Abstract: A method of fabricating a memory card. The method comprises the initial step of providing a leadframe which has a dambar and a plurality of contacts, each of the contacts being attached to the dambar by at least one tie bar. A layer of tape is applied to the leadframe such that the tape the bottom contact surfaces of the contacts, at least portions of the bottom dambar surface of the dambar. Thereafter, the tie bars are removed from the leadframe. At least one semiconductor die is electrically connected to the leadframe, with a body thereafter being formed on the leadframe such that the bottom contact surfaces are exposed in an exterior surface thereof.

Abstract: A magnetic sensor is constituted using magnetic sensor chips mounted on stages supported by interconnecting members and a frame having leads in a lead frame. Herein, the stages are inclined upon plastic deformation of the interconnecting members. When the frame is held in a metal mold and the stages are pressed, the interconnecting members are elastically deformed, so that the magnetic sensor chips are bonded onto the stages placed substantially in the same plane and are then wired with the leads. Thereafter, the stages are released from pressure, so that the interconnecting members are restored from the elastically deformed states thereof. When the magnetic sensor chips are combined together to realize three sensing directions, it is possible to accurately measure three-dimensional bearings of magnetism, and the magnetic sensor can be reduced in dimensions and manufactured with a reduced cost therefore.

Abstract: A tape wiring substrate may have dispersion wiring patterns. The dispersion wiring patterns may be provided between input/output wiring pattern groups to compensate for the intervals therebetween. Connecting wiring patterns may be configured to connect the dispersion wiring patterns to a first end of the adjacent input/output wiring pattern.

Abstract: A substrate may receive an integrated circuit and a flex circuit on the same side in the same vertical direction. In addition, in some embodiments, a flex circuit adapter and the integrated circuit may be surface mounted in one operation.

Abstract: The present invention provides a COF package which comprises a tape substrate including a plurality of external input terminals and a plurality of external output terminals provided in a chip non-mounting area, a plurality of input wirings connected to the external input terminals respectively, a plurality of output wirings connected to the external output terminals respectively, a plurality of internal input wirings which are provided from the chip non-mounting area to a chip mounting area and provided between the input wirings and which are connected to the external input terminals, respectively, and a dummy wiring provided from the chip non-mounting area to the chip mounting area and provided between the internal input wirings; and a semiconductor chip including a plurality of input electrodes connected to the input wirings respectively, a plurality of output electrodes connected to the input wirings respectively, internal input electrodes connected to the internal input wirings respectively, and a dummy e

Abstract: A method for manufacturing of flexible printed circuit boards is provided. The method includes the steps of: providing a tape substrate having an electrically insulating layer and an electrically conducting layer; forming a wiring pattern at the electrically conducting layer; attaching a back film on a surface of the tape substrate; and cutting the tape substrate to get a number of flexible printed circuit boards attached on the back film.

Abstract: An adhesive film for semiconductor use of the present invention is used in a method in which, after the adhesive film for semiconductor use is laminated to one side of a metal sheet, the metal sheet is processed to give a wiring circuit, a semiconductor die is mounted and molded, and the adhesive film is then peeled off. The adhesive film includes a resin layer A formed on one side or both sides of a support film, the 90 degree peel strength between the resin layer A and the metal sheet prior to the processing of the metal sheet laminated with the adhesive film for semiconductor use to give the wiring circuit is 20 N/m or greater at 25° C., and the 90 degree peel strengths, after molding with a molding compound the wiring circuit laminated with the adhesive film for semiconductor use, between the resin layer A and the wiring circuit and between the resin layer A and the molding compound are both 1000 N/m or less at at least one point in the temperature range of 0° C. to 250° C.

Abstract: An arrangement for connecting the terminal contacts of an optoelectronic component to electrical contacts of a printed circuit board using a flexible conductor arrangement. The flexible conductor arrangement has a planar form and includes a plurality of interconnects that are arranged to provide an electrical connection between the terminal contacts of the optoelectronic component and the electrical contacts of the printed circuit board. The flexible conductor arrangement is bent in such a way that, starting from the printed circuit board, it is led around the optoelectronic component and contacts the latter on a side facing away from the printed circuit board.

Abstract: A semiconductor device includes: an insulating tape having a device hole and a plurality of holes; a plurality of leads formed on one surface of the tape and extending at one end into the device hole and at the other end into the holes; a semiconductor chip having a plurality of electrodes on a main surface thereof, being connected with the leads extending into the device hole; an encapsulant formed of an insulating resin, the leads and a predetermined portion of the tape; bump electrodes provided on one surface of the leads; slits provided in the tape between the encapsulant and the bump electrodes and extending along a column of the bump electrodes; and a warp prevention reinforcement made of an insulating film and formed over the tape; wherein the semiconductor chip and the bump electrodes are connected to one and the same surface side of the leads.

Abstract: The present invention stacks packaged integrated circuits into modules that conserve PWB or other board surface area. The invention provides techniques and structures for aggregating chip scale-packaged integrated circuits (CSPs) or leaded packages with other CSPs or with monolithic or stacked leaded packages into modules that conserve PWB or other board surface area. The present invention can be used to advantage with packages of a variety of sizes and configurations ranging from larger packaged base elements having many dozens of contacts to smaller packages such as, for example, die-sized packages such as DSBGA. In a preferred embodiment devised in accordance with the present invention, a base element CSP and a support element CSP are aggregated through a flex circuit having at least two conductive layers that are patterned to selectively connect the two CSP elements.

Abstract: A method for manufacturing a semiconductor device is provided including: providing a reinforcing member on one surface of a wiring substrate that has a first region where a semiconductor chip is mounted and a second region around the first region, and has terminals extending from the first region to the second region formed on another surface thereof in a manner that the reinforcing member overlaps the terminals and a part thereof protrudes from the first region to the second region; cutting the terminals along a boundary between the first region and the second region; and continuously cutting the reinforcing member from an inboard side thereof to an outboard side along the boundary between the first region and the second region.

Abstract: A semiconductor package including a flexible tape having a mounting portion and an extended portion, a plurality of arrayed connection electrodes provided on the mounting portion of the flexible tape, and a semiconductor chip mounted on the mounting portion of the flexible tape. The semiconductor package further includes a high-speed signal electrode formed at the front end of the extended portion of the flexible tape, and a transmission line provided on the flexible tape for connecting the semiconductor chip and the high-speed signal electrode. A stiffener is mounted on the mounting portion of the flexible tape.

Abstract: A semiconductor device includes at least one semiconductor constructing body provided on one side of a base member, and having a semiconductor substrate and a plurality of external connecting electrodes provided on the semiconductor substrate. An insulating layer is provided on the one side of the base member around the semiconductor constructing body. An adhesion increasing film is formed between the insulating layer, and at least one of the semiconductor constructing body and the base member around the semiconductor constructing body, for preventing peeling between the insulating layer and the at least one of the semiconductor constructing body and base member.

Abstract: A chip carrier comprising a laminated layer and an oxidation protection layer is provided. The oxidation protection layer is a non-electrolytic metallic coating or an organic oxidation protection film on the surface of bonding finger pads or other contacts formed by deploying a simple, fast film-coating technique. Therefore, there is no need to plate a Ni/Au layer on the bonding pads or contacts using expensive electroplating equipment for preventing oxidation and there is no need to fabricate plating lines on the chip carrier or reserve space for laying out the plating lines. Thus, the cost for fabricating the chip carrier is reduced, the effective area of the chip carrier is increased and the electrical performance of the chip carrier is improved.

Abstract: Packaging and encapsulation methods include use of a tape substrate with a mold gate that includes an aperture and a support element that extends over at least a portion of the aperture. The tape substrate may be part of a strip. A semiconductor device is secured and electrically connected to the tape substrate. The resulting assembly is placed into a cavity of a mold, and encapsulant is introduced into the cavity through the mold gate of the tape substrate. Once the encapsulant has sufficiently hardened, the package assembly may be removed from the mold, and a sprue of residual encapsulant removed therefrom. If the package assembly is carried by a strip that carries other package assemblies, it may be removed from the strip.

Abstract: A bump-less chip package is provided. The bump-less chip package includes a chip, an interconnection structure and a panel-shaped component. The panel-shaped component has a plurality of electrical terminals on a first surface thereof. The back surface of the chip is disposed on the first surface of the panel-shaped component, and the chip has a plurality of first pads on the active surface thereof away from the panel-shaped component. The interconnection structure is disposed on the first surface of the panel-shaped component and the active surface of the chip. The first pads of the chip may electrically connect with the electrical terminals of the panel-shaped component through the interconnection structure. Furthermore, the interconnection structure has a plurality of second pads on the surface away from the chip.

Abstract: A semiconductor stacking structure has a semiconductor device. A flexible substrate is coupled to a bottom surface of the semiconductor device. The flexible substrate is folded over on at least two sides to form flap portions. The flap portions are coupled to an upper surface of the first semiconductor device and covers only a portion of the upper surface of the semiconductor device.