Abstract: In some examples, a semiconductor package comprises a die pad, a semiconductor die on the die pad, and a mold compound covering the die pad and the semiconductor die. The semiconductor package includes a conductive component including a roughened surface, the roughened surface having a roughness ranging from an arithmetic mean surface height (SA) of 1.4 to 3.2. The mold compound is coupled to the roughened surface. The semiconductor package includes a bond wire coupling the semiconductor die to the roughened surface. The bond wire is directly coupled to the roughened surface without a precious metal positioned therebetween.

Abstract: The present disclosure relates to the technical field of semiconductor packaging, and discloses a semiconductor structure and a method for forming the same. The method includes: providing a chip, the chip having interconnect structures on its surface, the top of the interconnect structures having an exposed fusible portion; providing a substrate, the substrate having conductive structures on its surface; patterning the conductive structures so that edges of the conductive structures have protrusions; combining the chip with the substrate.

Abstract: A package carrier, including a first redistribution structure layer, multiple conductive connecting members, a connection structure layer, at least one stiffener, and a molding compound, is provided. The conductive connecting members are disposed on a first surface of the first redistribution structure layer and are electrically connected to the first redistribution structure layer. The connection structure layer is disposed on a second surface of the first redistribution structure layer and includes a substrate and multiple pads. A top surface and a bottom surface of each pad are respectively exposed to an upper surface and a lower surface of the substrate. The pads are electrically connected to the first redistribution structure layer. The stiffener is disposed on the first surface and is located at least between the conductive connecting members. The molding compound is disposed on the first surface and covers the conductive connecting members and the stiffener.

Abstract: A semiconductor package includes a semiconductor chip, an encapsulation body encapsulating the semiconductor chip, and a metal sheet having a first sheet surface and an opposite second sheet surface. The first sheet surface is exposed at the encapsulation body. The semiconductor chip is arranged at the second sheet surface. The first sheet surface has a pattern having first subdivisions having a first average roughness and second subdivisions having a second average roughness. The first average roughness is greater than the second average roughness.

Abstract: A semiconductor device includes a semiconductor chip with bonding pads, the bonding pads being arranged along one side of an element forming surface of the semiconductor chip, a lead frame including first and second internal leads arranged such that tips thereof correspond to some of the bonding pads of the semiconductor chip, and first and second bonding vires by which the first internal leads and the some of the bonding pads are bonded to each other. The semiconductor device further includes a hanging pin section provided on the element non-forming surface of the semiconductor chip, and a sealing member with which the semiconductor chip is sealed including the hanging pin section and a bonding section between the first and second internal leads and the first and second bonding wires.

Abstract: A method of forming a chip assembly may include forming a plurality of cavities in a carrier; The method may further include arranging a die attach liquid in each of the cavities; arranging a plurality of chips on the die attach liquid, each chip comprising a rear side metallization and a rear side interconnect material disposed over the rear side metallization, wherein the rear side interconnect material faces the carrier; evaporating the die attach liquid; and after the evaporating the die attach liquid, fixing the plurality of chips to the carrier.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a lead-frame having a metal connector mounted thereon and having a peripheral mounting region; forming an insulation cover on the lead-frame and on the metal connector; connecting an integrated circuit die over the insulation cover; forming a top encapsulation on the integrated circuit die with the peripheral mounting region exposed from the top encapsulation; forming a routing layer, having a conductive land, from the lead-frame; and forming a bottom encapsulation partially encapsulating the routing layer and the insulation cover.

Abstract: An integrated circuit packaging system, and a method of manufacture therefor, including: electrical terminals; circuitry protective material around the electrical terminals and formed to have recessed pad volumes; routable circuitry on the top surface of the circuitry protective material; and an integrated circuit die electrically connected to the electrical terminals.

Abstract: A package carrier includes: (a) a dielectric layer defining a plurality of openings; (b) patterned electrically conductive layer, embedded in the dielectric layer and disposed adjacent to a first surface of the dielectric layer; a plurality of electrically conductive posts, disposed in respective ones of the openings, wherein the openings extend between a second surface of the dielectric layer to the patterned electrically conductive layer, the electrically conductive posts a connected to the patterned electrically conductive layer, and an end of each of the electrically conductive posts has a curved profile and is faced away from the patterned electrically conductive layer; and (d) a patterned solder resist layer, disposed adjacent to the first surface of the dielectric layer and exposing portions of the patterned electrically conductive layer corresponding to contact pads. A semiconductor package includes the package carrier, a chip, and an encapsulant covering the chip and the package carrier.

Abstract: A manufacturing method of a lead frame substrate includes: applying a photosensitive resist or a dry film to first and second surfaces of a metal plate; pattern-exposing the photosensitive resist or the dry film, and then developing the first surface and the second surface to form on the first surface a first resist pattern for forming a connection post and to form on the second surface a second resist pattern for forming a wiring pattern; etching the first surface partway down the metal plate to form the connection post; filling the first surface with a pre-molding resin to a thickness with which the etched surface is buried; removing the pre-molding resin uniformly in a thickness direction of the pre-molding resin until a bottom surface of the connection post is exposed; and etching the second surface to form a wiring pattern.

Abstract: A semiconductor device in accordance with an embodiment comprises a semiconductor chip; a die pad having a chip mount surface for mounting the semiconductor chip; first leads electrically connected to the semiconductor chip; a thermosetting resin part for securing end parts of the first leads to the die pad; and a thermoplastic resin part for sealing the semiconductor chip, the die pad, and the thermosetting resin part.

Abstract: An integrated circuit leadframe device supports various chip arrangements. As consistent with various embodiments, a leadframe includes a plurality of banks of conductive integrated circuit chip connectors. Each bank has a plurality of conductive strips respectively having an end portion, the end portions of each of the strips in the bank being substantially parallel to one another and arranged at an oblique angle to end portions of strips in at least one of the other banks. Each of the end portions has a tip extending to an interior portion of the leadframe device and separated from the other tips by a gap.

Abstract: System for flash-free overmolding of LED array substrates. In an aspect, a method is provided for molding encapsulations onto an LED array substrate. The method includes attaching a protective tape onto a substrate surface of the substrate so that openings in the protective tape align with LED devices of the substrate and applying molding material onto a molding surface of a molding tool and to portions of the substrate exposed through the openings in the protective tape. The method also includes pressing the molding surface and the substrate surface together at a selected pressure and a selected temperature so that encapsulations are formed on the portions of the substrate exposed through the openings in the protective tape, separating the molding surface from the substrate surface, and removing the protective tape so that molding material flash is removed from the substrate leaving a clean molded substrate.

Abstract: Terminals (2b, 2c) are divided into two along a common boundary, coatings (10, 11) most suitable for two conductive bonding materials (5, 6) to be used are exposed on the terminals (2b, 2c), the most suitable one of the coatings (10, 11) is selected, and the corresponding conductive bonding material (5, 6) is bonded onto the coating. Thus it is possible to improve the reliability of bonding and easily reduce a bonding resistance while suppressing a decrease in the reliability of a semiconductor element 3.

Abstract: A solid state light sheet and method of fabricating the sheet are disclosed. In one embodiment, bare LED chips have top and bottom electrodes, where the bottom electrode is a large reflective electrode. The bottom electrodes of an array of LEDs (e.g., 500 LEDs) are bonded to an array of electrodes formed on a flexible bottom substrate. Conductive traces are formed on the bottom substrate connected to the electrodes. A transparent top substrate is then formed over the bottom substrate. Various ways to connect the LEDs in series are described along with many embodiments. In one method, the top substrate contains a conductor pattern that connects to LED electrodes and conductors on the bottom substrate.

Abstract: A conductor layer 2 is formed as a circuit pattern on a base insulating layer 1, a terminal 3 is formed thereon, and a supporting column 4 is formed in the vicinity of the terminal on the upper face of the base insulating layer 1. Here, supposing the protrusion height B of the bump from the element to be connected is B, the height of the supporting column is H, the height of the terminal is h, and the layer thickness of the terminal is t, as measured from the upper face of the base insulating layer as the reference surface, the height H of the supporting column is determined to satisfy B<H<h+B wherein t<B, or h<H<h+B wherein t?B. As a result, the supporting column functions as a spacer to suppress compression that causes the solder of the terminal to reach the electrode of the element.

Abstract: A device is disclosed which includes a flexible material including at least one conductive wiring trace, a first die including at least an integrated circuit, the first die being positioned above a portion of the flexible material, and an encapsulant material that covers the first die and at least a portion of the flexible material. A method is disclosed which includes positioning a first die above a portion of a flexible material, the first die including an integrated circuit and the flexible material including at least one conductive wiring trace, and forming an encapsulant material that covers the first die and at least a portion of the flexible material, wherein at least a portion of the flexible material extends beyond the encapsulant material.

Abstract: A conductor layer 2 is formed as a circuit pattern on a base insulating layer 1, a terminal 3 is formed thereon, and a supporting column 4 is formed in the vicinity of the terminal on the upper face of the base insulating layer 1. Here, supposing the protrusion height B of the bump from the element to be connected is B, the height of the supporting column is H, the height of the terminal is h, and the layer thickness of the to terminal is t, as measured from the upper face of the base insulating layer as the reference surface, the height H of the supporting column is determined to satisfy B<H<h+B wherein t<B, or h<H<h+B wherein t?B. As a result, the supporting column functions as a spacer to suppress compression that causes the solder of the terminal to reach the electrode of the element.

Abstract: A tape wiring substrate may have dispersion wiring patterns. The dispersion wiring patterns may be provided between input/output wiring pattern groups to compensate for the intervals therebetween. Connecting wiring patterns may be configured to connect the dispersion wiring patterns to a first end of the adjacent input/output wiring pattern.

Abstract: A package carrier includes: (a) a dielectric layer defining a plurality of openings; (b) patterned electrically conductive layer, embedded in the dielectric layer and disposed adjacent to a first surface of the dielectric layer; a plurality of electrically conductive posts, disposed in respective ones of the openings, wherein the openings extend between a second surface of the dielectric layer to the patterned electrically conductive layer, the electrically conductive posts a connected to the patterned electrically conductive layer, and an end of each of the electrically conductive posts has a curved profile and is faced away from the patterned electrically conductive layer; and (d) a patterned solder resist layer, disposed adjacent to the first surface of the dielectric layer and exposing portions of the patterned electrically conductive layer corresponding to contact pads. A semiconductor package includes the package carrier, a chip, and an encapsulant covering the chip and the package carrier.

Abstract: An integrated circuit package system is provided forming a lead from a padless lead frame, and encapsulating the lead for supporting an integrated circuit die with a first molding compound for encapsulation with a second molding compound.

Abstract: AN LED chip package body provides an LED chip with a pad-installed surface, a plurality of pads disposed on the pad-installed surface and a rear surface formed opposite the pad-installed surface. The LED chip package body further has a light-reflecting coating disposed on the pad-installed surface of the LED chip and a plurality of pad-exposed holes for exposure of the corresponding pads of the LED chip. The LED chip package body further comprises a light-transparent element disposed on the rear surface of the LED chip and a plurality of conductive projecting blocks. Each of the conductive projecting blocks is disposed on the corresponding pad of the LED chip.

Abstract: A lead frame unit, a semiconductor package having a lead frame unit, a stacked semiconductor package having a semiconductor package, and methods of manufacturing the same are provided. The lead frame unit in a stacked semiconductor package may include a die pad supporting a semiconductor chip, an inner lead electrically connected to the semiconductor chip, an outer lead extending from the inner lead, and a heat-resistant insulation member surrounding the connection portion. The outer lead may include a connection portion connected to the inner lead and a junction portion connected to the connection portion and a circuit board. An external signal may be applied to the junction portion. If the lead frame unit is used in the stacked semiconductor package, the outer lead and a dummy outer lead in the stacked semiconductor package may have substantially the same shape.

Abstract: A semiconductor device is disclosed. One embodiment provides a device including a carrier, an electrically insulating layer arranged over the carrier and a first semiconductor chip arranged over the electrically insulating layer, wherein the first semiconductor chip has a first contact element on a first surface and a second contact element on a second surface.

Abstract: A semiconductor device which includes a radiating plate, a wiring patterned layer on the radiating plate via an insulating layer, at least one semiconductor chip mounted on the wiring patterned layer. The semiconductor chip has a surface electrode. The semiconductor device further includes a conductive lead plate electrically connected with the surface electrode of the semiconductor chip, and a resin package of thermoplastic resin having anisotropic linear expansion coefficient varying based upon directions. The resin package covers the wiring patterned layer, the semiconductor chip, the conductive lead plate, and at least a portion of the radiating plate. The conductive lead plate extends in a direction which provides the resin package with the maximum linear expansion coefficient. In the semiconductor device so structured, the warpage of the resin package is reduced both in longitudinal and transverse directions.

Abstract: A semiconductor device in which chips are resin-molded, including: frames having front and back surfaces and die pads; power chips mounted on the surfaces of the die pads; an insulation resin sheet having a first and a second surfaces which are opposed against each other, the resin sheet being disposed such that the back surfaces of the die pads contact the first surface of the resin sheet; and a mold resin applied on the first surface of the resin sheet so as to seal up the power chips. The thermal conductivity of the resin sheet is larger than that of the mold resin.

Abstract: A semiconductor device includes, a metal base plate, a semiconductor element mounted on the base plate, first and second dielectric plates are mounted on the base plate in the vicinity of the semiconductor element. The first and second dielectric plates are composed of such an insulator material as diamond having higher heat conductivity than that of the base plate material.

Abstract: Consistent with an example embodiment, there is an integrated circuit (IC) device in a packaging having electrically insulated connections. The IC device comprises a semiconductor device (100) mounted onto a die attachment area (10); the semiconductor device has a plurality of bonding pads (20a, 25a, 30a, 35a). A lead frame having a plurality of bonding fingers (20b, 25b, 30b, 35b) surrounds the die attachment area. A plurality of mutually isolated connection conductors (25d, 30d, 40, 50) having respective first ends are attached to respective bonding pads on the semiconductor device and the plurality of mutually isolated connection conductors having respective second respective second ends are attached to respective bonding fingers of the lead frame. An insulating material (45) coats at least a portion of the plurality of mutually isolated connection conductors.

Abstract: A semiconductor chip assembly includes a semiconductor chip that includes a conductive pad, a conductive trace that includes a routing line, a metal containment wall and a solder terminal, and a connection joint that electrically connects the routing line and the pad. The metal containment wall includes a cavity, and the solder terminal contacts the metal containment wall in the cavity and is spaced from the routing line.

Abstract: The specification describes a plastic overmolded package for high power devices that has a very low lead count, typically fewer than eight, and in a preferred embodiment, only two. The leads occupy essentially the same linear space as the multiple leads in a conventional package and thus have a wide-blade configuration. To improve mechanical integrity, the leads in the package are provided with retention slots to add back the equivalent of the plastic joints in the spaces that were eliminated due to the wide-blade design. The retention slots extend in the width dimension of the leads.

Abstract: A method of forming a stackable embedded leadframe package includes coupling an electronic component having bond pads to a substrate; coupling on the substrate a leadframe having a plurality of leads, each lead having a lower mounting portion; encapsulating the electronic component and partially encapsulating the leadframe; singulating each lead; forming via apertures through the substrate to expose the bond pads and the lower mounting portions; and filling the via apertures with an electrically conductive material to form vias electrically coupled to the bond pads and to the lower mounting portions. This permits stacking of electronic components in a small geometry.

Abstract: A conductor substrate for mounting a semiconductor element, at least a portion thereof mounting the semiconductor element being sealed with an insulating resin, wherein an uppermost surface layer of the conductor substrate comprises copper or an alloy thereof, and the conductor substrate is partly or entirely covered with a layer of copper oxide containing a hydroxide formed upon the surface treatment of the conductor substrate and a process of producing the conductor substrate as well as a process for the production of a semiconductor device using the conductor substrate.

Abstract: A flexible printed wiring board comprises a wiring pattern that is made of conductive metal on the surface of an insulating base film and that is protected by bonding an insulating cover layer film to the surface of the wiring pattern in such a manner that the terminal section of the wiring pattern is exposed, wherein the size of the cover layer film is specified previously in such a manner that the shape of the cover layer film is almost same as that of the wiring pattern area from which the terminal section is excluded, from a viewpoint of projection, and the cover layer film is bonded to the wiring pattern area from which the terminal section is excluded. Also disclosed is a method for fabricating a flexible printed wiring board, and a semiconductor device, all that can prevent film edges from peeling and bubbles from being formed in a cover layer film when the cover layer film is bonded to the surface of the wiring pattern.