Abstract: A press-fit semiconductor device includes a lead frame having a die pad, leads with inner and outer lead ends, and a press-fit lead. The press-fit lead has a circular section between an outer lead end and an inner lead end, and the circular section has a central hole that is sized and shaped to receive a press-fit connection pin. A die is attached to the die pad and electrically connected to the inner lead ends of the leads and the inner lead end of the press-fit lead. The die, electrical connections and inner lead ends are covered with an encapsulant that forms a housing. The outer lead ends of the leads extend beyond the housing. The housing has a hole extending therethrough that is aligned with the center hole of the press-fit lead, so that a press-fit connection pin can be pushed through the hole to connect the device to a circuit board.

Abstract: An integrated circuit package is provided with a thin-film battery electrically connected to and encapsulated with an integrated circuit die. The battery can be fabricated on a dedicated substrate, on the die pad, or on the integrated circuit die itself.

Abstract: An integrated circuit package is provided with a thin-film battery electrically connected to and encapsulated with an integrated circuit die. The battery can be fabricated on a dedicated substrate, on the die pad, or on the integrated circuit die itself.

Abstract: A semiconductor device includes a wafer level substrate having a plurality of first conductive vias formed through the wafer level substrate. A first semiconductor die is mounted to the wafer level substrate. A first surface of the first semiconductor die includes contact pads oriented toward a first surface of the wafer level substrate. A first encapsulant is deposited over the first semiconductor die. A second semiconductor die is mounted to the wafer level substrate. A first surface of the second semiconductor die includes contact pads oriented toward a second surface of the wafer level substrate opposite the first surface of the wafer level substrate. A second encapsulant is deposited over the second semiconductor die. A plurality of bumps is formed over the plurality of first conductive vias. A second conductive via can be formed through the first encapsulant and connected to the first conductive via. The semiconductor packages are stackable.

Abstract: A battery protection package assembly is disclosed. The assembly includes a power control integrated circuit (IC) with pins for a supply voltage input (VCC) and a ground (VSS) on a first side of the power control IC. First and second common-drain metal oxide semiconductor field effect transistors (MOSFETs) are electrically coupled to the power control IC. The power control IC and the first and second common-drain metal oxide semiconductor field effect transistors (MOSFET) are co-packaged on a common die pad. The power control IC is vertically stacked on top of one or more of the first and second common-drain MOSFETs. Leads coupled to a supply voltage input (VCC) and a ground (VSS) of the power control IC are on a first side of the common die pad.

Abstract: Embodiments provide a semiconductor light emitting device which comprises a light emitting structure comprising a plurality of compound semiconductor layers, an insulation layer on an outer surface of the light emitting structure, an ohmic layer under the light emitting structure and on an outer surface of the insulation layer, a first electrode layer on the light emitting structure, and a tunnel barrier layer between the first electrode layer and the ohmic layer.

Abstract: A semiconductor package assembly may include a lead frame having a die bonding pad and plurality of leads coupled to the first die bonding pad. A vertical semiconductor device may be bonded to the die bonding pad. The device may have a conductive pad electrically connected to one lead through a first bond wire. An electrically isolated conductive trace may be formed from a layer of conductive material of the first semiconductor device. The conductive trace provides an electrically conductive path between the first bond wire and a second bond wire. The conductive path may either pass underneath a third bond wire thereby avoiding the third bond wire crossing another bond wire, or the conductive path may result in a reduced length for the first and second bond wires that is less than a predetermined maximum length.

Abstract: A combined battery and device apparatus and associated method. This apparatus includes a first conductive layer, a battery comprising a cathode layer; an anode layer, and an electrolyte layer located between and electrically isolating the anode layer from the cathode layer, wherein the anode or the cathode or both include an intercalation material, the battery disposed such that either the cathode layer or the anode layer is in electrical contact with the first conductive layer, and an electrical circuit adjacent face-to-face to and electrically connected to the battery. Some embodiments further include a photovoltaic cell and/or thin-film capacitor. In some embodiments, the substrate includes a polymer having a melting point substantially below 700 degrees centigrade. In some embodiments, the substrate includes a glass. For example, some embodiments include a battery deposited directly on the back of a liquid-crystal display (LCD) device.

Abstract: A stacked-die package for battery protection is disclosed. The battery protection package includes a power control integrated circuit (IC) stacked on top of integrated dual common-drain metal oxide semiconductor field effect transistors (MOSFETs) or two discrete MOSFETs. The power control IC is either stacked on top of one MOSFET or on top of and overlapping both two MOSFETs.

Abstract: A Chip on Board (COB) package which can reduce the manufacturing costs by using a general PCB as a substrate, increase a heat radiation effect from a light source, thereby realizing a high quality light source at low costs, and a manufacturing method thereof. The COB package includes a board-like substrate with a circuit printed on a surface thereof, the substrate having a through hole. The package also includes a light source positioned in the through hole and including a submount and a dome structure made of resin, covering and fixing the light source to the substrate. The invention allows a good heat radiation effect by using the general PCB as the substrate, enabling manufacture of a high quality COB package at low costs. This in turn improves emission efficiency of the light source, ultimately realizing a high quality light source.

Abstract: A sense resistor and integrated circuit package combination is disclosed. A package lead frame is provided having a plurality of landing zones associated therewith and a die mounting area for mounting of a die thereon. The die has a plurality of bond pads associated therewith, with a first bond wire connected between a first one of the landing zones and a second one of the landing zones. The first bond wire forms a sense resistor with a resistance of a known value. A second bond wire is connected between the first one of the landing zones and a first one of the bond pads.