Via Connections Through Substrates, E.g., Pins Going Through Substrate, Coaxial Cables (epo) Patents (Class 257/E23.067)
  • Patent number: 11121067
    Abstract: An electronic device includes a housing, a first substrate disposed in the housing and configured to face a first direction, wherein the first substrate includes a first interconnection, a second substrate located in the first direction from the first substrate, wherein the second substrate includes a second interconnection, and a plurality of interposers formed between the first substrate and the second substrate to electrically connect the first interconnection and the second interconnection, wherein the plurality of interposers is configured to at least partially surround a shielded space formed between the first substrate and the second substrate, wherein each of the plurality of interposers includes a plurality of layers configured to face a direction perpendicular to the first direction, and wherein at least one of the plurality of layers includes a conductive pattern that extends in the first direction and is electrically connected with the first interconnection and the second interconnection.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: September 14, 2021
    Inventor: Eunseok Hong
  • Patent number: 11031370
    Abstract: A semiconductor device structure and a method for manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a method for manufacturing a semiconductor device that comprises ordering and performing processing steps in a manner that prevents warpage deformation from occurring to a wafer and/or die due to mismatching thermal coefficients.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: June 8, 2021
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Yeong Beom Ko, Jin Han Kim, Dong Jin Kim, Do Hyung Kim, Glenn Rinne
  • Patent number: 10980109
    Abstract: A printed circuit board has: a first wiring pattern laid in a first layer such that, when a predetermined component is mounted in a predetermined mounting region, a first current path in an open ring shape leading from a first end to a second end is formed; a second wiring pattern laid in a second layer different from the first layer such that a second current path in an open ring shape leading from a third end to a fourth end is formed; a first conductive member formed between the second and third ends; and a second conductive member formed between the first and fourth ends. The first and second wiring patterns are so laid that, as seen in their respective plan views, the directions of the currents flowing across the first and second current paths, respectively, are opposite to each other.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: April 13, 2021
    Assignee: Rohm Co., Ltd.
    Inventors: Shingo Hashiguchi, Shoichi Harada
  • Patent number: 10936782
    Abstract: A method is presented for incorporating skip vias in a place and route flow of an integrated circuit design. The method includes employing a place and route tool to add the skip vias, each skip via extending through a metallization layer to electrically connect a metal layer above the metallization layer to a metal layer below the metallization layer and, when a violation of a design rule is detected due to the addition of one or more of the skip vias, substituting skip vias that violate the design rule with a standard via.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: March 2, 2021
    Assignee: International Businesss Machines Corporation
    Inventors: Dongbing Shao, Zheng Xu, Lawrence A. Clevenger
  • Patent number: 10867977
    Abstract: A display device and a method for producing a display device are disclosed. In an embodiment a display device includes a flat textile support and a plurality of optoelectronic semiconductor components disposed on the support. Each semiconductor component includes a connection substrate comprising a plurality of electrical connections, the plurality of electrical connections electrically connected via electrically conductive contact threads, wherein each electrical connection is realized by a contact hole which completely penetrates through the semiconductor component and, viewed in a plan view, is surrounded all around by the connection substrate and wherein, in each case, at least one contact thread runs through the contact hole so that the contact thread is arranged in part on an upper side of the semiconductor component facing away from the support, a plurality of semiconductor chips for generating light and at least one control unit for adjusting a color location of the light.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: December 15, 2020
    Assignee: OSRAM OLED GMBH
    Inventors: Frank Singer, Andreas Dobner
  • Patent number: 10831973
    Abstract: A method is presented for incorporating skip vias in a place and route flow of an integrated circuit design. The method includes employing a place and route tool to add the skip vias, each skip via extending through a metallization layer to electrically connect a metal layer above the metallization layer to a metal layer below the metallization layer and, when a violation of a design rule is detected due to the addition of one or more of the skip vias, substituting skip vias that violate the design rule with a standard via.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dongbing Shao, Zheng Xu, Lawrence A. Clevenger
  • Patent number: 10748840
    Abstract: A low resistance metal is charged into holes formed in a semiconductor substrate to thereby form through electrodes. Post electrodes of a wiring-added post electrode component connected together by a support portion thereof are simultaneously fixed to and electrically connected to connection regions formed on an LSI chip. On the front face side, after resin sealing, the support portion is separated so as to expose front face wiring traces. On the back face side, the semiconductor substrate is grounded so as to expose tip ends of the through electrodes. The front face wiring traces exposed to the front face side and the tip ends of the through electrodes exposed to the back face side are used as wiring for external connection.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: August 18, 2020
    Assignee: Invensas Corporation
    Inventor: Masamichi Ishihara
  • Patent number: 10750622
    Abstract: A triggering condition is applied to a conductive polymer positioned in a drilled hole in a printed circuit board. The applied triggering condition causes the polymer to vertically expand within the drilled hole such that the expanded polymer creates an electrically conductive path between contact pads located in different layers of the printed circuit board.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: August 18, 2020
    Assignee: International Business Machines Corporation
    Inventors: Joseph Kuczynski, Timothy Tofil, Jeffrey N. Judd, Matthew Doyle, Scott D. Strand
  • Patent number: 10712374
    Abstract: As means for solving the above-described problem, there is provided a data processing device (1) including a measurement data acquisition unit (10) that acquires measurement data indicating a temporal change in at least one of current consumption and power consumption of an electrical apparatus, a reference component extraction unit (20) that extracts a reference component of the current consumption and a reference component of the power consumption from the measurement data, and a feature value acquisition unit (30) that acquires a feature value of each reference component.
    Type: Grant
    Filed: January 8, 2016
    Date of Patent: July 14, 2020
    Assignee: NEC CORPORATION
    Inventors: Takahiro Toizumi, Eisuke Saneyoshi, Ryota Suzuki, Shigeru Koumoto
  • Patent number: 10701808
    Abstract: A substrate includes: a signal line via, a ground line via, and a power supply line via; a first group of first conductor layers formed at a first wiring layer level and coupled to the signal line via, the ground line via, and the power supply line via; a second conductor layer formed at a second wiring layer level and coupled to the power supply line via; a second group of third conductor layers formed at a third wiring layer level and coupled to the signal line via, the ground line via, and the power supply line via; a first insulating layer; and a second insulating layer, wherein the second insulating layer has an opening with a third insulating layer, a relative dielectric constant of the second insulating layer is higher than the first insulating layer and the third insulating layer, and the opening reaches a conductor pattern.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: June 30, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Tomoyuki Akahoshi, Daisuke Mizutani
  • Patent number: 10586012
    Abstract: A method is presented for incorporating skip vias in a place and route flow of an integrated circuit design. The method includes employing a place and route tool to add the skip vias, each skip via extending through a metallization layer to electrically connect a metal layer above the metallization layer to a metal layer below the metallization layer and, when a violation of a design rule is detected due to the addition of one or more of the skip vias, substituting skip vias that violate the design rule with a standard via.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: March 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Dongbing Shao, Zheng Xu, Lawrence A. Clevenger
  • Patent number: 10571348
    Abstract: A sense die comprises a chip comprising a sense diaphragm, one or more sense elements supported by the diaphragm, one or more bond pads supported by a first side of the chip, a structural frame disposed on the first side of the chip, and one or more electrical contacts extending through the structural frame. Each of the one or more bond pads is electrically coupled to at least one of the one or more sense elements. The structural frame is disposed at least partially about the diaphragm, and the one or more electrical contacts are electrically coupled to the one or more bond pads.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: February 25, 2020
    Assignee: Honeywell International Inc.
    Inventors: Richard Wade, Richard Alan Davis
  • Patent number: 10553363
    Abstract: A multilayer ceramic capacitor (MLCC) includes: a ceramic body having a plurality of dielectric layers, first internal electrodes, and second internal electrodes; and a first external electrode and a second external electrode, disposed on an exterior of the ceramic body. A plurality of via electrodes are disposed in the ceramic body; a first via electrode connects the first internal electrodes to the first external electrode; a second via electrode connects the second internal electrodes to the second external electrode; and the plurality of via electrodes have a stepped shape, and a distance in a length direction from a first vertical edge of each step to a second vertical edge of each step in the plurality of via electrodes is increased in a direction from the substrate toward an upper portion of the ceramic body.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: February 4, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Ji Hyun Park, Jong Bong Lim, Hai Joon Lee
  • Patent number: 10514394
    Abstract: A probe or accessory for use with an electrical test and measurement instrument can include an input to receive an input signal from a device under test (DUT), a clamp control unit or oscilloscope to apply a clamping/limiting level to the input signal to generate an output signal, and/or a control unit output port to provide the clamped/limited output signal to an oscilloscope.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: December 24, 2019
    Assignee: Tektronix, Inc.
    Inventors: Michael J. Mende, Richard A. Booman, Wayne M. Wilburn
  • Patent number: 10509063
    Abstract: Systems and methods provide measurement of one or more electrical parameters (e.g., impedance) of a device under test (DUT) using an electrical parameter measurement device (e.g., multimeter, oscilloscope) that includes reference signal circuitry that generates, detects, and processes common mode reference signals. A measurement device may include a known common mode AC reference voltage source coupled to a common input terminal. During measurement of a DUT, circuitry may detect a signal at a voltage test input terminal and a signal at the common input terminal. The circuitry may process the first and second signals to determine one or more electrical parameters of the DUT, which one or more electrical parameters may be used to implement one or more features. The determined electrical parameters may be presented to an operator via a visual indicator device and/or may be communicated to an external device via a wired and/or wireless communications interface.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: December 17, 2019
    Assignee: FLUKE CORPORATION
    Inventor: Ronald Steuer
  • Patent number: 10498219
    Abstract: An apparatus and a method to adjust a source voltage based on an operating voltage response are provided. The apparatus includes a circuit configured to change state from a first state to a second state comprising receiving an operating voltage from a power source through a power distribution network. The apparatus further includes a sensor configured to measure an operating voltage response to the circuit changing state to receiving the operating voltage. The apparatus further includes a control circuit configured to adjust a source voltage at the power source based on the operating voltage response measured by the sensor. The method includes changing a state to receiving an operating voltage from a power source through a power distribution network, measuring an operating voltage response to the changing state to receiving the operating voltage, and adjusting the source voltage at the power source based on the measured operating voltage response.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: December 3, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Lingyun Wang, Yuan-cheng Pan, Junmou Zhang, Nan Chen, Mohamed Waleed Allam
  • Patent number: 10409343
    Abstract: A cooling system is provided for a 3D integrated circuit (IC) to deliver fluid in x, y, and z dimensions to interior regions of the IC as a means to regulate heat. An IC includes a microfluidic network of channels, at least one sensor and at least one microelectromechanical system (MEMS)-based device that is disposed within the network of channels and that is configured to regulate a flow of fluid within the network of channels. Each sensor monitors a state of the IC. Each MEMS-based device receives control signals based on a state of the IC and regulates a flow of fluid within the network of channels based on control signals that area received on a real-time basis based on changes detected in a state of the IC.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: September 10, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Alexander D. Breslow, Dong Ping Zhang, Nuwan Jayasena
  • Patent number: 10403599
    Abstract: Embedded organic interposers for high bandwidth are provided. Example embedded organic interposers provide thick conductors with more dielectric space, and more routing layers of such conductors than conventional interposers, in order to provide high bandwidth transmission capacity over longer spans. The embedded organic interposers provide high bandwidth transmission paths between components such as HBM, HBM2, and HBM3 memory stacks, and other components. To provide the thick conductors and more routing layers for greater transmission capacity, extra space is achieved by embedding the organic interposers in the core of the package. Example embedded organic interposers lower a resistive-capacitive (RC) load of the routing layers to provide improved signal transmission of 1-2 GHz up to 20-60 GHz bandwidth for each 15 mm length, for example. The embedded organic interposers are not limited to use with memory modules.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: September 3, 2019
    Assignee: Invensas Corporation
    Inventors: Javier A. Delacruz, Belgacem Haba
  • Patent number: 10371717
    Abstract: Structures and methods for directly testing a semiconductor wafer having micro-solder connections. According to one embodiment, a method forms a pattern of micro-solder connections coupled with a through substrate via (TSV) that can be directly tested by electrical probing, without the use of a testing interposer. According to another embodiment, a method tests the pattern of micro-solder connections. According to another embodiment, a novel electrical probe tip structure has contacts on the same pitch as the pattern of micro-solder connections.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: August 6, 2019
    Assignee: International Business Machines Corporation
    Inventors: Victor A. Garibay, Chetan Mehta, Doorlabh Panjwani, Tingdong Zhou
  • Patent number: 10326225
    Abstract: An electrical connector is configured to electrically connect to a chip module, where a bottom surface of the chip module is provided with at least one conductive sheet. The electrical connector includes: an insulating body, configured to sustain the chip module, and provided with at least one accommodating hole penetrating through the insulating body vertically; and at least one terminal, correspondingly accommodated in the at least one accommodating hole, and having at least two elastic arms. Two inner sides of two adjacent elastic arms of the at least two elastic arms are protrudingly provided with two contact portions upward, so that each of the contact portions is located higher than an upper surface of each of the two adjacent elastic arms. An outer side of each elastic arm is spaced from each of the contact portions. The two contact portions upward abut a same conductive sheet of the chip module.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: June 18, 2019
    Assignee: LOTES CO., LTD
    Inventor: Ted Ju
  • Patent number: 10269748
    Abstract: A semiconductor device includes a semiconductor substrate provided with a through hole that extends therethrough from a first surface to a second surface on a side opposite to the first surface, a device layer provided at the first surface of the semiconductor substrate which includes an electrode, an insulating layer that covers the device layer, a first through electrode that extends through the insulating layer, an insulating layer that extends from the second surface of the semiconductor substrate to a bottom surface of the through hole through an inner surface of the through hole of the semiconductor substrate, and in which the portion thereof in contact with the bottom surface has a tapered shape, and a second through electrode electrically connected to the electrode in the device layer that is exposed to the bottom surface of the through hole.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: April 23, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Ippei Kume, Kengo Uchida
  • Patent number: 10219390
    Abstract: A carrier board having two opposite surfaces is provided and a releasing film and a metal layer are formed on the two opposite surfaces respectively. Each metal layer formed with positioning pads is covered with a first hot-melt-dielectric layer where a passive component is disposed. The passive component has upper and lower surfaces each having electrode pads. Each first hot-melt-dielectric layer is disposed on a core board having a cavity to receive the passive component. A second hot-melt-dielectric layer is stacked on each core board. The first and second hot-melt-dielectric layers are heat pressed to form two dielectric layer units each having a top surface and a bottom surface. The carrier board and the releasing films are removed to separate the dielectric layer units. Wiring layers are formed on each top surface and each bottom surface and electrically connected to the electrode pads of the upper and lower surfaces respectively.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: February 26, 2019
    Assignee: Unimicron Technology Corp.
    Inventors: Shih-Pin Hsu, Zhao-Chong Zeng
  • Patent number: 10032694
    Abstract: A power electronics assembly includes a semiconductor device stack having a wide bandgap semiconductor device, a semiconductor cooling chip thermally coupled to the wide bandgap semiconductor device, and a first electrode electrically coupled to the wide bandgap semiconductor device and positioned between the wide bandgap semiconductor device and the semiconductor cooling chip. The semiconductor cooling chip is positioned between a substrate layer and the wide bandgap semiconductor device. The substrate layer includes a substrate inlet port and a substrate outlet port. An integrated fluid channel system extends between the substrate inlet port and the substrate outlet port and includes a substrate fluid inlet channel extending from the substrate inlet port into the substrate layer, a substrate fluid outlet channel extending from the substrate outlet port into the substrate layer, and one or more cooling chip fluid channels extending into the semiconductor cooling chip.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: July 24, 2018
    Assignee: TOYOTA MOTOR ENGINEERING & MANUFACTURING NORTH AMERICA, INC
    Inventors: Yuji Fukuoka, Ercan M. Dede, Shailesh N. Joshi, Feng Zhou
  • Patent number: 9837376
    Abstract: A semiconductor device structure and a method for manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a method for manufacturing a semiconductor device that comprises ordering and performing processing steps in a manner that prevents warpage deformation from occurring to a wafer and/or die due to mismatching thermal coefficients.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: December 5, 2017
    Assignee: AMKOR TECHNOLOGY, INC.
    Inventors: Yeong Beom Ko, Jin Han Kim, Dong Jin Kim, Do Hyung Kim, Glenn Rinne
  • Patent number: 9835665
    Abstract: Functionality for estimating characteristics of an on-chip noise signal can be implemented on a processing module. An on-chip noise signal is determined at an on-chip determination point of a computer chip. The on-chip noise signal is converted to a frequency-varying signal using a voltage-controlled oscillator implemented on the computer chip. The frequency-varying signal is measured at an off-chip measurement point and frequency information is extracted from the frequency-varying signal. The frequency information is converted to a voltage level associated with the on-chip noise signal based on the relationship between an input voltage provided to the voltage-controlled oscillator and an output frequency generated by the voltage-controlled oscillator.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: December 5, 2017
    Assignee: International Business Machines Corporation
    Inventors: Jose A. Hejase, Nanju Na, Nam H. Pham, Lloyd A. Walls
  • Patent number: 9806055
    Abstract: A package according to an embodiment includes a first device package and a fan-out RDL disposed over the first device package. The fan-out RDL extends past edges of the first device package. The first device package comprises a first die having a first redistribution layer (RDL) disposed on a first substrate, a second die having a second RDL disposed on a second substrate, an isolation material over the first die and extending along sidewalls of the second die, and a conductive via. The first RDL is bonded to the second RDL, and the first die and the second die comprise different lateral dimensions. At least a portion of the conductive via extends from a top surface of the isolation material to contact a first conductive element in the first RDL.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: October 31, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Ming-Fa Chen, Sung-Feng Yeh
  • Patent number: 9736948
    Abstract: Systems and methods of manufacturing printed circuit boards using blind and internal micro vias to couple subassemblies. An embodiment of the invention provides a method of manufacturing a printed circuit including attaching a plurality of metal layer carriers to form a first subassembly including at least one copper foil pad on a first surface, applying an encapsulation material onto the first surface of the first subassembly, curing the encapsulation material and the first subassembly; applying a lamination adhesive to a surface of the cured encapsulation material, forming at least one via in the lamination adhesive and the cured encapsulation material to expose the at least one copper foil pad, attaching a plurality of metal layer carriers to form a second subassembly, and attaching the first subassembly and the second subassembly.
    Type: Grant
    Filed: October 28, 2013
    Date of Patent: August 15, 2017
    Assignee: Viasystems Technologies Corp., L.L.C.
    Inventors: Rajesh Kumar, Monte P. Dreyer, Michael J. Taylor
  • Patent number: 9713248
    Abstract: Method for the manufacture of a printed circuit board with at least one cavity for the accommodation of an electronic component, wherein the cavity walls exhibit a reflective, in particular mirrored reflector layer characterized by the following steps: Provision of a printed circuit board, Application of a temporary protective layer onto at least a section of the surface of the circuit board, Creation of the cavity by way of penetration of the protective layer in the region of the cavity, Application of the reflector layer, Removal of the temporary protective layer.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: July 18, 2017
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventors: Gregor Langer, Mario Damej, Ferdinand Lutschounig
  • Patent number: 9698081
    Abstract: Disclosed herein is a package having a first redistribution layer (RDL) disposed on a first semiconductor substrate and a second RDL disposed on a second semiconductor substrate. The first RDL is bonded to the second RDL. The package further includes an insulating film disposed over the second RDL and around the first RDL and the first semiconductor substrate. A conductive element is disposed in the first RDL. A via extends from a top surface of the insulating film, through the first semiconductor substrate to the conductive element, and a spacer is disposed between the first semiconductor substrate and the via. The spacer extends through the first semiconductor substrate.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: July 4, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Ming-Fa Chen, Wen-Ching Tsai
  • Patent number: 9673287
    Abstract: In one implementation, a reliable and robust electrical contact includes a contact pad patterned from a first metal layer situated over a surface of an active die, and multiple dielectric islands situated over the contact pad. The dielectric islands are spaced apart from one another by respective segments of a second metal layer formed between and over the dielectric islands. The contact pad, the dielectric islands, and the second metal layer provide the reliable and robust electrical contact.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: June 6, 2017
    Assignee: Infineon Technologies Americas Corp.
    Inventor: Hugo Burke
  • Patent number: 9666520
    Abstract: Disclosed herein is a package comprising a first die having a first redistribution layer (RDL) disposed on a first side of a first substrate and a second die having a second RDL disposed on a first side of a second substrate, with the first RDL bonded to the second RDL. A third die having a third RDL is disposed on a first side of a third substrate, the third die mounted over the second die, with the second die disposed between the first die and the third die. First vias extend through, and are electrically isolated from, the second substrate, with the first vias each contacting a conductive element in the first RDL or the second RDL. Second vias extend through, and are electrically isolated from, the third substrate, with the second vias each contacting a conductive element in the third RDL or one of the first vias.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: May 30, 2017
    Assignee: Taiwan Semiconductor Manufactuing Company, Ltd.
    Inventors: Chen-Hua Yu, Ming-Fa Chen, Wen-Sen Lu, Wen-Chih Chiou, Wen-Ching Tsai
  • Patent number: 9590326
    Abstract: A contact terminal device for a Printed Circuit Board (PCB), includes the contact terminal being formed to correspondingly cover at least a portion of an opening formed in the PCB and a terminal member fixed onto the PCB, in which the terminal member includes a fixing portion fixed around the opening on a surface of the PCB and a contact terminal portion extending from the fixing portion to be disposed on the opening. The contact terminal for the PCB reduces a height from a surface of the PCB to a contact point with a counterpart component, i.e., a contact height, contributing to reducing the thickness of the portable terminal.
    Type: Grant
    Filed: June 19, 2014
    Date of Patent: March 7, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Soon-Woong Yang, Young-Gyun Kim
  • Patent number: 9543965
    Abstract: An integrated circuit package includes an interposer with an embedded clock network formed by multiple clock trees. A die with first and second clock circuits is disposed over the interposer. At least one of the first and second clock trees is a resonant clock tree and both the first and second clock circuits may provide clock signals at different frequencies. The first clock circuit may provide clock signals at one frequency to a clock tree in the embedded clock network while the second clock circuit may provide clock signals at another frequency to another clock tree in the embedded clock tree network.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: January 10, 2017
    Assignee: Altera Corporation
    Inventor: Weiqi Ding
  • Patent number: 9521759
    Abstract: The invention provides a vertical conductive unit. The vertical conductive unit comprises an insulating layer comprising a connecting via, a first conductor, a second conductor, and a third conductor. The insulating layer comprises photosensitive polyimide, and the glass transition temperature of the photosensitive polyimide is lower than about 200° C. The invention also provides a method for manufacturing the vertical conductive unit.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: December 13, 2016
    Assignee: MICROCOSM TECHNOLOGY CO., LTD.
    Inventor: Tang-Chieh Huang
  • Patent number: 9490231
    Abstract: A semiconductor device structure and a method for manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a method for manufacturing a semiconductor device that comprises ordering and performing processing steps in a manner that prevents warpage deformation from occurring to a wafer and/or die due to mismatching thermal coefficients.
    Type: Grant
    Filed: April 21, 2015
    Date of Patent: November 8, 2016
    Inventors: Yeong Beom Ko, Jin Han Kim, Dong Jin Kim, Do Hyung Kim, Glenn Rinne
  • Patent number: 9455189
    Abstract: A plurality of semiconductor memory devices on a multi-chip package is disclosed. Each semiconductor device may include a plurality of through vias and a plurality of capacitance enhanced through vias. The through vias may provide an electrical connection for signals that may transition between logic states. The capacitance enhanced through vias may provide an electrical connection from a first side to a second side of the respective semiconductor device for transmission signals that remain substantially stable such as reference voltages, power supply voltages or the like. In this way, noise may be reduced and a reservoir of charge for circuits that provide a load for reference voltages and/or power supply voltages may be provided.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: September 27, 2016
    Inventor: Darryl G. Walker
  • Patent number: 9443786
    Abstract: A packaging and cooling apparatus for power semiconductor devices comprising a printed circuit board and a semiconductor module. The semiconductor module having a manifold element and a semiconductor element consisting of power semiconductor devices, thermally conductive plates, and serpentine fin elements. The power semiconductor devices and serpentine fin elements are bonded to the thermally conductive plates on opposing sides to form plate assemblies. The plate assemblies are installed in the windows of the manifold element forming the semiconductor module, which allows for heat removal from each of the power semiconductor devices. The terminals of the semiconductor module are received in the holes of the circuit board, and soldered to traces. The packaging and cooling apparatus may be potted with a resin to prevent leakage of coolant or sealing may be achieved by use of clamped o-rings.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: September 13, 2016
    Assignee: AC Propulsion, Inc.
    Inventors: Wally E. Rippel, Paul F. Carosa, George R. Woody, Lon C. Cooper, David L. Bogdanchik
  • Patent number: 9414496
    Abstract: Implementations of the present disclosure involve an apparatus and/or method for a large array of AC coupling/DC blocking capacitors on a printed circuit board (PCB) of a microelectronic circuit. The method provides for the placement of the blocking capacitors (and associated vias) to be placed on/through the PCB in a small area while yielding low crosstalk or interference between the vias. In one particular embodiment, the blocking capacitors are placed on the PCB in an alternating pattern, with a pair of blocking capacitors placed on the top side of the PCB followed by a pair of blocking capacitors on the bottom side of the PCB, and so on. Further, top side capacitor vias may be back-drilled from the bottom side and bottom side capacitor vias may be back-drilled from the top side.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: August 9, 2016
    Assignee: Oracle International Corporation
    Inventors: Ricki Dee Williams, Ray Ping-kwan Chan
  • Patent number: 9035472
    Abstract: In a semiconductor device, a conductor pattern is disposed in a position overlapped by a semiconductor chip in a thickness direction over the mounting surface (lower surface) of a wiring board. A solder resist film (insulating layer) covering the lower surface of the wiring board has apertures formed such that multiple portions of the conductor pattern are exposed. The conductor pattern has conductor apertures. The outlines of the apertures and the conductor apertures overlap with each other, in a plan view, respectively.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: May 19, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Takaharu Nagasawa
  • Patent number: 9034769
    Abstract: A method for selective removing material from a substrate without damage to copper filling a via and extending at least partially through the substrate. The method comprises oxidizing a semiconductor structure comprising a substrate and at least one copper feature and removing a portion of the substrate using an etchant comprising SF6 without forming copper sulfide on the at least one copper feature. Additional methods are also disclosed, as well as semiconductor structures produced from such methods.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: May 19, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Mark A. Bossler, Jaspreet S. Gandhi, Christopher J. Gambee, Randall S. Parker
  • Patent number: 9029988
    Abstract: A semiconductor device includes an epitaxy layer formed on semiconductor substrate, a device layer formed on the epitaxy layer, a trench formed within the semiconductor substrate and including a dielectric layer forming a liner within the trench and a conductive core forming a through-silicon via conductor, and a deep trench isolation structure formed within the substrate and surrounding the through-silicon via conductor. A region of the epitaxy layer formed between the through-silicon via conductor and the deep trench isolation structure is electrically isolated from any signals applied to the semiconductor device, thereby decreasing parasitic capacitance.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: May 12, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Subramanian S. Iyer, Pranita Kerber, Ali Khakifirooz
  • Patent number: 9030017
    Abstract: An assembly includes a substrate having a substrate conductor and a contact at a first surface and a terminal at a second surface for electrically interconnecting the assembly with a component external to the assembly, at least one of the substrate conductor or the contact being electrically connected with the terminal; a first element having a first surface facing the first surface of the substrate and having a first conductor at the first surface and a second conductor at a second surface, an interconnect structure extending through the first element electrically connecting the first and second conductors; an adhesive layer bonding the first surfaces of the first element and the substrate, at least portions of the first conductor and the substrate conductor being disposed beyond an edge of the adhesive layer; and a continuous electroless plated metal region extending between the first conductor and the substrate conductor.
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: May 12, 2015
    Assignee: Invensas Corporation
    Inventors: Belgacem Haba, Cyprian Emeka Uzoh
  • Patent number: 9024428
    Abstract: A semiconductor device includes a package substrate, and a stack of semiconductor chips over the package substrate, each of the semiconductor chips including first and second surfaces, each of the semiconductor chips including a first through electrode that extends through each of the semiconductor chips, a first surface electrode positioned on the first surface of each of the semiconductor chips, the first surface electrode being coupled to a first end of the first through electrode, a second surface electrode positioned on the second surface of each of the semiconductor chips, the second surface electrode being coupled to a second end of the first through electrode, a second through electrode that extends through each of the semiconductor chips, the second through electrode having third and fourth ends, and a third surface electrode positioned on the second surface of the first semiconductor chip.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: May 5, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventors: Masahiro Yamaguchi, Hiroaki Ikeda
  • Patent number: 9018761
    Abstract: A semiconductor device of the present invention includes a circuit board having a number of electrode portions on the front side and the underside, an electronic circuit element such as a semiconductor chip bonded to the electrode portions on the front side of the circuit board and composing an electronic circuit; and a plurality of ball electrodes for external connection, the ball electrodes being formed on the electrode portions on the underside of the circuit board. Of the electrode portions on the underside of the circuit board, an electrode portion on the outer periphery is formed larger than an electrode portion on the inner periphery. The plurality of ball electrodes are solder balls heated and melted on the electrode portions on the underside of the board so as to form an alloy on the interfaces, the solder balls containing tin and silver but not containing lead.
    Type: Grant
    Filed: January 29, 2008
    Date of Patent: April 28, 2015
    Assignee: Panasonic Corporation
    Inventors: Kouji Oomori, Seishi Oida
  • Patent number: 9018730
    Abstract: A galvanic-isolated coupling of circuit portions is accomplished on the basis of a stacked chip configuration. The semiconductor chips thus can be fabricated on the basis of any appropriate process technology, thereby incorporating one or more coupling elements, such as primary or secondary coils of a micro transformer, wherein the final characteristics of the micro transformer are adjusted during the wafer bond process.
    Type: Grant
    Filed: April 3, 2012
    Date of Patent: April 28, 2015
    Assignee: STMicroelectronics S.r.l.
    Inventors: Crocifisso Marco Antonio Renna, Antonino Scuderi, Carlo Magro, Nunzio Spina, Egidio Ragonese, Barbaro Marano, Giuseppe Palmisano
  • Patent number: 9013031
    Abstract: A semiconductor package includes a lower package including a lower semiconductor chip on a lower package substrate, an upper package on the lower package, and a heat interface material between the lower package and the upper package. The upper package includes an upper semiconductor chip on an upper package substrate including a center portion adjacent to the lower semiconductor chip and an edge portion. The heat interface material is in contact with a top surface of the lower semiconductor chip and the upper package substrate. The upper package substrate includes a heat diffusion via penetrating the center portion and an interconnection via penetrating the edge portion. The interconnection via is spaced apart from the heat diffusion via.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: April 21, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yunhyeok Im, Jichul Kim, Kyol Park, Seongho Shin
  • Patent number: 8987868
    Abstract: Method and apparatus for programmable heterogeneous integration of stacked semiconductor die are described. In some examples, a semiconductor device includes a first integrated circuit (IC) die including through-die vias (TDVs); a second IC die vertically stacked with the first IC die, the second IC die including inter-die contacts electrically coupled to the TDVs; the first IC die including heterogeneous power supplies and a mask-programmable interconnect, the mask-programmable interconnect mask-programmed to electrically couple a plurality of the heterogeneous power supplies to the TDVs; and the second IC die including active circuitry, coupled to the inter-die contacts, configured to operate using the plurality of heterogeneous power supplies provided by the TDVs.
    Type: Grant
    Filed: February 24, 2009
    Date of Patent: March 24, 2015
    Assignee: Xilinx, Inc.
    Inventor: Arifur Rahman
  • Patent number: 8975751
    Abstract: A microelectronic unit can include a substrate having front and rear surfaces and active semiconductor devices therein, the substrate having a plurality of openings arranged in a symmetric or asymmetric distribution across an area of the rear surface, first and second conductive vias connected to first and second pads exposed at the front surface, pluralities of first and second conductive interconnects extending within respective ones of the openings, and first and second conductive contacts exposed for interconnection with an external element. The plurality of first conductive interconnects can be separated from the plurality of second conductive interconnects by at least one of the plurality of openings, the at least one opening at least partially filled with an insulating material. The distribution of the openings can include at least m openings spaced apart in a first direction and n openings spaced apart in a second direction transverse to the first direction.
    Type: Grant
    Filed: April 22, 2011
    Date of Patent: March 10, 2015
    Assignee: Tessera, Inc.
    Inventors: Ilyas Mohammed, Belgacem Haba, Cyprian Uzoh, Piyush Savalia
  • Patent number: 8970043
    Abstract: A wafer structure includes a first wafer stack and a first bonding layer disposed on the first wafer stack. The wafer structure further includes a second wafer stack that includes a first surface and a second surface opposing the first surface. A second bonding layer is disposed on the second surface and is in contact with the first bonding layer. The second wafer stack comprises through-silicon-vias (TSVs) that extend from the first surface to the second bonding layer. A seed layer is disposed on the first surface and is in contact with the TSVs.
    Type: Grant
    Filed: February 1, 2011
    Date of Patent: March 3, 2015
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Quanbo Zou, Uppili Sridhar, Amit S. Kelkar, Xuejun Ying
  • Patent number: 8952522
    Abstract: A method of forming an electronic component package includes coupling a first surface of an electronic component to a first surface of a first dielectric strip, the electronic component comprising bond pads on the first surface; forming first via apertures through the first dielectric strip to expose the bond pads; and filling the first via apertures with an electrically conductive material to form first vias electrically coupled to the bond pads. The bond pads are directly connected to the corresponding first vias without the use of a solder and without the need to form a solder wetting layer on the bond pads.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: February 10, 2015
    Inventors: Ronald Patrick Huemoeller, Sukianto Rusli, David Razu