Conductive Materials Containing Organic Materials Or Pastes, E.g., For Thick Films (epo) Patents (Class 257/E23.075)
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Patent number: 11591499Abstract: An anisotropic conductive film, capable of connecting a terminal formed on a substrate having a wavy surface such as a ceramic module substrate with conduction characteristics stably maintained, includes an insulating adhesive layer, and conductive particles regularly arranged in the insulating adhesive layer as viewed in a plan view. The conductive particle diameter is 10 ?m or more, and the thickness of the film is 1 or more times and 3.5 or less times the conductive particle diameter. The variation range of the conductive particles in the film thickness direction is less than 10% of the conductive particle diameter.Type: GrantFiled: January 13, 2016Date of Patent: February 28, 2023Assignee: DEXERIALS CORPORATIONInventors: Daisuke Sato, Yasushi Akutsu, Ryousuke Odaka, Yusuke Tanaka
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Patent number: 11471941Abstract: Disclosed herein are embodiments of methods, devices, and assemblies for processing feedstock materials using microwave plasma processing. Specifically, the feedstock materials disclosed herein pertains to scrap materials, dehydrogenated or non-hydrogenated feed material, and recycled used powder. Microwave plasma processing can be used to spheroidize and remove contaminants. Advantageously, microwave plasma processed feedstock can be used in various applications such as additive manufacturing or powdered metallurgy (PM) applications that require high powder flowability.Type: GrantFiled: November 23, 2020Date of Patent: October 18, 2022Assignee: 6K Inc.Inventors: John Barnes, Aaron Bent, Kamal Hadidi, Makhlouf Redjdal, Scott Turchetti, Saurabh Ullal, Ning Duanmu, Michael C. Kozlowski
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Patent number: 11239474Abstract: The present invention is to provide a method for producing a catalyst for fuel cells with excellent durability, and a fuel cell comprising a catalyst for fuel cells produced by the production method. Disclosed is a method for producing a catalyst for fuel cells, the catalyst comprising fine catalyst particles, each of which comprises a palladium-containing core particle and a platinum-containing outermost layer covering the core particle, and carbon supports on which the fine catalyst particles are supported, wherein the method comprises the steps of: preparing carbon supports on which palladium-containing particles are supported; fining the carbon supports; and covering the palladium-containing particles with a platinum-containing outermost layer after the fining step.Type: GrantFiled: January 21, 2013Date of Patent: February 1, 2022Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, AUDI AGInventors: Hiroko Kimura, Naoki Takehiro
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Patent number: 10499498Abstract: An electrically conductive composite is disclosed that includes a dielectric material having a first side and a second side, conductive particles within the dielectric material layer, and a discontinuous layer of a conductive material on a first side of the dielectric layer. The conductive particles are aligned to form a plurality of conductive paths from the first side to the second side of the dielectric material, and each of the conductive paths is formed of at least a plurality of conductive particles. The discontinuous layer includes a plurality of non-mutually connected portions that cover portions of, but not all of, the first side of the dielectric material such that exposed portions of the underlying first side of the dielectric material remain exposed through the discontinuous layer, yet the discontinuous layer facilitates the electronic coupling together of a plurality of the conductive paths from the first side to the second side of the dielectric material.Type: GrantFiled: September 25, 2017Date of Patent: December 3, 2019Assignee: FLEXcon Company, Inc.Inventors: Kenneth Burnham, Richard Skov, Stephen Tomas, Jimmy Nguyen, Stephen M. Pizzo, Lisa Crislip
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Patent number: 10147662Abstract: A circuit board includes: a base body formed of ceramics or sapphire, the base body being provided with a through hole which penetrates therethrough from one principal face to another principal face of the base body; a through conductor containing silver as a major constituent, the through conductor being located inside the through hole of the base body; metallic wiring layers located on the respective principal faces of the base body and on the through conductor; and regions in which a compound containing at least one substance selected from Sn, Cu, and Ni is present between the through conductor and the metallic wiring layers.Type: GrantFiled: October 29, 2015Date of Patent: December 4, 2018Assignee: Kyocera CorporationInventor: Yuuichi Abe
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Patent number: 9902862Abstract: A method is provided to make a nano-silver paste. An organic acid is used as a protective agent. Silver nitrate is used as a source of silver ions to reduce silver nanoparticles on a surface protected by the organic acid. The particle size of the silver nanoparticle is 45 nanometers. In the other hand, a silver precursor of organic metal is synthesized. The organic metal is cracked at 200 celsius degrees (° C.) to fill pores left during sintering. After mixing the silver nanoparticle, the silver precursor and the solvent, the nano-silver paste is obtained. After being heated at 250° C. for 30 minutes, the nano-silver paste has a resistance of (3.09±0.61)×10?5 ?·cm. By being heated at 250° C. and applied with a pressure of 10 MPa to be hot-pressed for 30 minutes for joining copper to copper, the nano-silver paste obtains a bonding strength reaching 36 MPa.Type: GrantFiled: July 6, 2016Date of Patent: February 27, 2018Assignee: NATIONAL CHENG KUNG UNIVERSITYInventors: Steve Lien-Chung Hsu, Yen-Ting Chen, In-Gann Chen
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Patent number: 9717149Abstract: Process for producing a ceramic circuit board with electrical conductor traces and contacting points on a side and with a through-hole contact by successively a) producing an AlN substrate and drilling holes at the locations for the vias, b) filling the holes with an adhesive paste containing copper, tungsten and/or molybdenum or alloys thereof, and c) single-pass overprinting with a second adhesive paste using a first screen-printing operation on a side of the ceramic substrate with the layout of the conductor traces and contact points, d) optionally, fully or partially repeating overprinting with the second adhesive paste, e) stoving the printed ceramic substrate in an oven with N2 while controlling oxygen at 0-50 ppm O2, f) overprinting using a second screen-printing process with a low-glass cover paste over the second adhesive paste, and g) stoving the printed ceramic substrate with N2 while keeping the oxygen content at 0-50 ppm O2.Type: GrantFiled: October 31, 2012Date of Patent: July 25, 2017Assignee: CeramTec GmbHInventors: Alexander Dohn, Roland Leneis, Klaus Herrmann, Dietmar Jähnig
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Patent number: 8933553Abstract: A semiconductor unit includes a first conductive layer, a second conductive layer electrically insulated from the first conductive layer, a first semiconductor device mounted on the first conductive layer, a second semiconductor device mounted on the second conductive layer, a first bus bar for electrical connection of the second semiconductor device to the first conductive layer, and a second bus bar for electrical connection of the first semiconductor device to one of the positive and negative terminals of a battery. The first bus bar is disposed in overlapping relation to the second bus bar in such a manner that mold resin fills between the first bus bar and the second bus bar.Type: GrantFiled: July 3, 2013Date of Patent: January 13, 2015Assignee: Kabushiki Kaisha Toyota JidoshokkiInventors: Shinsuke Nishi, Shogo Mori, Yuri Otobe, Naoki Kato
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Patent number: 8697485Abstract: Printed electronic device comprising a substrate onto at least one surface of which has been applied a layer of an electrically conductive ink comprising functionalized graphene sheets and at least one binder. A method of preparing printed electronic devices is further disclosed.Type: GrantFiled: September 5, 2012Date of Patent: April 15, 2014Assignees: Vorbeck Materials Corporation, The Trustees of Princeton UniversityInventors: John M. Crain, John S. Lettow, Ilhan A. Aksay, Sibel A. Korkut, Katherine S. Chiang, Chuan-Hua Chen, Robert K. Prud'Homme
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Patent number: 8456017Abstract: By adding particles of high thermal conductivity and low thermal expansion coefficient into the copper as a composite material and filling with the composite material into the through-via hole, the mismatch of the coefficient of thermal expansion and the stress of the through-silicon via are lowered and the thermal conductivity of the through-silicon via is increased.Type: GrantFiled: July 1, 2011Date of Patent: June 4, 2013Assignee: Industrial Technology Research InstituteInventors: Ming-Ji Dai, Heng-Chieh Chien, Ming-Che Hsieh, Jui-Feng Hung, Ra-Min Tain, John H. Lau
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Patent number: 8343386Abstract: An electrostatically dissipative adhesive in one embodiment includes a mixture comprising: an adhesive material; and electrically conductive particles intermixed with the adhesive material, the electrically conductive particles being present in an amount between 0 and about 10% by weight of a total weight of the mixture. An electrostatically dissipative adhesive in another embodiment includes a mixture comprising: an adhesive material; and electrically conductive particles intermixed with the adhesive material, the electrically conductive particles being present in an amount between 0 and about 10% by weight of a total weight of the mixture, wherein the mixture has at least 50% of a lap shear strength as measured in accordance with ISO 4587 after curing for 72 hours at 22° C. as the raw adhesive material has as measured in accordance with ISO 4587 after curing for 72 hours at 22° C.Type: GrantFiled: May 21, 2008Date of Patent: January 1, 2013Assignee: International Business Machines CorporationInventors: William Thomas Bandy, IV, Icko E. Tim Iben, Wayne Alan McKinley
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Patent number: 8288792Abstract: A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and first and second adhesives. The heat spreader includes a first post, a second post and a base. The conductive trace includes a pad and a terminal. The semiconductor device is electrically connected to the conductive trace and thermally connected to the heat spreader. The first post extends from the base in a first vertical direction into a first opening in the first adhesive, the second post extends from the base in a second vertical direction into a second opening in the second adhesive and the base is sandwiched between and extends laterally from the posts. The conductive trace provides signal routing between the pad and the terminal.Type: GrantFiled: January 10, 2011Date of Patent: October 16, 2012Assignee: Bridge Semiconductor CorporationInventors: Charles W. C. Lin, Chia-Chung Wang
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Patent number: 8241957Abstract: A method for fabricating a negative thermal expanding system device includes coating a wafer with a thermally decomposable polymer, patterning the decomposable polymer into repeating disk patterns, releasing the decomposable polymer from the wafer and forming a sheet of repeating patterned disks, suspending the sheet into a first solution with seeding compounds for electroless decomposition, removing the sheet from the first solution, suspending the sheet into a second solution to electrolessly deposit a first layer material onto the sheet, removing the sheet from the second solution, suspending the sheet into a third solution to deposit a second layer of material having a lower TCE value than the first layer of material, separating the patterned disks from one another, and annealing thermally the patterned disks to decompose the decomposable polymer and creating a cavity in place of the decomposable polymer.Type: GrantFiled: October 18, 2010Date of Patent: August 14, 2012Assignee: International Business Machines CorporationInventors: Gareth Geoffrey Hougham, S. Jay Chey, James Patrick Doyle, Xiao Hu Liu, Christopher V. Jahnes, Paul Alfred Lauro, Nancy C. LaBianca, Michael J. Rooks
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Patent number: 8178893Abstract: The invention provides a semiconductor element mounting substrate that, by virtue of an improvement in thermal conduction efficiency between the substrate and another member, can reliably prevent, for example, a light emitting element such as a semiconductor laser from causing a defective operation by heat generation of itself, by taking full advantage of high thermal conductivity of a diamond composite material.Type: GrantFiled: December 21, 2006Date of Patent: May 15, 2012Assignee: A. L. M. T. Corp.Inventors: Kouichi Takashima, Hideaki Morigami, Masashi Narita
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Patent number: 8067827Abstract: An assembly of microelectronic devices and method for forming an assembly of microelectronic devices. In one embodiment, the method includes positioning a first packaged microelectronic device adjacent to a support member having support member circuitry, with the first packaged microelectronic device having a first microelectronic die at least partially encased in a first encapsulant to define a first package configuration. The method can further include electrically connecting the first packaged microelectronic device to a first portion of the support member circuitry and positioning at least proximate to the first packaged microelectronic device a second packaged microelectronic device having a second microelectronic die at least partially encased in a second encapsulant to define a second package configuration different than the first package configuration. The first packaged microelectronic device can be positioned between the support member and the second packaged microelectronic device.Type: GrantFiled: May 21, 2007Date of Patent: November 29, 2011Assignee: Micron Technology, Inc.Inventor: David J. Corisis
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Patent number: 7893532Abstract: An external contact material for external contacts of a semiconductor device and a method for producing the same are described. The external contact material includes a lead-free solder material. Provided in the solder material is a filler which forms a plurality of gas pores and/or has plastic particles which are arranged in the volume of the solder material.Type: GrantFiled: September 13, 2006Date of Patent: February 22, 2011Assignee: Infineon Technologies AGInventors: Michael Bauer, Irmgard Escher-Poeppel, Edward Fuergut, Simon Jerebic, Bernd Rakow, Peter Strobel, Holger Woerner
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Patent number: 7847397Abstract: An apparatus composed of: (a) a substrate; and (b) a deposited composition comprising a liquid and a plurality of metal nanoparticles with a covalently bonded stabilizer.Type: GrantFiled: December 12, 2007Date of Patent: December 7, 2010Assignee: Xerox CorporationInventors: Yiliang Wu, Yuning Li, Beng S Ong
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Patent number: 7641811Abstract: A thermal conducting mixture is provided which is used to make thermal conducting formulations such as a paste having a high thermal conductivity and a relatively low viscosity. The paste is used to provide a thermal conductor connection between an electronic component and a cooling device to increase the heat transfer rate between the component and the device cooling the electronic component. The formulation contains the mixture of thermally conductive particles in various particle size ranges typically dispersed in a non-aqueous dielectric carrier containing an antioxidant and a dispersant with the thermally conductive particles mixture being specially correlated in the mixture by volume % based on particle size range and by particle size ratio of each particle size range. The mixture may be used to make other similar products such as thermal gels, adhesives, slurries and composites, for electronic and cosmetics, pharmaceuticals, automotive, and like products.Type: GrantFiled: August 22, 2008Date of Patent: January 5, 2010Assignee: International Business Machines CorporationInventors: Rajneesh Kumar, Stephen P. Ostrander
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Patent number: 7622803Abstract: An assembly for supporting a substrate during vacuum processing operations includes a thermally conductive heat sink tray including at least one wafer pocket recessed therein, and a thermally conductive heat sink carrier in the at least one wafer pocket. The heat sink carrier includes a first surface in contact with a surface within the at least one wafer pocket and a second surface opposite the first surface. A heat sink is affixed to the second surface of the heat sink carrier.Type: GrantFiled: August 24, 2006Date of Patent: November 24, 2009Assignee: Cree, Inc.Inventors: Winston T. Parker, Van Mieczowski, Jim Wood, Daniel Cronin, David Emerson
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Patent number: 7571536Abstract: A method of making capacitive/resistive devices provides both resistive and capacitive functions. The capacitive/resistive devices may be embedded within a layer of a printed wiring board. Embedding the capacitive/resistive devices conserves board surface real estate, and reduces the number of solder connections, thereby increasing reliability.Type: GrantFiled: January 26, 2007Date of Patent: August 11, 2009Assignee: E. I. du Pont de Nemours and CompanyInventor: David Ross McGregor
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Patent number: 7560371Abstract: Methods of forming a conductive via in a substrate include contacting the substrate with a wave of conductive liquid material, such as molten solder, and drawing the liquid material into the aperture with a vacuum. The wave may be formed by flowing the liquid material out from an outlet in a direction generally against the gravitational field. The liquid material may be solidified to form an electrically conductive structure. A plurality of apertures may be selectively filled with the liquid material one at a time, and liquids having different compositions may be used to provide conductive vias having different compositions in the same substrate. Systems for forming conductive vias include a substrate fixture, a vacuum device having a vacuum fixture, and a solder-dispensing device configured to provide a wave of molten solder material. Relative lateral and vertical movement is provided between the wave of molten solder and a substrate supported by the substrate fixture.Type: GrantFiled: August 29, 2006Date of Patent: July 14, 2009Assignee: Micron Technology, Inc.Inventors: Ross S. Dando, Steven Oliver, Swarnal Borthakur, Kevin Hutto
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Patent number: 7462294Abstract: A thermal conducting mixture is provided which is used to make thermal conducting formulations such as a paste having a high thermal conductivity and a relatively low viscosity. The paste is used to provide a thermal conductor connection between an electronic component and a cooling device to increase the heat transfer rate between the component and the device cooling the electronic component. The formulation contains the mixture of thermally conductive particles in various particle size ranges typically dispersed in a non-aqueous dielectric carrier containing an antioxidant and a dispersant with the thermally conductive particles mixture being specially correlated in the mixture by volume % based on particle size range and by particle size ratio of each particle size range. The mixture may be used to make other similar products such as thermal gels, adhesives, slurries and composites, for electronic and cosmetics, pharmaceuticals, automotive, and like products.Type: GrantFiled: April 25, 2007Date of Patent: December 9, 2008Assignee: International Business Machines CorporationInventors: Rajneesh Kumar, Steven P Ostrander
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Patent number: 7443027Abstract: An apparatus composed of: (a) a substrate; and (b) a deposited composition comprising a liquid and a plurality of metal nanoparticles with a covalently bonded stabilizer.Type: GrantFiled: November 3, 2005Date of Patent: October 28, 2008Assignee: Xerox CorporationInventors: Yiliang Wu, Yuning Li, Beng S. Ong
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Patent number: 7429778Abstract: There is provided a method for forming wiring or an electrode by coating a substrate with a composition comprising (A) a complex of an amine compound and a hydrogenated aluminum compound and (B) a titanium compound or a composition comprising the complex and (C) metal particles and subjecting the obtained coating film to heating and/or a light treatment. By the method, a film can be formed that uses a conductive film forming composition with which wiring and an electrode that can be suitably used for electronic devices can be formed easily and inexpensively.Type: GrantFiled: September 29, 2005Date of Patent: September 30, 2008Assignees: JSR Corporation, Sharp CorporationInventors: Michiko Yokoyama, legal representative, Naomi Shinoda, legal representative, Risa Yokoyama, legal representative, Isamu Yonekura, Takashi Satoh, Tamaki Wakasaki, Yasumasa Takeuchi, Masayuki Endo, Yasuaki Yokoyama
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Patent number: 7345331Abstract: A ferroelectric capacitor circuit for sensing hydrogen gas having a closed integrated circuit package, a ferroelectric capacitor within the closed integrated circuit package, the ferroelectric capacitor having a bismuth oxide based ferroelectric layer being able to absorb hydrogen gas that is within the closed integrated circuit package, absorbed hydrogen gas chemically reducing a portion of the bismuth oxide based ferroelectric layer into bismuth metal, the ferroelectric capacitor having a ferroelectric voltage, the ferroelectric voltage having a voltage strength, and means for measuring a decrease in the voltage strength of the ferroelectric voltage of the ferroelectric capacitor.Type: GrantFiled: September 23, 2005Date of Patent: March 18, 2008Assignee: United States of America as represented by the Secretary of the NavyInventors: Orville G. Ramer, Stuart C. Billette
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Patent number: 7276787Abstract: A carrier structure and method for fabricating a carrier structure with through-vias each having a conductive structure with an effective coefficient of thermal expansion which is less than or closely matched to that of the substrate, and having an effective elastic modulus value which is less than or closely matches that of the substrate. The conductive structure may include concentric via fill areas having differing materials disposed concentrically therein, a core of the substrate material surrounded by an annular ring of conductive material, a core of CTE-matched non-conductive material surrounded by an annular ring of conductive material, a conductive via having an inner void with low CTE, or a full fill of a conductive composite material such as a metal-ceramic paste which has been sintered or fused.Type: GrantFiled: December 5, 2003Date of Patent: October 2, 2007Assignee: International Business Machines CorporationInventors: Daniel Charles Edelstein, Paul Stephen Andry, Leena Paivikki Buchwalter, Jon Alfred Casey, Sherif A. Goma, Raymond R. Horton, Gareth Geoffrey Hougham, Michael Wayne Lane, Xiao Hu Liu, Chirag Suryakant Patel, Edmund Juris Sprogis, Michelle Leigh Steen, Brian Richard Sundlof, Cornelia K. Tsang, George Frederick Walker
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Patent number: 7262498Abstract: An assembly includes a substrate, a device coupled to the substrate; a ring formed on the substrate; and one or more bonding pads formed on the substrate, wherein the ring and bonding pads are formed of a same material.Type: GrantFiled: January 18, 2005Date of Patent: August 28, 2007Assignee: Hewlett-Packard Development Company, L.P.Inventors: David M. Craig, Chien-Hua Chen, Charles C. Haluzak, Ronnie J. Yenchik
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Patent number: 7253523Abstract: A process of making a reworkable thermal interface material is described. The reworkable thermal interface material is bonded to a die and a heat sink. The reworkable thermal interface material includes a phase-change polymer matrix material. Other materials in the reworkable thermal interface material can include heat transfer particles and low melting-point metal particles. The phase-change polymer matrix material includes a melting temperature below a selected temperature and the heat transfer particles have a melting temperature substantially above the selected temperature. The heat transfer particles act as a spacer limit, which holds the thermal interface material to a given bond-line thickness during use.Type: GrantFiled: July 29, 2003Date of Patent: August 7, 2007Assignee: Intel CorporationInventors: Ashay A. Dani, Scott Gilbert, Ajit V. Sathe, Ravi Prasher
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Patent number: 7235871Abstract: An assembly of microelectronic devices and method for forming an assembly of microelectronic devices. In one embodiment, the method includes positioning a first packaged microelectronic device adjacent to a support member having support member circuitry, with the first packaged microelectronic device having a first microelectronic die at least partially encased in a first encapsulant to define a first package configuration. The method can further include electrically connecting the first packaged microelectronic device to a first portion of the support member circuitry and positioning at least proximate to the first packaged microelectronic device a second packaged microelectronic device having a second microelectronic die at least partially encased in a second encapsulant to define a second package configuration different than the first package configuration. The first packaged microelectronic device can be positioned between the support member and the second packaged microelectronic device.Type: GrantFiled: July 15, 2003Date of Patent: June 26, 2007Assignee: Micron Technology, Inc.Inventor: David J. Corisis
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Patent number: 7227240Abstract: A semiconductor device (10) includes a semiconductor die (20) and an inductor (30, 50) formed with a bonding wire (80) attached to a top surface (21) of the semiconductor die. The bonding wire is extended laterally a distance (L30, L150) greater than its height (H30, H50) to define an insulating core (31, 57). In one embodiment, the inductor is extended beyond an edge (35, 39) of the semiconductor die to reduce loading.Type: GrantFiled: September 10, 2002Date of Patent: June 5, 2007Assignee: Semiconductor Components Industries, L.L.C.Inventors: James Knapp, Francis Carney, Harold Anderson, Yenting Wen, Cang Ngo
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Patent number: 7202154Abstract: A metallization process and material system for metallizing either blind or through vias in silicon, involving forming a low coefficient of thermal expansion composite or suspension, relative to pure metals, such as copper, silver, or gold, and filling the via holes in the silicon with the paste or suspension. The suspensions sinter with minimal bulk shrinkage, forming highly conductive structures without the formation of macroscopic voids. The selected suspension maintains a coefficient of thermal expansion closer to that of silicon.Type: GrantFiled: January 5, 2004Date of Patent: April 10, 2007Assignee: International Business Machines CorporationInventors: Jon A. Casey, Brian R. Sundlof
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Patent number: 7148562Abstract: A plurality of power semiconductor chips (power transistors or the like) are arranged, being separated from each other with a free space of a terminal board interposed therebetween. A radiating block is in contact with an insulating layer (a package and grease below the terminal board) below an arrangement region of each of the power semiconductor devices and a region between power semiconductor devices, and this increases a heat dissipation effect. With this construction, it is possible to provide a power semiconductor device and a power semiconductor module which ensure an excellent dissipation effect of heat radiated in operation of the power semiconductor chips.Type: GrantFiled: June 22, 2004Date of Patent: December 12, 2006Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Takanobu Yoshida, Shinji Hatae
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Patent number: 7091603Abstract: In a semiconductor device having semiconductor chips, a lower heat sink which is joined on the principal rear surface side of the semiconductor chips and an upper heat sink which is joined on the principal front surface side of the semiconductor chips, wherein substantially the whole device is encapsulated with a molded resin, the thick-walled portion of a resin lying around a mounted portion is provided with holes which are resin-flow hindering portions for hindering the flow of the resin during the molding thereof, whereby air bubbles are prevented from appearing in the resin within the mounted portion.Type: GrantFiled: December 16, 2004Date of Patent: August 15, 2006Assignee: Denso CorporationInventors: Kuniaki Mamitsu, Yoshimi Nakase
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Patent number: RE41559Abstract: A chip scale package has a semiconductor MOSFET die which has a top electrode surface covered with a layer of a photosensitive liquid epoxy which is photolithographically patterned to expose portions of the electrode surface and to act as a passivation layer and as a solder mask. A solderable contact layer is then formed over the passivation layer. The individual die are mounted drain side down in a metal clip or can with the drain electrode disposed coplanar with a flange extending from the can bottom. The metal clip or drain clip has a plurality, a parallel spaced fins extending from its outwardly facing surface.Type: GrantFiled: August 31, 2006Date of Patent: August 24, 2010Assignee: International Rectifier CorporationInventor: Charles S. Cardwell
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Patent number: RE41721Abstract: A semiconductor device comprising a semiconductor pellet mounted on a pellet mounting area of the main surface of a base substrate, in which first electrode pads arranged on the back of the base substrate are electrically connected to bonding pads arranged on the main surface of the semiconductor pellet. The base substrate is formed of a rigid substrate, and its first electrode pads are electrically connected to the second electrode pads arranged on its reverse side. The semiconductor pellet is mounted on the pellet mounting area of the main surface of the base substrate, with its main surface downward, and its bonding pads are connected electrically with the second electrode pads of the base substrate through bonding wires passing through slits formed in the base substrate.Type: GrantFiled: July 7, 2000Date of Patent: September 21, 2010Assignee: Renesas Electronics CorporationInventors: Atsushi Nakamura, Kunihiko Nishi
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Patent number: RE43444Abstract: A semiconductor device comprising a semiconductor pellet mounted on a pellet mounting area of the main surface of a base substrate, in which first electrode pads arranged on the back of the base substrate are electrically connected to bonding pads arranged on the main surface of the semiconductor pellet. The base substrate is formed of a rigid substrate, and its first electrode pads are electrically connected to the second electrode pads arranged on its reverse side. The semiconductor pellet is mounted on the pellet mounting area of the main surface of the base substrate, with its main surface downward, and its bonding pads are connected electrically with the second electrode pads of the base substrate through bonding wires passing through slits formed in the base substrate.Type: GrantFiled: November 23, 2005Date of Patent: June 5, 2012Assignee: Renesas Electronics CorporationInventors: Atsushi Nakamura, Kunihiko Nishi