Abstract: A method for manufacturing an electronics assembly, includes obtaining or producing an electronics module, which includes a first circuitry on a first surface at a first side of a circuit board, at least one electronics component on the circuit board in electrical connection with the first circuitry, and at least one first connection portion on the first surface and/or an adjacent side surface at a peripheral portion of the circuit board, wherein the at least one first connection portion is electrically connected to or comprised in the first circuitry. The method further includes arranging the electronics module on a second substrate including a second connection portion connected to a second circuitry on a surface of the second substrate, and arranging electrically conductive joint material onto the first and second connection portions to extend between them for electrically connecting the electronics module to the second circuitry.

Abstract: A package for mounting on a mounting base is disclosed. In one example, the package comprises a carrier, an electronic component mounted at the carrier, leads electrically coupled with the electronic component and to be electrically coupled with the mounting base, and a linear spacer for defining a spacing with respect to the carrier.

Abstract: The present invention provides a package structure and a method for manufacturing the same. The package structure includes at least two electrical elements, a second reconstruction layer, and a metal lead frame, wherein at least one of the electrical elements is a chip, at least one of the electrical elements has a first reconstruction layer, and the second reconstruction layer has a smaller pin pitch than that of the metal lead frame; the second reconstruction layer has a first surface and a second surface, a functional surface of the electrical element is disposed on and connected to the first surface, and at least one of the electrical elements is connected to the second reconstruction layer; and the second surface is disposed on and connected to the metal lead frame. A fan-out package structure is formed on the metal lead frame, which improves the heat dissipation capacity of the chip.

Abstract: In an embodiment, a device includes: an interposer; a first integrated circuit device attached to the interposer; a second integrated circuit device attached to the interposer adjacent the first integrated circuit device; a heat dissipation die on the second integrated circuit device; and an encapsulant around the heat dissipation die, the second integrated circuit device, and the first integrated circuit device, a top surface of the encapsulant being coplanar with a top surface of the heat dissipation die and a top surface of the first integrated circuit device.

Abstract: A plastic material substrate has a die mounting location for a semiconductor die. Metallic traces are formed on selected areas of the plastic material substrate, wherein the metallic traces provide electrically-conductive paths for coupling to the semiconductor die. The semiconductor die is attached onto the die mounting location. The semiconductor die attached onto the die mounting location is electrically bonded to selected ones of the metallic traces formed on the plastic material substrate. A package material is molded onto the semiconductor die attached onto the die mounting location.

Abstract: A semiconductor device includes: multiple semiconductor elements each having a one surface and a rear surface in a plate thickness direction; a first member that sandwiches the multiple semiconductor elements and is electrically connected to an electrode on the one surface; a second member electrically connected to an electrode on the rear surface; and multiple terminals that are continuous from the first or second member. An area of the second member is smaller than that of the first member. Semiconductor elements are arranged in a longitudinal direction of the second member. The semiconductor device further includes a first joint portion that electrically connects each semiconductor element and the second member and a second joint portion that electrically connects a terminal and the second member. The multiple solder joint portions are symmetrically placed.

Abstract: A hybrid strain sensing system and the method of making such a system provides a thin semiconductor film with strain sensors and signal processing circuits integrated deposited thereon. The semiconductor film may be further processed and then mounted onto a substrate to be used for strain, force, or other related measurements. The system combines the high sensitivity of a semiconductor strain gauge with the high level of integration of semiconductor integrated circuits (IC)s. Both are highly desirable features for applications where miniaturization and/or flexibility are important requirements.

Abstract: A semiconductor device includes a semiconductor package, including a package body that includes an encapsulant portion and an isolation structure, a semiconductor die embedded within the package body, and a plurality of leads that protrude out from the encapsulant body, wherein the encapsulant portion and the isolation structure are each electrically insulating structures, wherein the isolation structure has a greater thermal conductivity than the encapsulant portion, and wherein the isolation structure is thermally coupled to the semiconductor die, and a releasable layer affixed to the semiconductor package, wherein a first outer face of the package body includes a first surface of the isolation structure, wherein the releasable layer at least partially covers the first surface of the isolation structure, and wherein the releasable layer is releasable from the semiconductor package.

Abstract: A chip package including a heat-dissipating device, a first thermal interface material layer disposed on the heat-dissipating device, a patterned circuit layer disposed on the first thermal interface material layer, a chip disposed on the patterned circuit layer and electrically connected to the patterned circuit layer, and an insulating encapsulant covering the chip, the patterned circuit layer, and the first thermal interface material layer is provided. The first thermal interface material layer has a thickness between 100 ?m and 300 ?m. The first thermal interface material layer is located between the patterned circuit layer and the heat-dissipating device.

Abstract: A semiconductor device according to an embodiment includes a base frame, a semiconductor element provided on the base frame, a connector provided on the semiconductor element, the connector having an upper surface, a side surface, and a porous body having a plurality of pores provided on at least the side surface, and a molded resin provided in a periphery of the semiconductor element and at least the side surface of the connector. The upper surface of the connector is exposed.

Abstract: In some examples, a semiconductor package comprises a lead frame. The lead frame includes a first row of leads; a first pad coupled to the first row of leads; a second row of leads; and a second pad coupled to the second row of leads, the first and second pads separated by a gap. The semiconductor package includes a heat-generating device coupled to the first and second pads and exposed to an exterior of the semiconductor package.

Abstract: In a general aspect, a semiconductor device assembly can include a semiconductor substrate that excludes a buried oxide layer. The semiconductor device assembly can also include a first semiconductor device stack disposed on a first portion of the semiconductor substrate, and a second semiconductor device stack disposed on a second portion of the semiconductor substrate. The semiconductor device assembly can further include an isolation trench having a dielectric material disposed therein, the isolation trench being disposed between the first portion of the semiconductor substrate and the second portion of the semiconductor substrate. The isolation trench can electrically isolate the first portion of the semiconductor substrate from the second portion of the semiconductor substrate.

Abstract: A semiconductor device with high heat dissipation efficiency includes a base structure, a semiconductor chip, a heat dissipating structure, and a package body. The semiconductor chip is disposed on the base structure and has a first surface distant from the base structure. The heat dissipating structure includes a buffer layer and a first heat spreader. The buffer layer is disposed on the first surface of the semiconductor chip and a coverage rate thereof on the first surface is at least 10%. The first heat spreader is disposed on the buffer layer and bonded to the first surface of the semiconductor chip through the buffer layer. The package body encloses the semiconductor chip and the heat dissipating structure, and the package body and the buffer layer have the same heat curing temperature.

Abstract: The present disclosure discloses a trench Insulated Gate Bipolar Transistor (IGBT) packaging structure and a method for manufacturing the trench Insulated Gate Bipolar Transistor packaging structure. The trench IGBT packaging structure includes: a trench IGBT, which includes an emitting electrode metal layer, and a trench gate electrode; a lead frame, which includes a chip placement area and an emitting electrode lead-out end; a first bonding wire connecting the emitting electrode metal layer and an emitting electrode pin. One end of the first bonding wire is connected to a surface, away from the trench gate electrode, of the emitting electrode metal layer to form a strip-shaped first solder joint, the other end is connected to the emitting electrode lead-out end to form a second solder joint, and an extension direction of the first solder joint is perpendicular to an extension direction of the trench of the trench gate electrode.

Abstract: A power module has a plurality of packaged power semiconductors, a printed circuit board, a heat sink, and possibly a sealing compound. The power semiconductors have electrically conductive connection elements and heat removal areas on respective outer sides. The power semiconductors are arranged on a cooling surface of the heat sink and has its heat removal area connected to the cooling surface of the heat sink to conduct heat, and the printed circuit board is arranged on a side of the power semiconductors that is opposite the heat sink in an orthogonal direction, wherein the connection elements of the power semiconductors make electrical contact with pads on the printed circuit board regions, for example, laterally beside an edge of the heat sink, in which a projection of the heat sink onto the printed circuit board in the orthogonal direction does not cover the connection elements.

Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.

Abstract: A packaged integrated circuit includes a core structure with a cavity therein; a component accommodated in the cavity; an electrically insulating structure formed over the core structure and the component; a partially electrically insulating carrier structure formed below the core structure and the component; and an electrically conducting redistribution arrangement formed at least partially within the carrier structure. The redistribution arrangement includes conductor structures each having a first element extending through the carrier structure and electrically connecting a contact of the component and a second element below the carrier structure. A part of the second element is a contact pad for electrically connecting the redistribution arrangement with external circuitry. The carrier structure includes a polyimide layer and an adhesive layer.

Abstract: A power electronic switching device has a substrate facing in a normal direction with a first and a second conductive track, and a power semiconductor component is arranged on the first conductive track by an electrically conductive connection. The power semiconductor component has a laterally surrounding edge and an edge region and a contact region on its first primary side facing away from the substrate, and with a three-dimensionally preformed insulation molding that has an overlap segment, a connection segment and an extension segment, wherein the overlap segment, starting from the edge partially overlaps the edge region of the power semiconductor component.

Abstract: Various embodiments of an integrated circuit package and a method of forming such package are disclosed. The package includes a substrate having a core layer disposed between a first dielectric layer and a second dielectric layer, a die disposed in a cavity of the core layer, and an encapsulant disposed in the cavity between the die and a sidewall of the cavity. The package further includes a first patterned conductive layer disposed within the first dielectric layer, a device disposed on an outer surface of the first dielectric layer such that the first patterned conductive layer is between the device and the core layer, a second patterned conductive layer disposed within the second dielectric layer, and a conductive pad disposed on an outer surface of the second dielectric layer such that the second patterned conductive layer is between the conductive pad and the core layer.

Abstract: A semiconductor structure includes a molding, a device in the molding, and a RDL over the device and the molding. The RDL includes a first portion directly over a surface of the molding, and a second portion directly over a surface of the device. A bottom surface of the first portion is in contact with the surface of the molding, and a bottom surface of the second portion is in contact with the surface of the device. The bottom surface of the first portion of the RDL and the bottom surface of the second portion of the RDL are at different levels and misaligned from each other. A thickness of the first portion is greater than a thickness of the second portion.

Abstract: An embodiment is a method including depositing a first dielectric layer over a molding compound and a chip and patterning a first opening in the first dielectric layer to expose a contact of the chip. A first metallization layer is deposited over the first dielectric layer and in the first opening, where a portion of the first metallization layer in the first opening has a flat top. A second dielectric layer is deposited over the first metallization layer and the first dielectric layer. A second metallization layer is deposited in a second opening in the second dielectric layer, where the second metallization layer does not have a flat top within the second opening.

Abstract: A display device according to an exemplary embodiment includes: a display panel for displaying an image; a support plate provided on one side of the display panel; and a heat sink layer provided below the support plate, wherein the heat sink layer includes a metal alloy having thermal conductivity that is equal to or greater than 150 W/mK and equal to or less than 340 W/mK, and an elastic modulus that is equal to or greater than 100 GPa and equal to or less than 140 GPa.

Abstract: A semiconductor packaging device includes a wiring board, a working chip, a heat-dissipating metal lid and a silicon thermal conductivity element. The working chip is mounted on the wiring board, and in-built with an working circuit therein. The silicon thermal conductivity element is thermally coupled to the working chip and the heat-dissipating metal lid, and is electrically isolated from the working circuit and the wiring board.

Abstract: A high-frequency module includes a substrate having a mounting surface, a laminated component disposed on the mounting surface, and a wiring, in which the laminated component includes a lower stage component, and an upper stage component disposed on the lower stage component, the lower stage component includes a lower surface 31 facing the mounting surface, an upper surface facing the lower surface 31 back to back, and a connection terminal 33 provided on the lower surface 31, the upper stage component includes a lower surface 41 facing the upper surface, and a connection terminal 43 provided on the lower surface 41, and the wiring is provided on the upper surface, and is connected with the connection terminal 43.

Abstract: A magnetic substance detection sensor includes a support substrate, a semiconductor chip provided on the support substrate and having a magnetic field detection element, a permanent magnet provided on the support substrate, and a resin encapsulation layer covering the semiconductor chip and the permanent magnet. The resin encapsulation layer has a first resin layer exposing the permanent magnet and covering the semiconductor chip, and a second resin layer continuously covering the permanent magnet and the first resin layer, and stress caused by curing contraction of the second resin layer is smaller than that of the first resin layer.

Abstract: Examples of an electronic package include a package assembly. The package assembly can include a substrate having a first substrate surface that includes a conductive layer attached to the first substrate surface. The package assembly includes a die communicatively coupled to the conductive layer and a contact block that includes a first contact surface on one end of the contact block, a second contact surface on an opposing side of the contact block, and a contact block wall extended therebetween. The contact block can include a conductive material. The first contact surface can be coupled to the package assembly with a joint extended partially up the contact block wall. The electronic package can further include an overmold covering portions of the substrate, conductive layer, and die. The second contact surface of the contact block can be exposed through the overmold.

Abstract: A method of forming a semiconductor package includes attaching a thermal conductivity layer to a chip. The chip has a first surface and a second surface. The thermal conductivity layer is attached to the first surface of the chip. The thermal conductivity layer provides a path through which heat generated from the chip is dissipated to the ambient. A substrate is attached to the second surface of the chip after attaching the thermal conductivity layer to the chip. A molding compound is formed to encapsulate the chip and the thermal conductivity layer.

Abstract: A method and structure for providing improved thermal management in multichip and package on package (PoP) applications. A first substrate attached to a second smaller substrate wherein the second substrate is encircled by a heat ring attached to the first substrate, the heat ring comprising heat conducting materials and efficient heat dissipating geometries. The first substrate comprises a heat generating chip and the second substrate comprises a heat sensitive chip. A method is presented providing the assembled structure with increased heat dissipation away from the heat sensitive chip.

Abstract: An electronic package includes an integrated circuit chip mounted to a support plate and encapsulated by an encapsulating body. The package includes at least one weakening deep perforation. The perforation is formed in either the support plate or the encapsulating body, and functions to reduce a resistance of the package to bending stresses perpendicular to the support plate.

Abstract: Provided are a thin circuit device with show-through of thin metal wires prevented and a method of manufacturing the circuit device. A circuit device mainly includes: a substrate including a first substrate and second substrates; pads formed respectively on upper surfaces of the second substrates; a semiconductor element fixed on an upper surface of the first substrate; thin metal wires each connecting the semiconductor elements and a corresponding one of the pads; and a sealing resin with which the semiconductor element and the thin metal wires are covered, and which thereby seals the circuit device with the semiconductor element and the thin metal wires disposed therein. Furthermore, filler particles located in the uppermost portion of the sealing resin are covered with a resin material constituting the sealing resin.

Abstract: Provided is a semiconductor device capable of reducing a temperature-dependent variation of a current sense ratio and accurately detecting current In the semiconductor device, at least one of an impurity concentration and a thickness of each semiconductor layer is adjusted such that a value calculated by a following equation is less than a predetermined value: [ ? i = 1 n ? ( R Mi × k Mi ) - ? i = 1 n ? ( R Si × k Si ) ] / ? i = 1 n ? ( R Mi × k Mi ) where a temperature-dependent resistance changing rate of an i-th semiconductor layer (i=1 to n) of the main element domain is RMi; a resistance ratio of the i-th semiconductor layer of the main element domain relative to the entire main element domain is kMi; a temperature-dependent resistance changing rate of the i-th semiconductor layer of the sense element domain is RSi; and a resistance ratio of the i-th semiconductor layer of the sense element domain to the entire sense element domain is kSi.

Abstract: A method for producing a component and device including a component is disclosed. A basic substrate having paper as substrate material is provided, at least one integrated circuit is applied to the basic substrate, the at least one integrated circuit applied on the basic substrate is enveloped with an encapsulant, and at least parts of the basic substrate are removed from the at least one enveloped integrated circuit.

Abstract: Provided is a semiconductor device capable of reducing a temperature-dependent variation of a current sense ratio and accurately detecting current. In the semiconductor device, at least one of an impurity concentration and a thickness of each semiconductor layer is adjusted such that a value calculated by a following equation is less than a predetermined value: [ ? i = 1 n ? ( R Mi × k Mi ) - ? i = 1 n ? ( R Si × k Si ) ] / ? i = 1 n ? ( R Mi × k Mi ) where a temperature-dependent resistance changing rate of an i-th semiconductor layer (i=1 to n) of the main element domain is RMi; a resistance ratio of the i-th semiconductor layer of the main element domain relative to the entire main element domain is kMi; a temperature-dependent resistance changing rate of the i-th semiconductor layer of the sense element domain is RSi; and a resistance ratio of the i-th semiconductor layer of the sense element domain to the entire sense element domain is kSi.

Abstract: A package includes a die, an encapsulant, and a capacitor. The package has a package first side and a package second side. The die has a die first side corresponding to the package first side, and has a die second side corresponding to the package second side. The die first side is opposite the die second side. The encapsulant surrounds the die. The capacitor includes a first plate and a second plate in the encapsulant, and opposing surfaces of the first plate and the second plate extend in a direction from the package first side to the package second side. The external conductive connectors are attached to at least one of the package first side and the package second side.

Abstract: A heat spreader frame is provided including: heat spreaders having upper surfaces; a peripheral frame surrounding the heat spreaders; spreaders, the peripheral frame having stand-off legs; tie bars having upper surfaces and a pin identifier at an end portion of the tie bars, the heat spreaders connected to one another and to the peripheral frame by the tie bars, the width of the stand-off legs wider than widths of the tie bars; at least portions of the upper surfaces of the tie bars being thinned to reduce heights of the tie bars; the upper surfaces of the heat spreader in an elevated position supported by the peripheral frame; and the heat spreaders and the tie bars covered by an package molding compound exposing the upper surface of the heat spreaders and one surface of the pin identifier coplanar to the upper surfaces of the heat spreaders.

Abstract: A radiation detector made of High Purity Germanium (HPGe) has been specially machined to be this invented multilayer Inter-Coaxial configuration. With this special configuration, extra large volume HPGe detectors of diameters to be 6 inches, 9 inches, and even 12 inches, can be produced with current achievable HPGe crystal purity and quality, in which the entire detector crystal will be depleted and properly over biased for effective photo-induced signal collection with just less than 5000V bias applied. This invention makes extra large efficiency of 200%, 300%, and maybe even higher than 500% possible with HPGe gamma ray detectors with reasonable great resolution performances procurable based on current HPGe crystal supply capability. The invention could also be applied to any other kind of semiconductor materials if any of them could be purified enough for this application in the future.

Abstract: An integrated heat spreader (IHS) lid over a semiconductor die connected to a substrate forms a cavity. A bead of foaming material may be placed within the IHS cavity. During an IHS cure and reflow process the foaming material will expand and fill the IHS cavity and the foam's shape conforms to the various surface features present, encapsulating a thermal interface material (TIM) material, and increasing contact area of the foam sealant.

Abstract: A thermally enhanced expanded wafer level ball grid array package. The expanded wafer level ball grid array package includes an integrated thermally conductive heat dissipater. In one embodiment the heat dissipater is positioned in close proximity to a non-active face of a die and is separated from the non-active face by a thermal interface material. In another embodiment the heat dissipater includes legs that displace the heat dissipater a short distance from the non-active die face, with the intervening space occupied by encapsulation material. In yet another embodiment, the thermal interface material exists between the non-active die face and the heat dissipater, but extends beyond the edge of the semiconductor die to also cover a portion of the encapsulation material. Methods for making the various embodiments of the expanded wafer level ball grid array package are also shown.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a peripheral lead having a peripheral contact layer surrounding the peripheral lead with a non-horizontal side exposed from the peripheral contact layer; forming an inner lead and a paddle non-planar with the peripheral lead; mounting an integrated circuit to the paddle; and forming an encapsulation covering the integrated circuit and exposing the inner lead, the paddle, and the non-horizontal side.

Abstract: A semiconductor housing package may be provided. The semiconductor housing package may include a mold layer, a housing chip, a redistribution structure, and a housing node. The mold layer may surround and partially expose the housing chip. The redistribution structure may be electrically connected to the housing chip and may be disposed on the mold layer. The housing node may be in contact with the redistribution structures. The semiconductor housing package may be disposed on a semiconductor base package and may constitute a semiconductor package structure along with the semiconductor base package. The semiconductor package structure may be disposed on a processor-based system.

Abstract: One embodiment of the present disclosure provides an apparatus comprising a flex circuit substrate having a core, a first solder mask and first traces disposed on the core on a first side of the flex circuit substrate, and a second solder mask and second traces disposed on the core on a second side of the flex circuit substrate. The first side is opposite to the second side. The apparatus further includes vias formed through the core to electrically couple the first traces to the second traces, and a stiffening structure coupled to the first side of the flex circuit substrate to increase structural rigidity of the flex circuit substrate. The stiffening structure provides structural, support to allow attachment of an integrated circuit die to the first side of the flex circuit substrate.

Abstract: A semiconductor apparatus includes a first stacked body including a first radiator plate, a first insulating layer, a first conductive layer and a first semiconductor element in this order; a second stacked body including a second radiator plate, a second insulating layer, a second conductive layer and a second semiconductor element in this order and configured to be made of a semiconductor material different from that of the first semiconductor element; and a connecting part configured to electrically connect the first conductive layer and the second conductive layer, wherein the first stacked body and the second stacked body are thermally insulated.

Abstract: A system of mold locks (28, 30) is formed on a heatsink (2) of a packaged semiconductor to prevent/mitigate delamination. The mold locks (4, 12) anchor a plastic mold compound (34) that forms the protective cover for the packaged semiconductor die. The mold locks (4, 12) are miniaturized to allow the positioning of them within the flag portion of the heatsink (2) and leadframe (24) such that a semiconductor die can be anchored above the mold locks (4, 12) formed within the flag portion of the heatsink/lead frame (2, 24). The miniaturized size of the said moldlocks (4, 12 do not detract from the purpose of the die attach solder (36).

Abstract: The present invention provide a heat dissipation structure on the active surface of the die to increase the performance of the heat conduction in longitude direction of the semiconductor package device, so that the heat dissipating performance can be improved when the semiconductor package device is associated with the exterior heat dissipation mechanism.

Abstract: A semiconductor package, containing two or more stacked IC devices attached to a substrate. Each of the IC devices has a plurality of electrical contact regions which are connected to the substrate by means of electrical connections.

Abstract: An interposer includes a substrate, a conductive structure configured to contact the back side of a semiconductor device and contact pads. The interposer may include first and second sets of contact pads carried by the substrate. The interposer may also include conductive traces carried by the substrate to electrically connect corresponding contact pads of the first and second sets. The receptacles, which may be formed in a surface of the substrate and expose contacts of the second set, may be configured to at least partially receive conductive structures that are secured to the contact pads of the second set. Thus, the interposer may be useful in providing semiconductor device assemblies and packages of reduced height or profile. Such assemblies and packages are also described, as are multi-chip modules including such assemblies or packages.

Abstract: A semiconductor package and related methods are described. In one embodiment, the package includes a die pad, multiple leads, a chip, a package body, and a protective layer. The die pad includes an upper sloped portion, a lower sloped portion, and a peripheral edge region defining a cavity with a cavity bottom. Each lead includes an upper sloped portion and a lower sloped portion. The chip is disposed on the cavity bottom and is coupled to the leads. The package body is formed over the chip and the leads, substantially fills the cavity, and substantially covers the upper sloped portions of the die pad and the leads. The lower sloped portions of the die pad and the leads at least partially extend outwardly from a lower surface of the package body. The protective layer substantially covers the lower sloped portion and the lower surface of at least one lead.

Abstract: A circuit device in which highly reliable sealing with a resin can be achieved is provided. A semiconductor chip is provided on one surface of an insulating resin film and a conductive layer that is electrically connected to the semiconductor chip is provided on another surface of the insulating resin film. A solder ball (electrode) for the connection to a circuit board is provided on the conductive layer. An insulating resin layer is further provided between the conductive layer and the circuit board to embed the electrode therein. In this manner, the circuit device is formed. A side face of the semiconductor chip is covered with the insulating resin film.

Abstract: An integrated circuit module package includes a lead frame having a recessed area. A semiconductor die containing active electrical components is attached to the recessed area of the lead frame. An integrated passive device containing passive electrical components is vertically stacked with, and electrically coupled to, the semiconductor die. An optional heat sink is attached to the integrated passive device. The integrated passive device is connected to the lead frame by conductors to electrically couple the integrated passive device and the semiconductor die to circuitry external to the integrated circuit module package. A cap is then attached to the heat sink or the integrated passive device to protect the semiconductor die and the integrated passive device. The integrated circuit module package dissipates heat from the semiconductor die through the lead frame, and dissipates heat from the integrated passive device through the cap and optional heat sink.

Abstract: An assembly of microelectronic devices and method for forming an assembly of microelectronic devices. In one embodiment, the method includes positioning a first packaged microelectronic device adjacent to a support member having support member circuitry, with the first packaged microelectronic device having a first microelectronic die at least partially encased in a first encapsulant to define a first package configuration. The method can further include electrically connecting the first packaged microelectronic device to a first portion of the support member circuitry and positioning at least proximate to the first packaged microelectronic device a second packaged microelectronic device having a second microelectronic die at least partially encased in a second encapsulant to define a second package configuration different than the first package configuration. The first packaged microelectronic device can be positioned between the support member and the second packaged microelectronic device.