Auxiliary Members In Containers Characterized By Their Shape, E.g., Pistons (epo) Patents (Class 257/E23.09)
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Patent number: 11973004Abstract: Described is a multi-chip module that may include a Redistribution Layer (RDL) substrate having Integrated Circuit (IC) dies mounted to a first surface of the RDL substrate. A second plurality of IC dies may be mounted to an opposite second surface. A plurality of sockets can be mounted upon the second plurality of IC dies and a cold plate then mounted to the first plurality of IC dies. The mounting structure may include socket frames coupled to the plurality of sockets.Type: GrantFiled: September 19, 2019Date of Patent: April 30, 2024Assignee: Tesla, Inc.Inventors: Robert Yinan Cao, Mitchell Heschke, Mengzhi Pang, Shishuang Sun, Vijaykumar Krithivasan
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Patent number: 11955402Abstract: A power semiconductor component is specified, having a power semiconductor device arranged within a housing, wherein a heat sink is exposed on a first surface of the housing; a wiring substrate which receives the housing with the power semiconductor device and which has a first main surface and a second main surface. A heat dissipation region with increased thermal conductivity is arranged on the second main surface. The housing is arranged on the wiring substrate in such a way that the heat sink is connected to the heat dissipation region via a solder layer. A number of spacers which are arranged between the heat sink and the heat dissipation region are embedded in the solder layer. Furthermore, a method for producing a power semiconductor component is specified.Type: GrantFiled: October 6, 2020Date of Patent: April 9, 2024Assignee: Vitesco Technologies GbmHInventors: Christina Quest-Matt, Detlev Bagung, Daniela Wolf
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Patent number: 11942495Abstract: A semiconductor device includes a semiconductor chip, a circuit board, a heat releasing plate, an adhesive member, and a conductive member. The circuit board transmits a signal of the semiconductor chip. The heat releasing plate has the semiconductor chip disposed thereon, and has an opening in a region on the outer side of a semiconductor chip placement region that is a region in which the semiconductor chip is disposed. The adhesive member is disposed in a region on the outer side of the opening on a different surface of the heat releasing plate from the surface on which the semiconductor chip is disposed, and bonds the circuit board and the heat releasing plate to each other. The conductive member connects the semiconductor chip and the circuit board to each other via the opening.Type: GrantFiled: June 21, 2019Date of Patent: March 26, 2024Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Daisuke Chino, Hiroyuki Shigeta, Shigekazu Ishii, Koyo Hosokawa, Hirohisa Yasukawa, Mitsuhito Kanatake, Kosuke Hareyama, Yutaka Ootaki, Kiyohisa Sakai, Atsushi Tsukada, Hirotaka Kobayashi, Ninao Sato, Yuki Yamane
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Patent number: 11924989Abstract: A fixing device includes a circuit board, a first cover, a reinforcing piece, and a double-layer chip. The circuit board has a first surface and a second surface opposite to each other. The first cover is disposed adjacent to the first surface and has a first bump which has a first abutting surface facing the first surface. The reinforcing piece is located on the first surface and adjacent to the first bump. The double-layer chip has an upper layer and a lower layer which are electrically connected. An upper surface of the upper layer and a lower surface of the lower layer are respectively located on opposite sides of the double-layer chip, and an area of the upper surface is smaller than an area of the lower surface. The lower layer of the double-layer chip and the second surface of the circuit board are electrically connected.Type: GrantFiled: September 12, 2022Date of Patent: March 5, 2024Assignees: Inventec (Pudong) Technology Corporation, INVENTEC CORPORATIONInventor: Ming Hung Shih
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Patent number: 11901309Abstract: In general aspect, a semiconductor device package can include a substrate and a semiconductor die disposed on and coupled with the substrate. The semiconductor device package can further include a leadframe having an indentation defined therein, at least a portion of the indentation being disposed on and coupled with the semiconductor die via a conductive adhesive.Type: GrantFiled: November 12, 2019Date of Patent: February 13, 2024Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Seungwon Im, Oseob Jeon
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Patent number: 11876345Abstract: Techniques and systems for a semiconductor laser, namely a grating-coupled surface-emitting (GCSE) comb laser, having thermal management for facilitating dissipation of heat, integrated thereon. The thermal management is structured in manner that prevents deformation or damage to the GCSE laser chips included in the semiconductor laser implementation. The disclosed thermal management elements integrated in the laser can include: heat sinks; support bars; solder joints; thermal interface material (TIM); silicon vias (TSV); and terminal conductive sheets. Support bars, for example, having the GCSE laser chip positioned between the bars and having a height that is higher than a thickness of the GCSE laser chip. Accordingly, the heat sink can be placed on top of the support bars such that heat is dissipated from the GCSE laser chip, and the heat sink is separated from directed contact with the GCSE laser chip due to the height of the support bars.Type: GrantFiled: September 8, 2020Date of Patent: January 16, 2024Assignee: Hewlett Packard Enterprise Development LPInventors: Di Liang, Chih C. Shih, Kevin B. Leigh, Geza Kurczveil, Marco Fiorentino
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Patent number: 11876032Abstract: A bond layer including at least one metal region in a plan view is disposed on a surface layer portion of a substrate formed from a semiconductor. A semiconductor element is disposed on the bond layer and includes a first transistor disposed on a first metal region that is a metal region as the at least one metal region of the bond layer and including a collector layer electrically coupled to the first metal region, a base layer disposed on the collector layer, and an emitter layer disposed on the base layer. A first emitter electrode is disposed on the emitter layer of the first transistor. A first conductor protrusion is disposed on the first emitter electrode. The thermal conductivity of the semiconductor material of the surface layer portion is higher than that of each of the collector layer, the base layer, and the emitter layer of the first transistor.Type: GrantFiled: October 18, 2021Date of Patent: January 16, 2024Assignee: Murata Manufacturing Co., Ltd.Inventors: Shinnosuke Takahashi, Masayuki Aoike, Masatoshi Hase, Fumio Harima
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Patent number: 11869824Abstract: A thermal interface structure may be formed comprising a thermally conductive substrate having a first surface and an opposing second surface, a first liquid metal layer on the first surface of the thermally conductive substrate, and a second liquid metal layer on the second surface of the thermally conductive substrate. The thermal interface structure may be used in an integrated circuit assembly or package between at least one integrated circuit device and a heat dissipation device.Type: GrantFiled: November 4, 2019Date of Patent: January 9, 2024Assignee: Intel CorporationInventors: Kyle J. Arrington, Aaron McCann, Kelly Lofgreen, Elah Bozorg-Grayeli, Aravindha Antoniswamy, Joseph B. Petrini
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Patent number: 11862603Abstract: A semiconductor package includes a package substrate; a plurality of lower chip structures on the package substrate; an upper chip structure on the plurality of lower chip structures and covering portions of upper surfaces of the plurality of lower chip structures; a non-conductive adhesive layer on a lower surface of the upper chip structure and receiving upper portions of the plurality of lower chip structures; and a molded member on the plurality of lower chip structures and the upper chip structure.Type: GrantFiled: August 25, 2020Date of Patent: January 2, 2024Inventors: Taewook Kim, Jongho Lee, Jeongjoon Oh, Hyeon Hwang
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Patent number: 11856734Abstract: A set of electronic package elements intended to be mounted on an electronic board having a component to be cooled including: a chassis, a heatsink fixed by a retaining piece inside the chassis, a cover configured to be fixed on the chassis so as to retain the electronic board in the package. The heatsink is configured to be fixed on the electronic board while maintaining a predetermined distance between a lower face of the heatsink and the component. The cover is configured to be able to be fixed by a fixing point to the heatsink. The retaining piece is connected to the heatsink so as to allow the heatsink a translational movement relative to the chassis in three orthogonal directions.Type: GrantFiled: July 7, 2021Date of Patent: December 26, 2023Assignee: CONTINENTAL AUTOMOTIVE TECHNOLOGIES GMBHInventors: Jean-Philippe Bekaert, Gilles Le Roy
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Patent number: 11774190Abstract: Pierced thermal interface constructions including a thermal interface material (TIM) structure comprising: a TIM sheet comprising a plurality of piercings, where each of the plurality of piercings comprises a cavity and displaced material, and where the displaced material from each of the plurality of piercings protrudes away from the TIM sheet.Type: GrantFiled: April 14, 2020Date of Patent: October 3, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Mark K. Hoffmeyer
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Patent number: 11769709Abstract: A miniaturized oscillating heat pipe (OHP) embedded within an integrated circuit (IC) is provided. The miniaturized oscillating heat pipe (OHP) integrally formed within an integrated circuit (IC) is fabricated to form a monolithic IC device using silicon (or similar future semiconductors) fabrication techniques. The OHP is operable to transfer high local heat fluxes within the IC device to more accessible locations on the IC device for heat rejection to an available heat sink.Type: GrantFiled: December 4, 2017Date of Patent: September 26, 2023Assignee: THERMAVANT TECHNOLOGIES, LLCInventors: Christopher D. Smoot, Joe Boswell, Corey Wilson
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Patent number: 11756860Abstract: Embodiments disclosed herein include semiconductor dies and methods of forming such dies. In an embodiment, the semiconductor die comprises a semiconductor substrate, an active device layer in the semiconductor substrate, where the active device layer comprises one or more transistors, an interconnect layer over a first surface of the active device layer, a first bonding layer over a surface of the semiconductor substrate, a second bonding layer secured to the first bonding layer, and a heat spreader attached to the second bonding layer.Type: GrantFiled: July 25, 2019Date of Patent: September 12, 2023Assignee: Intel CorporationInventors: Shrenik Kothari, Chandra Mohan Jha, Weihua Tang, Robert Sankman, Xavier Brun, Pooya Tadayon
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Patent number: 11683911Abstract: A sensing device for a vehicular sensing system includes a housing having a front housing portion and a metallic rear housing portion. A first printed circuit board and a second printed circuit board are disposed in the housing. The second printed circuit board is electrically connected to the first printed circuit board, which has an electrical connector for electrically connecting the sensing device to a vehicle wire harness. The second printed circuit board has circuitry thereat, with the circuitry generating heat when the sensing device is operating. The rear housing portion comprises a thermally conductive element that extends through an aperture of the first printed circuit board and is thermally coupled at the second printed circuit board. The thermally conductive element conducts heat generated by the circuitry of the second printed circuit board to the rear housing portion to dissipate the heat from the sensing device.Type: GrantFiled: October 24, 2019Date of Patent: June 20, 2023Assignee: Magna Electronics Inc.Inventor: Wilhelm Johann Wolfgang Wöhlte
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Patent number: 11658691Abstract: To achieve miniaturization, a high-frequency module includes a mounting substrate, a power amplifier, and an electronic component. The mounting substrate has a first main surface and a second main surface on opposite sides. The power amplifier is arranged on a mounting substrate. The power amplifier has a driver stage amplifier and an output stage amplifier. The driver stage amplifier is arranged on the second main surface of the mounting substrate. The output stage amplifier is arranged on the first main surface of the mounting substrate. The electronic component is arranged on the first main surface of the mounting substrate. The electronic component overlaps the driver stage amplifier in a plan view from a thickness direction of the mounting substrate.Type: GrantFiled: March 3, 2022Date of Patent: May 23, 2023Assignee: MURATA MANUFACTURING CO., LTD.Inventor: Takayuki Shinozaki
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Patent number: 11647586Abstract: A substrate layered structure including a first circuit board; a second circuit board overlapping the first circuit board; and interposer blocks interposed between the first circuit board and the second circuit board and spaced apart from each other. Further, each corresponding interposer block includes a dielectric block body; a plurality of signal via holes passing through the dielectric block body and transferring signals between the first circuit board and the second circuit board; and a plurality of signal pads arranged at first ends of the signal via holes and connected to the first circuit board and arranged at second ends of the signal via holes and connected to the second circuit board.Type: GrantFiled: April 2, 2021Date of Patent: May 9, 2023Assignee: LG ELECTRONICS INC.Inventors: Sanggeun Kim, Jungtae Seo, Kipoung Kim, Inkyu Park, Youngjik Lee, Youngkweon Kim
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Patent number: 11626344Abstract: Provided are a package structure and a method of forming the same. The package structure includes a first die, a second die group, an interposer, an underfill layer, a thermal interface material (TIM), and an adhesive pattern. The first die and the second die group are disposed side by side on the interposer. The underfill layer is disposed between the first die and the second die group. The adhesive pattern at least overlay the underfill layer between the first die and the second die group. The TIM has a bottom surface being in direct contact with the first die, the second die group, and the adhesive pattern. The adhesive pattern separates the underfill layer from the TIM.Type: GrantFiled: January 21, 2022Date of Patent: April 11, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hao Chen, Chin-Fu Kao, Li-Hui Cheng, Szu-Wei Lu, Chih-Chien Pan
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Patent number: 11622475Abstract: A power module includes a power source module and a metallic heat-dissipation substrate. The power source module has an input pin and an output pin soldered on and electrically connected with a system board and includes a printed circuit board. The printed circuit board has a first surface and a second surface. At least a heat-generating component is disposed on the second surface. The metallic heat-dissipation substrate has a first surface and a second surface opposite to each other. The first surface has at least a fixing position and at least a heat-dissipating position. The fixing position is directly or indirectly connected with the second surface. A gap accumulated by tolerances is existed between the heat-dissipating position and the heat-generating component. A gap-filling material is filled into the gap. The second surface and the system board are soldered with each other. Therefore, the heat-dissipation efficiency is enhanced.Type: GrantFiled: July 1, 2021Date of Patent: April 4, 2023Assignee: DELTA ELECTRONICS, INC.Inventors: Da Jin, Shaojun Chen, Yahong Xiong
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Patent number: 11616019Abstract: A semiconductor assembly is described that includes a substrate having top and bottom sides. An integrated circuit die coupled to the substrate includes first and second distinct sets of ground pads. In some embodiments, the first and second sets of ground pads are configured to have distinct ground return paths to a host system. In further embodiments, one of the ground return paths may include a metal plate coupled between ground contacts on the top side of the substrate and ground contacts on a printed circuit board of the host system.Type: GrantFiled: December 21, 2020Date of Patent: March 28, 2023Assignee: NVIDIA Corp.Inventors: Jacky Qiu, Martin Ding, Jerry Zhou, Minto Zheng
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Patent number: 11600548Abstract: According to an aspect of the disclosure, an example microelectronic device assembly includes a substrate, a microelectronic element electrically connected to the substrate, a stiffener element overlying the substrate, and a heat distribution device overlying the rear surface of the microelectronic element. The stiffener element may extend around the microelectronic element. The stiffener element may include a first material that has a first coefficient of thermal expansion (“CTE”). A surface of the stiffener element may face toward the heat distribution device. The heat distribution device may include a second material that has a second CTE. The first material may be different than the second material. The first CTE of the first material of the stiffener element may be greater than the second CTE of the second material of the heat distribution device.Type: GrantFiled: May 28, 2021Date of Patent: March 7, 2023Assignee: Google LLCInventors: Woon-Seong Kwon, Yuan Li, Zhi Yang
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Patent number: 11599168Abstract: A cooling system for cooling components in an information handling system contained in a portable chassis comprises a die plate for receiving heat from a component, a heat pipe for transferring heat from the die plate to a single heat exchanger, a fan for generating an airflow across the heat exchanger and a thermal battery. The heat pipe comprises at least one curvature and the thermal battery is coupled to the die plate and has a length and a width such that the thermal battery is in contact with the heat pipe from the die plate to a point past the at least one curvature. The thermal battery may be formed from a thermally conductive material, be a vapor chamber or otherwise facilitate heat transfer to a heat pipe from the die plate to a point past the curvature for improved cooling.Type: GrantFiled: July 27, 2021Date of Patent: March 7, 2023Assignee: Dell Products L.P.Inventors: Allen B. McKittrick, Pomin Shih, Travis North
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Patent number: 11602076Abstract: The disclosure provides a liquid-cooling heat dissipation device. The liquid-cooling heat dissipation device is configured to be in thermal contact with an expansion card. The liquid-cooling heat dissipation device includes a base plate, a thermally-conductive component and a heat exchanger. The base plate is configured to be mounted on the expansion card. The thermally-conductive component is mounted on the base plate. The thermally-conductive component and the base plate together form a liquid chamber therebetween. The heat exchanger is mounted on the base plate and connected to the liquid chamber.Type: GrantFiled: January 29, 2020Date of Patent: March 7, 2023Assignee: COOLER MASTER CO., LTD.Inventor: Tung-Yang Shieh
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Patent number: 11582888Abstract: Described herein is a hybrid cooling device and a cooling method that use a combination of phase change cooling and air cooling. The hybrid cooling device includes a closed loop two phase system, one or more fans, and an assembly clamp. The two phase system further includes a cold plate, an integrated channel, and a radiator, and a pressure sensor. The cold plate can include phase change fluid for extracting heat from electronics on a printed circuit board sandwiched between the cold plate and the assembly clamp. The one or more fans can be used to create airflows for cooling both the cold plate and the radiator. The pressure sensor can be used to control the operation of the hybrid cooling device, which can be deployed in different system environments and server configurations.Type: GrantFiled: March 25, 2021Date of Patent: February 14, 2023Assignee: BAIDU USA LLCInventor: Tianyi Gao
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Patent number: 11563360Abstract: A housing for an electric machine includes a cooling device arranged on the periphery of a support plate, the cooling device contacts a heat-conducting ring connected to the housing, and the support plate as well as components arranged thereon have vibration damping and an electric insulation to provide advantageous structural conditions such that an advantageous cooling effect is achieved, and regions within the cooling device can be provided for fitting elements of the support plate.Type: GrantFiled: December 7, 2017Date of Patent: January 24, 2023Assignee: MELECS EWS GMBHInventors: Leopold Hellinger, Gerhard Neumann, Manfred Lex
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Patent number: 11486661Abstract: A thermal bridge includes an upper bridge assembly including upper plates arranged in an upper plate stack and a lower bridge assembly including lower plates arranged in a lower plate stack. The thermal bridge includes upper spring elements extending from upper plates having upper mating interfaces engaging lower plates to bias the upper plates in a first biasing direction generally away from the lower bridge assembly. The thermal bridge includes lower spring elements extending from lower plates having lower mating interfaces engaging upper plates to bias the lower plates in a second biasing direction generally away from the upper bridge assembly. A bridge frame having connecting elements extends through the upper plates and the lower plates to hold the upper plates in the upper plate stack and to hold the lower plates in the lower plate stack.Type: GrantFiled: May 28, 2020Date of Patent: November 1, 2022Assignee: TE CONNECTIVITY SOLUTIONS GmbHInventor: Leo Joseph Graham
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Patent number: 11469185Abstract: Semiconductor packages having support members are provided. Support members can mitigate damage to a semiconductor die mounted on a semiconductor package. In some embodiments, an arrangement of support packages can be formed at respective locations of a frame layer that serves as a stiffener for the semiconductor package. Each support member in the arrangement can be formed from a same material of the frame layer or a different material. In some embodiments, a support member can be mounted or otherwise coupled to an exposed surface of the frame layer. In addition or in other embodiments, a support member can be mounted on a surface that supports the semiconductor die. The arrangement of support members can include support members comprising a first material and/or other support members formed from respective materials. A support member can be formed from a metal, a metal alloy, a semiconductor, a polymer, a composite material, or a porous material.Type: GrantFiled: November 27, 2017Date of Patent: October 11, 2022Assignee: Intel CorporationInventors: Je-Young Chang, Shubhada H. Sahasrabudhe, Tannaz Harirchian
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Patent number: 11462520Abstract: The present invention provides a chip integration module, including a die, a passive device, and a connecting piece, where the die is provided with a die bonding portion, the passive device is provided with a passive device bonding portion, the die bonding portion of the die and the passive device bonding portion of the passive device are disposed opposite to each other, and the connecting piece is disposed between the die bonding portion and the passive device bonding portion and is connected to the die bonding portion and the passive device bonding portion. The chip integration module of the present invention achieves easy integration and has low costs. Moreover, a path connecting the die to the passive device becomes shorter, which can improve performance of the passive device. The present invention further discloses a chip package structure and a chip integration method.Type: GrantFiled: March 16, 2018Date of Patent: October 4, 2022Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: HuiLi Fu, Song Gao
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Patent number: 11454835Abstract: Disclosed are a light emission device including a magnetoactive element, a method of fabricating the same, and an electronic device including the light emission device. The disclosed light emission device may include a light emission layer; a first electrode and a second electrode spaced apart from each other on a first surface side of the light emission layer; and a magnetoactive fluid layer disposed on a second surface side of the light emission layer and having a plurality of nanostructures of which arrangement and distribution is configured to change according to application of a magnetic field. The light emitting properties of the light emission layer may be changed according to the arrangement and distribution of a plurality of nanostructures in the magnetoactive fluid layer. The plurality of nanostructures may include conductive nanowire and magnetic nanoparticle provided on the surfaces of the conductive nanowire.Type: GrantFiled: September 24, 2020Date of Patent: September 27, 2022Assignee: UNIVERSITY-INDUSTRY FOUNDATION (UIF), YONSEI UNIVERSITYInventors: Cheolmin Park, Soyeon Baek, Seung Won Lee
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Patent number: 11382230Abstract: An electronic apparatus includes a first circuit board, a second circuit board, one or more electronic components, an enclosure portion, and a second housing. The electronic components are mounted on at least one of opposing surfaces of the first circuit board and the second circuit board that oppose each other. The enclosure portion supports a surface of each of the first circuit board and the second circuit board to oppose each other with a predetermined gap therebetween. The enclosure portion encloses a gap space that includes the one or more electronic components within a space between the first circuit board and the second circuit board. The second housing accommodates the first circuit board, the second circuit board, and the enclosure portion. The enclosure portion contacts the housing.Type: GrantFiled: March 13, 2019Date of Patent: July 5, 2022Assignee: KYOCERA CorporationInventors: Masaki Fujiwara, Hiroshi Nakao
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Patent number: 9258924Abstract: An electronic ballast is provided with an elongated housing; a heat sink module disposed in the housing and including a channel extending from one end to an other end; a plurality of power semiconductor modules disposed on both sides of the heat sink module respectively; an inlet assembly disposed at one end of the heat sink module proximate to a first panel at one end of the housing; an outlet assembly disposed at the other end of the heat sink module proximate to a second panel at an other end of the housing; and a fan disposed between the other end of the heat sink module and the second panel. Only a small portion of heat is dissipated by surface areas of the housing. Thus, the housing can be made compact to save space.Type: GrantFiled: September 6, 2013Date of Patent: February 9, 2016Assignee: SHENZHEN LONGOOD INTELLIGENT ELECTRIC CO., LTD.Inventors: Wei Wu, Jianlin Huang, Qingsong Chu
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Patent number: 8941094Abstract: Methods for adjusting and/or limiting the conductivity range of a nanotube fabric layer are disclosed. In some aspects, the conductivity of a nanotube fabric layer is adjusted by functionalizing the nanotube elements within the fabric layer via wet chemistry techniques. In some aspects, the conductivity of a nanotube fabric layer is adjusted by functionalizing the nanotube elements within the fabric layer via plasma treatment. In some aspects, the conductivity of a nanotube fabric layer is adjusted by functionalizing the nanotube elements within the fabric layer via CVD treatment. In some aspects, the conductivity of a nanotube fabric layer is adjusted by functionalizing the nanotube elements within the fabric layer via an inert ion gas implant.Type: GrantFiled: September 2, 2010Date of Patent: January 27, 2015Assignee: Nantero Inc.Inventors: C. Rinn Cleavelin, Thomas Rueckes, H. Montgomery Manning, Darlene Hamilton, Feng Gu
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Patent number: 8937383Abstract: The semiconductor package as well as a method for making it and using it is disclosed. The semiconductor package comprises a semiconductor chip having at least one heat-generating semiconductor device and a volumetrically expandable chamber disposed to sealingly surround the semiconductor chip, the volumetrically expandable chamber filled entirely with a non-electrically conductive liquid in contact with the semiconductor device and circulated within the volumetrically expandable chamber at least in part by the generated heat of the at least one semiconductor device to cool the at least one semiconductor device.Type: GrantFiled: October 23, 2013Date of Patent: January 20, 2015Assignee: The Boeing CompanyInventors: Andrew G. Laquer, Ernest E. Bunch
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Patent number: 8836110Abstract: A packaged semiconductor device includes a package substrate, an integrated circuit (IC) die mounted on the package substrate, and a heat spreader mounted on the package substrate. The heat spreader surrounds at least a portion of the IC die and includes a lid with a plurality of openings. An inner portion of the heat spreader includes a plurality of thermally conductive protrusions adjacent the die.Type: GrantFiled: August 31, 2012Date of Patent: September 16, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Sheila F. Chopin, Varughese Mathew
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Patent number: 8786082Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, at least two pads, a passivation layer, at least two under bump metallization (UBM) layers and at least two bumps. The pads are disposed adjacent to each other on the substrate along the first direction. The passivation layer covers the substrate and the peripheral upper surface of each pad to define an opening. Each of the openings defines an opening projection along the second direction. The opening projections are disposed adjacent to each other but not overlapping with each other. Furthermore, the first direction is perpendicular to the second direction. The UBM layers are disposed on the corresponding openings, and the bumps are respectively disposed on the corresponding UBM layers. With the above arrangements, the width of each bump of the semiconductor structure of the present invention could be widened without being limited by the bump pitch.Type: GrantFiled: November 7, 2012Date of Patent: July 22, 2014Assignee: Chipmos Technologies Inc.Inventor: Geng-Shin Shen
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Patent number: 8592971Abstract: The semiconductor package as well as a method for making it and using it is disclosed. The semiconductor package comprises a semiconductor chip having at least one heat-generating semiconductor device and a volumetrically expandable chamber disposed to sealingly surround the semiconductor chip, the volumetrically expandable chamber filled entirely with a non-electrically conductive liquid in contact with the semiconductor device and circulated within the volumetrically expandable chamber at least in part by the generated heat of the at least one semiconductor device to cool the at least one semiconductor device.Type: GrantFiled: December 15, 2009Date of Patent: November 26, 2013Assignee: The Boeing CompanyInventors: Andrew G. Laquer, Ernest E. Bunch
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Patent number: 8546935Abstract: The invention includes semiconductor packages having grooves within a semiconductor die backside; and includes semiconductor packages utilizing carbon nanostructures (such as, for example, carbon nanotubes) as thermally conductive interface materials. The invention also includes methods of cooling a semiconductor die in which coolant is forced through grooves in a backside of the die, and includes methods of making semiconductor packages.Type: GrantFiled: May 31, 2012Date of Patent: October 1, 2013Assignee: Micron Technology, Inc.Inventors: Chandra Mouli, Gurtej S. Sandhu
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Publication number: 20120299175Abstract: Systems and methods are disclosed for fabricating a semiconductor device by forming heat conducting nanowires on a first side of a wafer; and depositing semiconductor structures on a second side of the wafer.Type: ApplicationFiled: November 19, 2011Publication date: November 29, 2012Inventor: Bao Tran
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Publication number: 20110298131Abstract: A germanium semiconductor radiation detector contact made of yttrium metal. A thin (˜1000 ?) deposited layer of yttrium metal forms a thin hole-barrier and/or electron-barrier contact on both p- and n-type germanium semiconductor radiation detectors. Yttrium contacts provide a sufficiently high hole barrier to prevent measurable contact leakage current below ˜120 K. The yttrium contacts can be conveniently segmented into multiple electrically independent electrodes having inter-electrode resistances greater than 10 G?. Germanium semiconductor radiation detector diodes fabricated with yttrium contacts provide good gamma-ray spectroscopy data.Type: ApplicationFiled: May 20, 2011Publication date: December 8, 2011Inventors: Ethan Hull, Richard Pehl, Bruce Suttle, James Lathrop
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Patent number: 7728440Abstract: A semiconductor device includes: a semiconductor chip mounted on a mounting substrate; a first resin filling a gap between the chip and the substrate; a frame-shaped stiffener surrounding the chip; a first adhesive for bonding the stiffener to the substrate; a lid for covering the stiffener and an area surrounded by the stiffener; and a second resin filling a space between the stiffener and the chip. A thermal expansion coefficient of the second resin is smaller than that of the first resin. The first resin includes an underfill part filling a gap between the chip and the substrate and a fillet part extended from the chip region.Type: GrantFiled: January 23, 2004Date of Patent: June 1, 2010Assignee: NEC Electronics CorporationInventor: Hirokazu Honda
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Patent number: 7700943Abstract: An embodiment of the present invention is a technique to functionalize carbon nanotubes in situ. A carbon nanotube (NT) array is grown or deposited on a substrate. The NT array is functionalized in situ with a polymer by partial thermal degradation of the polymer to form a NT structure. The functionalization of the NT structure is characterized. The functionalized NT structure is processed according to the characterized functionalization.Type: GrantFiled: August 20, 2008Date of Patent: April 20, 2010Assignee: Intel CorporationInventors: Nachiket R. Raravikar, James C. Matayabas, Jr.
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Patent number: 7687901Abstract: Electrode plates acting as a heat sink are arranged to sandwich a power transistor and a diode. Electrode plates at their surfaces opposite cooling elements at a portion opposite power transistor and diode are formed to be smaller in thickness at a portion adjacent to power transistor and diode substantially at the center than at a periphery. Cooling elements are disposed geometrically along electrode plates to sandwich electrode plates.Type: GrantFiled: January 20, 2006Date of Patent: March 30, 2010Assignee: Toyota Jidosha Kabushiki KaishaInventor: Norifumi Furuta
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Patent number: 7656025Abstract: The semiconductor package as well as a method for making it and using it is disclosed. The semiconductor package comprises a semiconductor chip having at least one heat-generating semiconductor device and a volumetrically expandable chamber disposed to sealingly surround the semiconductor chip, the volumetrically expandable chamber filled entirely with a non-electrically conductive liquid in contact with the semiconductor device and circulated within the volumetrically expandable chamber at least in part by the generated heat of the at least one semiconductor device to cool the at least one semiconductor device.Type: GrantFiled: November 21, 2006Date of Patent: February 2, 2010Assignee: The Boeing CompanyInventors: Andrew G. Laquer, Ernest E. Bunch
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Patent number: 7633151Abstract: Various integrated circuit packages, lids therefor and methods of making the same are provided. In one aspect, a method of manufacturing is provided that includes providing an integrated circuit package lid that has a surface adapted to face towards an integrated circuit, and forming a wetting film on the surface. The wetting film has at least one void where the surface of the lid is exposed. The void inhibits bonding so that a stress reduction site is produced.Type: GrantFiled: March 16, 2007Date of Patent: December 15, 2009Assignee: Advanced Micro Devices, Inc.Inventors: Seah Sun Too, Jacquana Diep, Mohammad Khan
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Patent number: 7622314Abstract: A method of making a carbon nanotube structure includes forming a plurality of carbon nanotubes and contacting the carbon nanotubes with a polymer. A solid composition is formed from the carbon nanotubes and polymer and then shaped. For example, the solid composition can be shaped into an elongated structure such as a filament, wire, rope, cable, and the like. In at least some instances, at least some, or all, of the polymer is removed from the solid composition after it is shaped.Type: GrantFiled: May 5, 2006Date of Patent: November 24, 2009Assignee: Brother International CorporationInventor: Kangning Liang
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Patent number: 7608917Abstract: A power semiconductor module and an inverter apparatus in which a device or a joining part is not mechanically damaged even when the temperature in use becomes a high temperature in the range of 175 to 250° C., resulting in excellent reliability at high temperature retaining test and thermal cycling test. Low thermal expansion ceramic substrates are disposed above and below the device. A material having a coefficient of thermal expansion of 10 ppm/K or less is disposed between the ceramic substrates. In addition, an inorganic material having a coefficient of thermal expansion in the range of 2 to 6 ppm/K or less is disposed around the device.Type: GrantFiled: May 16, 2007Date of Patent: October 27, 2009Assignee: Hitachi, Ltd.Inventors: Ryoichi Kajiwara, Kazuhiro Suzuki, Toshiaki Ishii, Kazutoshi Itou
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Patent number: 7581583Abstract: A heat dissipating device includes a heat sink, and an adjusting member. The heat sink includes a base, and a plurality of fins formed on a top surface of the base. The adjusting member includes a mounting portion mounted to a side surface facing an airflow-generating source of the base, a first air-blocking portion connected to an upper portion of the mounting part, and a second air-blocking portion connected to a lower portion of the mounting part. Positions of the first air-blocking portion and the second air-blocking portion relative to the base are adjustable for adjusting distribution of an airflow on top and bottom sides of the base when the airflow flows through the heat dissipating device.Type: GrantFiled: September 15, 2006Date of Patent: September 1, 2009Assignee: Hon Hai Precision Industry Co., Ltd.Inventor: Zheng-Heng Sun
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Patent number: 7544542Abstract: Various method and apparatus for packaging an integrated circuit are provided. In one aspect, a method of packaging an integrated circuit is provided that includes coupling an integrated circuit to a substrate, mixing an adhesive with a plurality of particles, and coupling a lid to the substrate with the adhesive. At least a portion of the plurality of particles in the adhesive oppose compressive force from the lid to restrict rotation of the lid relative to the substrate.Type: GrantFiled: August 7, 2006Date of Patent: June 9, 2009Assignee: Advanced Micro Devices, Inc.Inventors: Seah Sun Too, Raj N. Master, Jacquana Diep, Mohammad Khan
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Patent number: 7488532Abstract: The present invention is to provide an adhesive resin composition for use in preparing an adhesive in the form of a film which is excellent in the adhesiveness at a low temperature and in the heat resistance, an adhesive in the form of a film comprising the adhesive resin composition, and a semiconductor device using the adhesive in the form of a film.Type: GrantFiled: April 13, 2004Date of Patent: February 10, 2009Assignee: Mitsui Chemicals, Inc.Inventors: Youichi Kodama, Hiroshi Maruyama, Isao Naruse
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Patent number: 7473607Abstract: A method of manufacturing a device includes doping a low voltage threshold area and a high voltage threshold area. Gate structures are formed over the low voltage threshold and high voltage threshold areas while protecting the gate structure over the low voltage threshold area. A silicidation process is performed over the high voltage threshold area while the gate structure over the low voltage threshold area remains protected. Siliciding includes depositing metal on the gate of the high voltage threshold area and annealing the metal, the metal is deposited either by CVD or sputtering followed by anneal to fully suicide the gate structure of the high voltage threshold area. The metal, preferably cobalt or nickel is deposited to a thickness of approximately 500 ?, annealed for about 3 minutes at about 400° C.Type: GrantFiled: July 6, 2005Date of Patent: January 6, 2009Assignee: International Business Machines CorporationInventors: Xiangdong Chen, Rajesh Rengarajan
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Patent number: 7170165Abstract: An assembly includes a circuit board with a ball grid array device attached to a first side of the circuit board. A brace surrounding the ball grid array device has a series of mounting holes and a series of members extending between the mounting holes. The brace is removably secured to the first side of the circuit board at the mounting holes.Type: GrantFiled: February 2, 2005Date of Patent: January 30, 2007Assignee: Agilent Technologies, Inc.Inventors: Thomas E. Berto, Anirudh N. Vaze