Abstract: A semiconductor module includes: a board; a semiconductor device disposed on the board, a first surface of the semiconductor device closer to the board being connected to the board; an interconnection layer to which a second surface of the semiconductor device opposite to the first surface is connected, and which has a recess portion on an opposite surface to a surface closer to the semiconductor device; a first metal film disposed in the recess portion of the interconnection layer via a bonding film, and that is electrically connected to the interconnection layer; an insulating layer disposed on the first metal film; and a heat transfer plate disposed on the insulating layer.

Abstract: The present disclosure provides an OLED packaging structure and a manufacturing method thereof, and a display device comprising the packaging structure. The OLED packaging structure comprises a first substrate, an OLED disposed on the surface of the first substrate, and a packaging layer covering the OLED, wherein the packaging layer comprises a heat dissipation layer.

Abstract: The invention is to provide a semiconductor apparatus configured to position a semiconductor device reliably and easily without having a protruding portion formed in the bottom surface of the semiconductor device in the semiconductor apparatus. A semiconductor apparatus is fabricated by attaching a semiconductor device of a surface mount package type and a wiring member to a heat sink. A fitting portion in which the semiconductor device is fit is provided to the wiring member, so that the semiconductor device is positioned by fitting the semiconductor device into the fitting portion provided to the wiring member. According to the semiconductor apparatus of the invention, it becomes possible to position the semiconductor device at a high degree of accuracy.

Abstract: The respective main electrodes of the semiconductor switching elements such as IGBTs, which are respectively mounted on the plurality of insulating boards, are electrically connected to each other via the conductor member. This configuration makes it possible to suppress the occurrence of the resonant voltage due to the junction capacity and the parasitic inductance of each semiconductor switching element.

Abstract: A chip package is provided, the chip package including: first encapsulation structure; first passivation layer formed over first encapsulation structure and first electrically conductive layer formed over first passivation layer; at least one chip arranged over first electrically conductive layer and passivation layer wherein at least one chip contact pad contacts first electrically conductive layer; at least one cavity formed in first encapsulation structure, wherein at least one cavity exposes a portion of first passivation layer covering at least one chip contact pad; second encapsulation structure disposed over first encapsulation structure and covering at least one cavity, wherein a chamber region over at least one chip contact pad is defined by at least one cavity and second encapsulation structure; wherein second encapsulation structure includes an inlet and outlet connected to chamber region, wherein inlet and outlet control an inflow and outflow of heat dissipating material to and from chamber region

Abstract: A packaged semiconductor device includes a package substrate, an integrated circuit (IC) die mounted on the package substrate, and a heat spreader mounted on the package substrate. The heat spreader surrounds at least a portion of the IC die and includes a lid with a plurality of openings. An inner portion of the heat spreader includes a plurality of thermally conductive protrusions adjacent the die.

Abstract: An embodiment of a method for making semiconductor device packages includes a heat sink matrix and a substrate. A plurality of semiconductor devices are attached to the substrate. Then, a package body is formed between the heat sink matrix and the substrate, wherein the package body encapsulates the semiconductor devices. Then, a plurality of first cutting slots is formed, wherein the first cutting slots extend through the heat sink matrix and partially extend into the package body. Then, a plurality of second cutting slots is formed, wherein the second cutting slots extend through the substrate and through the package body to the first cutting slot, thereby singulating the heat sink matrix and substrate into a plurality of individual semiconductor device packages.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting an integrated circuit over the substrate; mounting a lid base over the substrate, the lid base having a base indentation and a hole with the integrated circuit within the hole; and mounting a heat slug over the lid base, the heat slug having a slug non-horizontal side partially within the base indentation.

Abstract: Stacked semiconductor devices and assemblies including attached lead frames are disclosed herein. One embodiment of a method of manufacturing a semiconductor assembly includes forming a plurality of first side trenches to a first intermediate depth in a molded portion of a molded wafer having a plurality of dies arranged in rows and columns. The method also includes forming a plurality of lateral contacts at sidewall portions of the trenches and electrically connecting first side bond-sites of the dies with corresponding lateral contacts of the trenches. The method further includes forming a plurality of second side channels to a second intermediate depth in the molded portion such that the channels intersect the trenches. The method also includes singulating and stacking the first and second dies with the channels associated with the first die aligned with channels associated with the second die.

Abstract: A semiconductor device includes a wafer level substrate having a plurality of first conductive vias formed through the wafer level substrate. A first semiconductor die is mounted to the wafer level substrate. A first surface of the first semiconductor die includes contact pads oriented toward a first surface of the wafer level substrate. A first encapsulant is deposited over the first semiconductor die. A second semiconductor die is mounted to the wafer level substrate. A first surface of the second semiconductor die includes contact pads oriented toward a second surface of the wafer level substrate opposite the first surface of the wafer level substrate. A second encapsulant is deposited over the second semiconductor die. A plurality of bumps is formed over the plurality of first conductive vias. A second conductive via can be formed through the first encapsulant and connected to the first conductive via. The semiconductor packages are stackable.

Abstract: A layered substrate includes a first substrate including an upper surface, a lower surface, a peripheral surface between peripheral edges of the upper surface and the lower surface, and a cut portion cut into the peripheral surface and passing through the upper surface and the lower surface, and a second substrate including an upper surface, a lower surface, and a peripheral surface between peripheral edges of the upper surface and the lower surface, and the lower surface of the second substrate layered on the upper surface of the first substrate and closing the cut portion of the first substrate from above. The second substrate includes a heat conductor that is thermally connected to an element to be mounted on the upper surface of the second substrate, the heat conductor configured to thermally extend to the cut portion of the first substrate.

Abstract: Disclosed are a light emitting device and a light unit using the same. The light emitting device includes a body, a light emitting diode installed in the body, a plurality of lead frames disposed in the body and electrically connected to the light emitting diode; and a heat dissipation member received in the body, thermally connected to the light emitting diode, and having a plurality of heat dissipation fins exposed from a lower surface of the body.

Abstract: A technology with which the reliability of a package making up a semiconductor device can be enhanced is provided. A feature of the technical idea of the invention is that: a heat sink unit and an outer lead unit are separated from each other: and the outer lead unit is provided with chip placement portions and each of the chip placement portions and each heat sink are joined together. As a result, when a sealing body is formed at a resin sealing step, tying portions function as a stopper for preventing resin leakage and the formation of resin burr in a package product can be thereby prevented. In addition, camber does not occur in the heat sink unit and cracking in a sealing body caused by winding (camber) can be suppressed.

Abstract: A heat spreader die holder that covers at least 50% of both major sides of a semiconductor die. The heat spreader die holder includes at least one opening. The heat spreader die holder is attached to a substrate. Electrically conductive structures of the die are electrically coupled to electrically conductive structures of the substrate.

Abstract: A semiconductor package and a package on package are provided. The semiconductor package includes a substrate; a semiconductor chip attached to a surface of the substrate; connecting conductors disposed on the surface of the substrate; a mold formed on the substrate and in which the connecting conductors and the semiconductor chip are provided; and connecting via holes extending through the mold and exposing the connecting conductors. With respect to a first connecting via hole of the connecting via holes, a planar distance between a first connecting conductor exposed by the first connecting via hole and an entrance of the first connecting via hole is not uniform.

Abstract: A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace, a substrate and an adhesive. The heat spreader includes a post and a base. The conductive trace includes a pad, a terminal, a conductive pattern and first and second vias. The substrate includes the conductive pattern and a dielectric layer. The semiconductor device is electrically connected to the conductive trace and thermally connected to the heat spreader. The post extends upwardly from the base into an opening in the adhesive and an aperture in the substrate, and the base extends laterally from the post. The conductive trace provides signal routing between the pad and the terminal using the conductive pattern and the vias.

Abstract: A stacked structure of semiconductor packages includes an upper semiconductor package, a lower semiconductor package and inter-package connectors. The upper semiconductor package includes an upper package substrate, a plurality of upper semiconductor chips stacked on the upper package substrate, and conductive upper connection lands formed on a bottom surface of the upper package substrate. The lower semiconductor package includes a lower package substrate, a plurality of lower semiconductor chips stacked on the lower package substrate, and lower through-silicon vias vertically penetrating the lower semiconductor chips. The inter-package connectors may electrically connect the through-silicon vias to the upper connection lands.

Abstract: A heatsink may include an area in thermal contact with a semiconductor microchip surface and a first trench of a first depth. The first trench may be substantially continuous around the area. A first substance, such as ferrite, may be positioned in the first trench to attenuate electromagnetic interference. A second trench having a second depth may be formed around and further from the area than the first trench. A second substance may be positioned in the second trench.

Abstract: A method of making a semiconductor chip assembly includes providing a post and a base, mounting an adhesive on the base including inserting the post into an opening in the adhesive, mounting a conductive layer on the adhesive including aligning the post with an aperture in the conductive layer, then flowing the adhesive upward between the post and the conductive layer, solidifying the adhesive, then providing a conductive trace that includes a pad, a terminal, a plated through-hole and a selected portion of the conductive layer, mounting a semiconductor device on the post, wherein a heat spreader includes the post and the base, electrically connecting the semiconductor device to the conductive trace and thermally connecting the semiconductor device to the heat spreader.

Abstract: A method of making a semiconductor chip assembly includes providing a bump and a ledge, wherein the bump includes first, second and third bent corners that shape a cavity, mounting an adhesive on the ledge including inserting the bump into an opening in the adhesive, mounting a conductive layer on the adhesive including aligning the bump with an aperture in the conductive layer, then flowing the adhesive between the bump and the conductive layer, solidifying the adhesive, then providing a conductive trace that includes a pad, a terminal and a selected portion of the ledge, providing a heat spreader that includes the bump, then mounting a semiconductor device on the bump within the cavity, electrically connecting the semiconductor device to the conductive trace and thermally connecting the semiconductor device to the heat spreader.

Abstract: A method of making a semiconductor chip assembly includes providing first and second posts, first and second adhesives and a base, wherein the first post extends from the base in a first vertical direction into a first opening in the first adhesive, the second post extends from the base in a second vertical direction into a second opening in the second adhesive and the base is sandwiched between and extends laterally from the posts, then flowing the first adhesive in the first vertical direction and the second adhesive in the second vertical direction, solidifying the adhesives, then providing a conductive trace that includes a pad and a terminal, wherein the pad extends beyond the base in the first vertical direction and the terminal extends beyond the base in the second vertical direction, providing a heat spreader that includes the posts and the base, then mounting a semiconductor device on the first post, electrically connecting the semiconductor device to the conductive trace and thermally connecting the

Abstract: A method of making a semiconductor chip assembly includes providing first and second posts, first and second adhesives and a base, wherein the first post extends from the base in a first vertical direction into a first opening in the first adhesive and is located within a periphery of the second post, the second post extends from the base in a second vertical direction into a second opening in the second adhesive and the base is sandwiched between and extends laterally from the posts, then flowing and solidifying the adhesives, then providing a conductive trace that includes a pad and a terminal, wherein the pad extends beyond the base in the first vertical direction and the terminal extends beyond the base in the second vertical direction, providing a heat spreader that includes the posts and the base, then mounting a semiconductor device on the first post, electrically connecting the semiconductor device to the conductive trace and thermally connecting the semiconductor device to the heat spreader.

Abstract: A sealed semiconductor power module that may include a rectifier, such as a silicon controlled rectifier (SCR), is provided. The module includes an AlN substrate having a bottom surface positioned on a metallic base plate and a top surface that includes a first pad and a second pad, the substrate including a copper body on both of the two major surfaces. The module also includes a first die and a second die positioned on top of the first and second pads, respectively, the first die and the second die each including a main contact area on a top surface thereof, the first die including an isolated gate area on the top surface to which is coupled a gate terminal; and first and second power terminals in direct wirebondless electrical connection via molybdenum tabs with the main contact areas of the die.

Abstract: A method of making a semiconductor chip assembly includes providing a post and a base, mounting an adhesive on the base including inserting the post through an opening in the adhesive, mounting a substrate on the adhesive including inserting the post into an aperture in the substrate, then flowing the adhesive between the post and the substrate in the aperture, solidifying the adhesive, then grinding the post and the adhesive, then mounting a semiconductor device on a heat spreader that includes the post and the base, electrically connecting the semiconductor device to the substrate and thermally connecting the semiconductor device to the heat spreader.

Abstract: A method of making a semiconductor chip assembly includes providing first and second posts, first and second adhesives, first and second conductive layers and a dielectric base, wherein the first post extends from the dielectric base in a first vertical direction into a first opening in the first adhesive and is aligned with a first aperture in the first conductive layer, the second post extends from the dielectric base in a second vertical direction into a second opening in the second adhesive and is aligned with a second aperture in the second conductive layer and the dielectric base is sandwiched between and extends laterally from the posts, then flowing the first adhesive in the first vertical direction and the second adhesive in the second vertical direction, solidifying the adhesives, then providing a conductive trace that includes a pad, a terminal and selected portions of the conductive layers, wherein the pad extends beyond the dielectric base in the first vertical direction and the terminal extends

Abstract: An LED assembly can include a heat sink base, at least one LED die attached to the heat sink base, and a lens. One or more layers of phosphor can be formed upon the lens. A heat sink, such as a finned heat sink, can attach the heat sink base to the lens. Heat from the LED die can flow through the heat sink base to the heat sink, from which the heat can be dissipated. Similarly, heat from phosphors can flow through the lens to the heat sink, from which the heat can be dissipated. By removing heat from the LED die, more current can be used to drive the LED die, thus providing brighter light. By removing heat from the phosphors, desired colors can be more reliably provided.

Abstract: In various embodiments, semiconductor components and methods to manufacture these components are disclosed. In one embodiment, a method to manufacture a semiconductor component is disclosed. The semiconductor includes a heat sink and a semiconductor die that has a first terminal on a top surface of the semiconductor die, a second terminal on the top surface of the die, and a third terminal on the bottom surface of the die. The method includes attaching a first portion of a leadframe structure to the first terminal of the semiconductor die. The method further includes attaching the second terminal of the semiconductor die to the heat sink after the attaching of the first portion of the leadframe structure to the first terminal of the semiconductor die, wherein the leadframe structure is spaced apart from the heat sink and is electrically isolated from the heat sink. Other embodiments are described and claimed.

Abstract: An LED leadframe package with surface tension function to enable the production of LED package with convex lens shape by using dispensing method is disclosed. The LED leadframe package of the invention is a PPA supported package house for LED packaging with metal base, four identical metal electrodes, and PPA plastic to fix the metal electrodes and the heat dissipation base together, four ring-alike structures with a sharp edge and with a tilted inner surface, and three ring-alike grooves formed between sharp edge ring-alike structures.

Abstract: A semiconductor package includes a chip base material; a capacitor formed on the base material; and a cover formed over the base material to cover the capacitor, and having a side portion and an upper portion. The base material is provided with a bonding pattern connecting the base material and the cover to cover the capacitor. The bonding pattern includes a region A having a substantially uniform pattern width A, and at least one region B having a pattern width B which is larger than the width pattern width A.

Abstract: A method of forming a ball grid array (BGA) package is provided. The method includes coupling an integrated circuit (IC) die to a heat spreader in an opening of a substrate, the opening of the substrate extending through the substrate, such that a portion of the heat spreader is accessible through the opening and coupling a first surface of a second substrate to the IC die via a bump interconnect. The second surface of the second substrate has an array of contact pads capable of coupling to a board.

Abstract: A semiconductor device includes a wiring board, a semiconductor element mounted on the wiring board, a sealing resin configured to cover the semiconductor element, a ground electrode having an end connected to a wiring layer of the wiring board and an exposing part exposed at a surface of the sealing resin, and a shielding member configured to cover the sealing resin and be connected to the ground electrode.

Abstract: The invention provides semiconductor chip packages, tools, and methods for preventing and for correcting leadfinger deformation caused during wirebonding in semiconductor chip package manufacturing. Disclosed are improved heat blocks and methods for their use in ensuring adequate clearance between leadfingers and adjacent heat spreaders, as well as semiconductor chip package assemblies wherein a selected clearance between leadfingers and parallel surfaces may be assured. Methods of the invention include steps for supporting the proximal ends of the leadfingers using the wirebonding cavity of a heat block. Thus supported, a plurality of bondwires are attached to couple bond pads of the semiconductor chip to the proximal ends of leadfingers. Thereafter, the clearance between the wirebonded proximal ends of the leadfingers and the adjacent parallel surface of the heat spreader is adjusted using a spacing cavity of the heat block.

Abstract: Embodiments of a heat spreader and an assembly including such a heat spreader are disclosed. The heat spreader includes a stiffening member, which in one embodiment comprises a wall extending from a lower surface of the heat spreader. The wall may be coupled with a substrate, and the addition of this wall may decrease warpage of the substrate and increase package stiffness. The wall may be located between adjacent integrated circuit die that are disposed on the substrate. Other embodiments are described and claimed.

Abstract: The present invention is intended to obtain a semiconductor device that is reduced in size, weight, and cost and improved in performance stability and productivity. The semiconductor device includes a semiconductor module in which a semiconductor element is sealed with a resin, a reinforcing beam fixed to an upper surface of the semiconductor module via a plate-like spring, and a frame part to which both ends of the reinforcing beam are fixed, the frame part being disposed in such a fashion as to enclose from four directions an outer periphery of the semiconductor module, plate-like spring, and the reinforcing beam.

Abstract: Various methods and apparatus for establishing a thermal pathway for a semiconductor device are disclosed. In one aspect, a method of manufacturing is provided that includes placing a gel-type thermal interface material in a preselected pattern on a semiconductor chip that is coupled to a substrate. The preselected pattern of gel-type thermal interface material is allowed to partially set up. Additional thermal interface material is placed on the semiconductor chip and cured.

Abstract: A semiconductor power module includes one or more power semiconductor power devices sandwiched between a fluid conducting base and a fluid conducting cover joined to the base. Fluid coolant entering the base diverges into a first flow path through the base and a second parallel flow path through the cover, and then converges and discharges through an outlet. The semiconductor devices have upper and lower active areas that are thermally coupled to inboard faces of the cover and base for low double-sided thermal resistance, and the devices are electrically accessed through a set of terminals formed on the base. Multiple sets of semiconductor power devices are double-side cooled by joining multiple fluid conducting covers to the base such that the coolant successively diverges and then re-converges at the locations where each cover is joined to the base. Preferably, the flow paths in both the base and cover include integral features for enhancing the surface area in contact with the coolant.

Abstract: One embodiment of the present invention is a compliant thermal contactor that includes a resilient metal film having a plurality of first thermally conductive, compliant posts disposed in an array on a top side thereof and a plurality of second thermally conductive, compliant posts disposed in an array on a bottom side thereof.

Abstract: A heat dissipation package is provided. Conducting leads of the package are located between two dissipating parts of a heat dissipation carrier to form the heat dissipation package with a structure of heat outside and electricity inside. Consequently, there is no limitation caused by electrical elements surrounding the heat dissipation carrier, so as to enhance the expandability of the heat dissipation carrier and improve the efficiency for heat dissipation of the heat generation element.

Abstract: A package structure and an electronic device using the same are provided. The package structure includes a chip module and a cover. The chip module covered by the cover is used for receiving a first signal. The chip module includes a substrate, a heat sink and a first chip. The substrate has a first surface, a second surface and an opening. The first surface is opposite to the second surface. The opening penetrates the first surface and the second surface. The heat sink is disposed on the first surface of the substrate and covers the opening. The first chip is disposed on the heat sink and is positioned inside the opening. A bottom surface of the first chip flatly contacts the heat sink. The cover has a window element. The first signal passes through the window element to contact with the chip module.

Abstract: A double-face-cooled semiconductor module with an upper arm and a lower arm of an inverter circuit includes first and second heat dissipation members, each having a heat dissipation surface on one side and a conducting member formed on another side through an insulation member. On the conducting member on the first dissipation plate is provided with a fixing portion that fixes a collector surface of the semiconductor chip and a gate conductor connected to a gate terminal of the semiconductor module. The gate electrode terminal and the gate conductor are wire bonded. The conducting member on the second heat dissipation member is connected to an emitter surface of the semiconductor chip connected to the first heat dissipation member. The productivity and reliability are improved by most of formation operations for the upper and lower arms series circuit on one of the heat dissipation member.

Abstract: The present invention relates generally to apparatus and methods for cooling semiconductor integrated circuit (IC) chip package structures. More specifically, the present invention relates to apparatus and methods for thermally coupling semiconductor chips to a heat conducting device (e.g., copper thermal hat or lid) using a compliant thermally conductive material (e.g., thermal paste), wherein a thermal interface is designed to prevent/inhibit the formation of voids in the compliant thermally conductive material due to the flow of such material in and out from between the chips and the heat conducting device due to thermal cycling.

Abstract: A multi-functional metal shield case and a method for making the same are provided. The multi-functional metal shield case includes a metal main body and an electrically non-conductive and heat conductive silicon layer. The metal main body includes a base and sidewalls integrally bent along edges of the base, and the electrically non-conductive and heat conductive silicon layer is formed on inner sides of the base and the sidewalls. Accordingly, heat can be rapidly transferred to the metal main body and emitted to an outside. Since the heat conductive silicon layer is non-conductive, an electric shock does not occur between the electronic component and the metal shield case. Further, since the heat conductive silicon layer is in contact with the electronic component, heat can be transferred more rapidly.

Abstract: A semiconductor device 10 includes a silicon substrate 20 having a first interconnection layer 24, a second interconnection layer 26, and grooves 22 provided at the second main surface 20b. Mounted on the substrate 20 are one or more semiconductor chips 30 having chip external terminals 32 electrically connected to the first interconnection layer; and one or more peripheral chips 40 electrically connected to the first interconnection layer on the silicon substrate. By the provision of the grooves 22, the heat radiating property is improved.

Abstract: The present disclosure suggests various microelectronic component assembly designs and methods for manufacturing microelectronic component assemblies. In one particular implementation, a microelectronic component assembly includes a microelectronic component, a substrate, and at least one bond wire. The substrate has a reduced-thickness base adjacent terminals of the microelectronic component and a body having a contact surface spaced farther from the microelectronic component than a bond pad surface of the base. The bond wire couples the microelectronic component to a bond pad carried by the bond pad surface and has a maximum height outwardly from the microelectronic component that is no greater than the height of the contact surface from the microelectronic component.

Abstract: A module (100) comprises a component (10) and a shielding element (11), which is mounted on a main surface (12) of the component (10) and has a welding contact (13).

Abstract: An electronic component includes at least one vertical MOSFET device, a leadframe and a contact clip. A source electrode and gate electrode are provided on a lower surface of the MOSFET device and are mounted on a source portion and a gate portion, respectively, of the leadframe. The contact clip is electrically connected between the drain electrode, which is positioned on the upper surface of MOSFET device, and a drain portion of the leadframe.

Abstract: A semiconductor device according to a preferred embodiment of the present invention is a semiconductor device including a main substrate and one or more sub substrates, and the semiconductor device includes first heat generating devices mounted on the sub substrates, sub-substrate heatsinks mounted to the first heat generating devices, and a main-substrate heatsink mounted to the main substrate, wherein the sub-substrate heatsinks and the main-substrate heatsink are secured to each other, such that there is a predetermined positional relationship between the sub substrates and the main substrate.

Abstract: Various integrated circuit packages, lids therefor and methods of making the same are provided. In one aspect, a method of manufacturing is provided that includes providing an integrated circuit package lid that has a surface adapted to face towards an integrated circuit, and forming a wetting film on the surface. The wetting film has at least one void where the surface of the lid is exposed. The void inhibits bonding so that a stress reduction site is produced.

Abstract: A heat dissipating package structure includes a chip carrier; a semiconductor chip mounted and electrically connected to the chip carrier; a heat spreader having a first surface, an opposed second surface and a hollow structure, the second surface of the heat spreader being mounted on the chip, wherein the chip is larger in size than the hollow structure such that the chip is partly exposed to the hollow structure; an encapsulant formed between the heat spreader and the chip carrier, for encapsulating the chip, wherein the first surface and sides of the heat spreader are exposed from the encapsulant to dissipate heat produced from the chip; and a plurality of conductive elements disposed on the chip carrier, for electrically connecting the chip to an external device. The present invention also provides a method for fabricating the heat dissipating package structure.

Abstract: A package module is provided. The package module includes a substrate having a surface including a die region. A die is disposed in the die region of the surface on the substrate. A flexible heat spreader conformally covers the surface of the substrate and the die. The invention also discloses an electronic device with the package module.