Abstract: In one example, a semiconductor device comprises an electronic component comprising a component face side, a component base side, a component lateral side connecting the component face side to the component base side, and a component port adjacent to the component face side, wherein the component port comprises a component port face. A clip structure comprises a first clip pad, a second clip pad, a first clip leg connecting the first clip pad to the second clip pad, and a first clip face. An encapsulant covers portions of the electronic component and the clip structure. The encapsulant comprises an encapsulant face, the first clip pad is coupled to the electronic component, and the component port face and the first clip face are exposed from the encapsulant face. Other examples and related methods are also disclosed herein.

Abstract: A heat dissipation structure is provided. The heat dissipation structure includes a heat dissipation unit and a fixation unit. The fixation unit has a bottom and a wall that jointly define a hollow area. The fixation unit is surroundingly arranged on a periphery of a heating source. The hollow area has a first non-masking area, a second non-masking area, and a masking area. The masking area corresponds to at least one part of the heat dissipation unit, and the first non-masking area and the second non-masking area are respectively arranged on opposite sides of the masking area. The first non-masking area has a first volume, the second non-masking area has a second volume, and a sum of the first volume and the second volume is at least greater than a predetermined volume change of the heat dissipation unit.

Abstract: A method of manufacturing an optoelectronic device, including the steps of: a) arranging an active photosensitive diode stack on a first substrate; b) arranging an active light-emitting diode stack on a second substrate; c) after steps a) and b), transferring the active photosensitive diode stack onto the active light-emitting diode stack, and then removing the first substrate; and d) after step c), transferring the assembly comprising the active photosensitive diode stack and the active light-emitting diode stack onto an integrated control circuit previously formed inside and on top of a third substrate, and then removing the second substrate.

Abstract: An integrated circuit package comprising a heat spreader; one or more substrate(s); one or more standoff(s); and one or more electronic component(s). One or more component(s) is/are coupled to a substrate and the substrate maybe coupled to a heat spreader. Standoff(s) are coupled on the heat spreader or substrates forming a cavity, and one or more component(s) and substrate(s) are located inside the cavity.

Abstract: Apparatus for flattening a warped ball grid array (BGA) package, including a first plate having a first surface and opposite second surface and a second plate having a first surface and opposite second surface. The first surface of the first plate and the first surface of the second plate oppose each other with a gap there-between. The gap houses the warped BGA package there-in, the warped BGA package including a package substrate with solder balls attached to a device mounting surface of the package substrate to form a BGA thereon. The gap adjustable by changing the position of the first plate or of the second plate such that a pushing force is applicable to the warped BGA package. A method of manufacturing a flattened BGA package and computer having a circuit that include the flatted BGA package are also disclosed.

Abstract: The present disclosure provides for a heatshield that can be actively cooled during a rework process. The heatshield may include a backer plate and a metal plate. A plurality of vents may extend from air inlet ducts to a top surface of the backer plate such that the plurality of vents directs cooling gas forced into the heatshield towards the metal plate and a first ball grid array (BGA) package. The cooling gas may maintain the solder joint temperature of the first BGA package below a reflow temperature and below a solidus temperature to prevent reflow-related solder joint defects from occurring in the first BGA package during rework of a second BGA package.

Abstract: The invention relates to a device (10; 10a) for inductive energy transfer into a human body (1), having a transmitter unit (11) with a housing (12), in which at least one transmitter coil (14) is arranged, wherein the housing (12) comprises a contact surface (23), which is configured in order to be brought into surface contact with the body (1), and a receiver unit (20) that can be positioned in the body (1) with a receiver coil (21), wherein a heat-insulating element (26) and a heat-conducting element (30; 30a) are arranged between the transmitter coil (14) and the body.

Abstract: A sample holder includes a base comprising a support structure and a printed circuit board (PCB) in contact with the base. The PCB has a through hole. The PCB has a cavity in at least a part of the base below the through hole. The support structure that supports a surface of a chip and is electrically connected to the base. The support structure is disposed in the cavity. At least a part of the section supporting the chip in the support structure is not parallel to the back surface of the chip.

Abstract: An electronic device includes a semiconductor device, a wiring board, a heat dissipating member, and a housing. The semiconductor device includes a semiconductor element, a conductive member electrically connected to the semiconductor element, and a resin mold sealing the semiconductor element. The wiring board includes a wiring portion on which the semiconductor device is mounted, and a resist portion disposed around the wiring portion. The heat dissipating member is in thermal contact with at least one of surfaces of the semiconductor device. The housing is in thermal contact with the semiconductor device through the heat dissipating member. Each of the resin mold and the heat dissipating member has a thermal conductivity higher than that of the resist portion.

Abstract: The present description concerns a package for an electronic device. The package including a plate and a lateral wall, separated by a layer made of a bonding material and at least one region made of a material configured to form in the region an opening between the inside and the outside of the package when the package is heated.

Abstract: A printed circuit board assembly comprises: a printed circuit board (PCB); an integrated circuit (IC) package that is mounted on the PCB and includes a first surface and a bare IC die disposed on the first surface; and a vapor chamber coupled to the first surface of the IC package.

Abstract: The semiconductor chip includes a semiconductor substrate having a surface, a circuit formed on the surface, and a plurality of pillars coupled to the surface adjacent to the circuit. The plurality of pillars is thermally conductive and is thermally coupled to the circuit so as to dissipate heat generated by the circuit. The semiconductor substrate, circuit, and plurality of pillars are integral parts of the integrated semiconductor chip. A method of fabricating the integrated semiconductor chip includes providing a semiconductor substrate having a surface. The method includes forming a circuit on the surface, and forming a plurality of pillars thermally coupled to the surface adjacent to the circuit.

Abstract: A semiconductor device including a circuit substrate, a chip package, and a stiffener ring is provided. The chip package is disposed on and electrically connected to the circuit substrate, the chip package includes a pair of first parallel sides and a pair of second parallel sides shorter than the pair of first parallel sides. The stiffener ring is disposed on the circuit substrate, the stiffener ring includes first stiffener portions extending along a direction substantially parallel with the pair of first parallel sides and second stiffener portions extending along the direction substantially parallel with the pair of second parallel sides. The first stiffener portions are connected to the second stiffener portions, and the second stiffener portions is mechanically weaker than the first stiffener portions. A semiconductor device including stiffener lids is also provided.

Abstract: An apparatus includes a baseplate and a cooler providing a cooling channel adapted for providing a coolant flow. An electronic circuit includes a power semiconductor device disposed at the first side of baseplate. A footprint of the power semiconductor device defines a device area on the first side. A cooling area at the second side of the baseplate opposite the device area is adapted for dissipating heat from the baseplate by bringing the cooling area into thermal contact with the coolant flow in the cooling channel. An auxiliary area is located on the second side of the baseplate adjacent to the cooling area. The auxiliary area includes a flow guide for reducing a flow rate of the coolant flow in the auxiliary area and the cooling channel is adapted to receive the cooling area and the flow guide.

Abstract: An array substrate, a method of manufacturing the array substrate, and a display device are provided. The array substrate includes: a transparent rigid base; light-emitting chips on the transparent rigid base, each light-emitting chip including a chip body and a pin coupled to the chip body, a light-exiting surface of the chip body facing towards the transparent rigid base, and the pin being on a side of the chip body facing away from the transparent rigid base; a driving wire layer on a side of the pin facing away from the transparent rigid base; and a driving chip structure on a side of the driving wire layer facing away from the transparent rigid base. The driving chip structure is coupled to pins of the plurality of light-emitting chips through the driving wire layer, and is used for provide driving signals for the light-emitting chips.

Abstract: A method for manufacturing a PCB with an embedded thermal conductor and a PCB are provided. A sheet of copper-clad ceramic serves as a thermal conductor. A sheet of copper foil having no opening serves as an outer layer of a laminate. A part of the sheet of copper foil covering the thermal conductor is removed after a lamination process, to expose a conductive layer as the outer layer of the thermal conductor. Finally, the outer layer pattern is formed. The sheet of copper foil has no opening before the lamination process, so that the sheet of copper foil has good flatness during the lamination process, thereby avoiding wrinkles. Moreover, the sheet of copper-clad ceramic serves as the thermal conductor, so that a pattern is manufactured on the outer layer of the thermal conductor based on the exposed conductive layer.

Abstract: A dual-side cooling (DSC) semiconductor package includes a first metal-insulator-metal (MIM) substrate having a first insulator layer, first metallic layer, and second metallic layer. A second MIM substrate includes a second insulator layer, third metallic layer, and fourth metallic layer. The third metallic layer includes a first portion having a first contact area and a second portion, electrically isolated from the first portion, having a second contact area. A semiconductor die is coupled with the second metallic layer and is directly coupled with the third metallic layer through one or more solders, sintered layers, electrically conductive tapes, solderable top metal (STM) layers, and/or under bump metal (UBM) layers. The first contact area is electrically coupled with a first electrical contact of the die and the second contact area is electrically coupled with a second electrical contact of the die. The first and fourth metallic layers are exposed through an encapsulant.

Abstract: A heat dissipation device of electronic equipment has a base, a heat dissipation group, and a cover. The base has an opening, a chamber, and a boss formed in the chamber. The heat dissipation group is connected to the base and has a circuit board and a cooling blade. The circuit board is mounted in the chamber, abuts against the boss, and has a heat source area and at least one non-heat-source area. The heat source area has a first surface facing the boss and a second surface facing the opening. The cooling blade is connected to the base and is located at the second surface. The first surface and the second surface of the heat source area respectively correspond to the boss and the cooling blade in location to provide a guiding direction for heat conduction. The cover is connected to the base.

Abstract: An electronic device includes a substrate, an electronic component, a structure, and an adhesive. The substrate has a proximal surface. The electronic component includes at least one die, wherein the electronic component is attached to the substrate. The structure has a proximal surface adjacent to proximal surface of the substrate. A feature extends from the proximal surface of the structure or the substrate, and the adhesive contacts the feature and the proximal surfaces of the structure and the substrate. In another aspect, a process of forming the electronic device can include applying the adhesive, placing the substrate and structure adjacent to each other, wherein the adhesive contacts the feature and the proximal surfaces of the substrate and the substrate, and curing the adhesive.

Abstract: An apparatus includes a printed circuit board (PCB), and an integrated circuit (IC) package connected with the PCB. The IC package includes a package substrate, a die secured to the package substrate and including an integrated circuit, and a stiffener ring secured to the package substrate and surrounding so as to define a perimeter around the die. The stiffener ring increases a rigidity of the package substrate and delivers electrical power to the integrated circuit, where the stiffener ring includes a first conductive layer forming a power (PWR) plane for the integrated circuit, a second conductive layer forming a ground (GND) plane for the integrated circuit, and an insulating layer disposed between the first conductive layer and the second conductive layer.

Abstract: The present invention improves a heat dissipation property of a semiconductor device by transferring hexagonal boron nitride (hBN) with a two-dimensional nanostructure to the semiconductor device. A semiconductor device of the present invention includes a substrate having a first surface and a second surface, a semiconductor layer formed on the first surface of the substrate, an hBN layer formed on at least one surface of the first surface and the second surface of the substrate, and a heat sink positioned on the second surface of the substrate. A radiation rate of heat generated during driving of an element is increased to decrease a reduction in lifetime of a semiconductor device due to a temperature increase. The semiconductor device has a structure and configuration which are very effective in improving a rapid temperature increase due to heat generated by high-power semiconductor devices.

Abstract: A battery and cooling device system comprising a thermal battery and a cooling device including a boiler, a condenser, a vapor tube, a reaction container, and a siphon. The boiler boils a solvent via heat drawn from the battery. The condenser condenses the vaporized solvent. The vapor tube connects the boiler to the reaction container so that the vaporized solvent travels through the vapor tube from the boiler into the condenser. The reaction container receives the liquidated solvent from the condenser so that the liquidated solvent interacts with a solute in the reaction container to effect an endothermic reaction to further draw heat from the battery. The siphon connects the reaction container to the boiler and drains the liquid solvent from the reaction container into the boiler once a predetermined amount of liquid solvent fills the reaction container.

Abstract: A semiconductor module includes a cooling device that includes: a ceiling plate; a side wall; a bottom plate; a plurality of pin fins having a polygonal shape and arranged in a matrix form in which one end of the respective pin fins is connected to a fin region having a rectangular shape; an inlet for a coolant at a first position adjacent to a part of one of long sides of the fin region, and an outlet for the coolant at a second position adjacent to a part of the other long side of the fin region. The matrix directions of the respective pin fins make an angle with a straight line connecting the first position and the second position, and a length of a segment of the straight line passing across the fin region is longer than a length of short sides of the fin region.

Abstract: The present disclosure relate to a semiconductor light emitting device and a method for manufacturing the same. The semiconductor light emitting device comprises a semiconductor light emitting chip, and first electrodes electrically connected to the semiconductor light emitting chip, with the first electrodes each having a planar area larger than that of the semiconductor light emitting chip, wherein lower surfaces of the first electrodes are exposed externally, and an insulating material is filled in-between inner lateral surfaces of the first electrodes.

Abstract: A semiconductor device includes a semiconductor chip, a heat sink, a resin package, heat transfer material and multiple spacers. The heat sink absorbs heat of the semiconductor chip. The resin package accommodates the semiconductor chip, and the resin package has a surface at which the heat sink is disposed. The heat transfer material has fluidity, and the heat transfer material is filled between the heat sink and the cooling plate. The spacers are dispersedly arranged in the heat transfer material, and the spacers are in contact with the heat sink and the cooling plate.

Abstract: A multi-die package includes a thermally conductive flange, a first semiconductor die made of a first semiconductor material attached to the thermally conductive flange via a first die attach material, a second semiconductor die attached to the same thermally conductive flange as the first semiconductor die via a second die attach material, and leads attached to the thermally conductive flange or to an insulating member secured to the flange. The leads are configured to provide external electrical access to the first and second semiconductor dies. The second semiconductor die is made of a second semiconductor material different than the first semiconductor material. Additional multi-die package embodiments are described.

Abstract: A structure including a wiring substrate, an interposer disposed on and electrically connected to the wiring substrate, a semiconductor die disposed on and electrically connected to the interposer, a first insulating encapsulation disposed on the interposer, a second insulating encapsulation disposed on the wiring substrate, and a lid is provided. The semiconductor die is laterally encapsulated by the first insulating encapsulation. The semiconductor die and the first insulating encapsulation are laterally encapsulated by the second insulating encapsulation. A top surface of the first insulating encapsulation is substantially leveled with a top surface of the second insulating encapsulation and a surface of the semiconductor die. The lid is disposed on the semiconductor die, the first insulating encapsulation and the second insulating encapsulation.

Abstract: A part among a plurality of through vias formed in a non-transistor region is a floating via having a floating potential.

Abstract: A display device with self-luminous display elements, which are arranged in a panel. The panel is provided, on its rear side opposite the light-emitting surface used for display, with a heat distribution element, on the side of which facing away from the rear side at least one temperature sensor is arranged. The heat distribution element has at least one opening, behind which a light sensor is arranged, wherein the light sensor and the temperature sensor are arranged on a common carrier.

Abstract: A semiconductor package includes a substrate including a wiring, a semiconductor chip structure on the substrate, and electrically connected to the wiring, an underfill resin in a space between the substrate and the semiconductor chip structure, and a stiffener surrounding the semiconductor chip structure, on the substrate, wherein the stiffener includes a conductive frame having a cavity and an insulating filler in the cavity.

Abstract: A power electronics converter includes a substrate and a converter commutation cell including a power circuit. The power circuit includes at least one power semiconductor switching element and at least one capacitor. Each power semiconductor switching element is comprised in a power semiconductor prepackage. An electrical connection side of the respective power semiconductor prepackage is spaced apart in a z direction from the substrate so as to define a prepackage gap between the substrate and the electrical connection side. At least a portion of the prepackage gap is filled with an electrically insulating material having voids. A converter parameter ? defined as an insulation fill factor divided by a maximum void size is greater than or equal to 10/mm. The insulation fill factor is defined as a cumulated volume of the voids subtracted from a volume of the electrically insulating material divided by the volume of the electrically insulating material.

Abstract: A chip encapsulation structure, including: a wafer provided with a groove; a first metal wire arranged on surfaces of the groove and the wafer; a metal solder ball arranged on the first metal wire or on a metal pad of the chip, and is configured to solder the metal pad of the chip to the first metal wire; a first plastic encapsulation film covering upper surfaces of the wafer, the chip and the first metal wire, and entering a gap between a periphery of a functional area of the chip and the first metal wire, so as to form a closed cavity among the wafer, the groove and the chip; an inductive structure arranged on an upper surface of the first plastic encapsulation film and/or a lower surface of the wafer, and connected to the chip through the first metal wire; and a pad arranged on the inductive structure.

Abstract: It is an object of the present invention to improve a heat radiation property of a metal wire on a semiconductor chip in a power module. A power module includes: a plurality of metal wires connected to a surface of at least one semiconductor chip; and a thermal conductive sheet having contact with the metal wire. The metal wire includes: at least one first metal wire connecting a surface of the semiconductor chip and a circuit pattern and at least one second metal wire connecting two points on the surface of the semiconductor chip and having the same potential as the first metal wire. The thermal conductive sheet includes a graphite sheet, and a sheet surface of the thermal conductive sheet has contact with the at least one first metal wire and the at least one second metal wire.

Abstract: The disclosure describes a 3D (3-dimensional) water block for cooling a heat source of an electronic system such as a semiconductor chip package, comprising: a box with a base plate, a 3D heat exchanger and a circulating liquid; wherein the base plate is attached onto the heat source through a thermal interface material, the 3D heat exchanger includes a heat pipe or vapor chamber structure and a plurality of fin layers, which are attached to the heat pipe or vapor chamber structure so as to form a plurality of channels among them; wherein the heat pipe or vapor chamber structure includes a bottom portion attached to the base plate and a top portion extending upwards from the base plate; and wherein the circulating liquid flows through the plurality of channels for taking away heat from the 3D heat exchanger to an ambient.

Abstract: Flexible modules and methods of manufacture are described. In an embodiment, a flexible module includes a flex board formed in which a passivation layer is applied in liquid form in a panel level process, followed by exposure and development. An electronic component is then mounted onto the flex board and encapsulated in a molding compound that is directly on a top surface of the passivation layer.

Abstract: A semiconductor package including a package base substrate, an interposer on the package base substrate, a plurality of semiconductor chips on the interposer, and a stiffener structure including a stiffener frame and a stiffener extension portion, the stiffener frame being on the package base substrate and apart from the interposer, the stiffener extension portion extending from the stiffener frame, spaced apart from the plurality of semiconductor chips, and extending onto the interposer to have a portion on the interposer, and the stiffener frame being an integral structure with the extension portion, may be provided.

Abstract: A 3D device including: a first level including first transistors and a first interconnect; a second level including second transistors and is overlaying the first level; at least four electronic circuit units (ECUs); and a redundancy circuit, where each of the ECUs includes a first circuit which includes a portion of the first transistors, where each of the ECUs includes a second circuit, the second circuit including a portion of the second transistors, where each of the at least four ECUs includes a first vertical bus, where the first vertical bus provides electrical connections between the first circuit and the second circuit, where each of the at least four ECUs includes at least one processor and at least one memory array, where the second level is bonded to the first level, and the bonded includes oxide to oxide bonding regions and metal to metal bonding regions.

Abstract: A method of semiconductor overlay measuring includes following operations. Provide a test substrate. Conductive structures are located in the test substrate and exposed from a top surface of the test substrate. Positioning the test substrate to a standard position and capturing a first image of the top surface of the test substrate. Mark first marks corresponding to the exposed conductive structures on the first image. Form a test capping layer with capacitor openings on the top surface of the test substrate. Move the test substrate to the standard position and capturing a second image of a top surface of the test capping layer. Identify the capacitor openings on the second image with second marks. Compare the first marks with the second marks to determine a position offset between the test substrate and the test capping layer.

Abstract: Methods, apparatuses, and systems related to die-to-die communications are described. An apparatus may include an interfacing die and at least one additional die communicatively coupled to each other through an internal bus. The interfacing die may be configured to provide a combined external interface for the coupled dies. For the die-to-die communications, a target die may coordinate transfer of communicated data to the internal interface according to a timing signal generated by a source external to the at least one additional die.

Abstract: In a semiconductor device, a first metal plate faces a first semiconductor element and a second semiconductor element and is electrically connected to a second terminal. A second metal plate faces the first metal plate while interposing the first semiconductor element between the first and second metal plates, and is electrically connected to a first terminal. A third metal plate faces the first metal plate while interposing the second semiconductor element between the first and third metal plates. The first semiconductor element has an electrode on a surface adjacent to the second metal plate and electrically connected to the second metal plate, and an electrode on a surface adjacent to the first metal plate and electrically connected to the third metal plate. The first semiconductor element is thermally connected to the first metal plate while being electrically insulated from the first metal plate by an insulator.

Abstract: A motor-driven compressor includes an inverter and a housing. The inverter includes three-phase switching elements and a holder that retains the switching elements. The holder is fixed to the housing with fastening members and is configured to push the three-phase switching elements toward a heat dissipating surface of the housing. The three-phase switching elements are arranged along a line segment that connects two of the fastening members. The holder includes a first accommodating portion that accommodates one of the three-phase switching elements that is located in the middle, and two second accommodating portions that respectively accommodate two of the three-phase switching elements that are located at opposite ends. Each of the two second accommodating portions includes a tongue-shaped contact portion that contacts the corresponding switching element. The contact portions are configured to be deformed to reduce a pushing force of the holder acting on the switching elements.

Abstract: A semiconductor package includes a module substrate having opposite top and bottom surfaces, a semiconductor chip provided with bumps and mounted on the top surface of the module substrate via the bumps, and a metal member having a top portion disposed at a level higher than the semiconductor chip with reference to the top surface of the module substrate and including the semiconductor chip in plan view and a side portion extending from the top portion toward the module substrate. The module substrate includes a first metal film disposed on or in at least one of the bottom surface and an internal layer of the module substrate. The first metal film is electrically connected to the bumps and reaches a side surface of the module substrate. The side portion is thermally coupled to the first metal film at the side surface of the module substrate.

Abstract: A heat dissipation plate has a structural body including a first metal portion formed from a first metal and a second metal portion formed from a second metal that differs from the first metal and bonded to the first metal portion through solid state bonding. The first metal has a higher thermal conductance than the second metal, and the second metal has a higher mechanical strength than the first metal. The structural body includes a first surface of the heat dissipation plate connected to a semiconductor element and a second surface of the heat dissipation plate located at a side opposite to the first surface. The second surface includes an upper surface of the first metal portion and an upper surface of the second metal portion.

Abstract: The power module semiconductor device (2) includes: an insulating substrate (10); a first pattern (10a) (D) disposed on the insulating substrate (10); a semiconductor chip (Q) disposed on the first pattern; a power terminal (ST, DT) and a signal terminal (CS, G, SS) electrically connected to the semiconductor chip; and a resin layer (12) configured to cover the semiconductor chip and the insulating substrate. The signal terminal is disposed so as to be extended in a vertical direction with respect to a main surface of the insulating substrate.

Abstract: A semiconductor apparatus includes: a system substrate; a semiconductor package mounted on the system substrate and having a first length in a first horizontal direction; a conductive label flexible and arranged on the semiconductor package, the conductive label including: a first adhesive layer contacting the semiconductor package; a thermally-conductive layer attached to the semiconductor package by the first adhesive layer and having a second length in the first horizontal direction greater than the first length; and a second adhesive layer contacting a portion of a surface of the conductive layer, the portion not vertically overlapping the semiconductor package; a thermal interface material (TIM) arranged on the conductive layer to vertically overlap the semiconductor package; and a cover including: a first cover portion vertically overlapping the semiconductor package and contacting the TIM; and a second cover portion to which the thermally-conductive layer is attached by the second adhesive layer.

Abstract: A side wettable package includes a molding compound, a chip and multiple conductive pads exposed from a bottom surface of the molding compound. The conductive pads include peripheral conductive pads arranged near a side wall of the molding compound. Each of the peripheral conductive pads is over etched to form an undercut. When the side wettable package is connected to a circuit board via solder, the solder ascends to the undercut of the peripheral conductive pads for improving connection yield and facilitating inspection of soldering quality.

Abstract: Methods and systems for a semiconductor package with high routing density routing patch are disclosed and may include a semiconductor die bonded to a substrate and a high routing density patch bonded to the substrate and to the semiconductor die, wherein the high routing density patch comprises a denser trace line density than the substrate. The high routing density patch can be a silicon-less-integrated module (SLIM) patch, comprising a BEOL portion, and can be TSV-less. Metal contacts may be formed on a second surface of the substrate. A second semiconductor die may be bonded to the substrate and to the high routing density patch. The high routing density patch may provide electrical interconnection between the semiconductor die. The substrate may be bonded to a silicon interposer. The high routing density patch may have a thickness of 10 microns or less. The substrate may have a thickness of 10 microns or less.

Abstract: Systems and methods are disclosed for systems-in-packages that have multiple shielding components. In one embodiment, a system-in-package may include a substrate, an integrated circuit package disposed on the substrate, a system-on-a-chip disposed on the substrate, and a molding compound disposed over the integrated circuit package and the system-on-a-chip. The system-in-package may include a first electromagnetic interference shielding component disposed about the molding compound, and a second electromagnetic interference shielding component that at least partially forms an outer surface of the system-in-package. The second electromagnetic interference shielding component may have a patterned structure formed thereon.

Abstract: A semiconductor package includes a semiconductor chip structure that includes an image sensor chip and a logic chip that contact each other, a transparent substrate disposed on the semiconductor chip structure, and an adhesive structure disposed on an edge of the semiconductor chip structure and between the semiconductor chip structure and the transparent substrate. The adhesive structure includes a first adhesive segment disposed on a top surface of the semiconductor chip structure and a second adhesive segment disposed on a bottom surface of the transparent substrate. The second adhesive segment covers top and lateral surfaces of the first adhesive segment. The image sensor chip is closer to the transparent substrate than the logic chip.

Abstract: An external terminal electrode is attached to a frame, and the frame contains a first resin, and has a first adhered surface. A heat sink plate supports the frame, has an unmounted region where a power semiconductor element is to be mounted within the frame in plan view, is made of metal, and has a second adhered surface. An adhesive layer contains a second resin different from the first resin, and adheres the first adhered surface of the frame and the second adhered surface of the heat sink plate to each other. One of the first and second adhered surfaces includes a flat portion and a protruding portion. The protruding portion protrudes from the flat portion and opposes the other one of the first adhered surface and the second adhered surface with the adhesive layer therebetween.