Selection Of Materials, Or Shaping, To Facilitate Cooling Or Heating, E.g., Heat Sinks (epo) Patents (Class 257/E23.101)
  • Patent number: 10299389
    Abstract: In an example embodiment, a circuit interconnect includes a first printed circuit board (PCB), a second PCB, a spacer, and an electrically conductive solder joint. The first PCB includes a first electrically conductive pad. The second PCB includes a second electrically conductive pad. The spacer is configured to position the first PCB relative to the second PCB such that a space remains between the first PCB and the second PCB after the first electrically conductive pad and the second electrically conductive pad are conductively connected in a soldering process. The electrically conductive solder joint conductively connects the first electrically conductive pad and the second electrically conductive pad.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: May 21, 2019
    Assignee: FINISAR CORPORATION
    Inventor: Wei Shi
  • Patent number: 10242894
    Abstract: Apparatus, systems, and processes for substrate breakage detection in a thermal processing system are provided. In one example implementation, a process can include: accessing data indicative of a plurality of temperature measurements for a substrate, the plurality of measurements obtained during a cool down period of a thermal process; estimating one or more metrics associated with a cooling model based at least in part on the data indicative of the plurality of temperature measurements; and determining a breakage detection signal based at least in part on the one or more metrics associated with the cooling model. The breakage detection signal is indicative of whether the substrate has broken during thermal processing.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: March 26, 2019
    Assignee: Mattson Technology, Inc.
    Inventor: Joseph Cibere
  • Patent number: 10031562
    Abstract: A mechanism is provided for cooling electronic components of a printed circuit board module and for supplying power to the electronic components of the printed circuit board module. The computer module comprises a printed circuit board module, wherein the electronic components are attached to a first side of the printed circuit board module, and a cooling module being attached to a second side of the printed circuit board, being arranged in parallel to the printed circuit board and having a first layer being thermally and electrically conductive. The first layer is arranged such that heat is dissipated from the printed circuit board module and that power from a power source is supplied to the electronic components of the printed circuit board module.
    Type: Grant
    Filed: February 5, 2014
    Date of Patent: July 24, 2018
    Assignee: International Business Machines Corporation
    Inventors: Andreas C. Doering, Ronald P. Luijten, Bruno Michel, Stephan Paredes
  • Patent number: 9859004
    Abstract: A method is provided that includes forming a three-dimensional NAND stacked non-volatile memory array on a substrate, and forming a DRAM memory array on the substrate. The three-dimensional NAND stacked non-volatile memory array and the DRAM memory array are formed using a single integrated circuit fabrication process.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: January 2, 2018
    Assignee: SanDisk Technologies LLC
    Inventor: Johann Alsmeier
  • Patent number: 9768256
    Abstract: Embodiments of mechanisms for forming dislocations in source and drain regions of finFET devices are provided. The mechanisms involve recessing fins and removing the dielectric material in the isolation structures neighboring fins to increase epitaxial regions for dislocation formation. The mechanisms also involve performing a pre-amorphous implantation (PAI) process either before or after the epitaxial growth in the recessed source and drain regions. An anneal process after the PAI process enables consistent growth of the dislocations in the source and drain regions. The dislocations in the source and drain regions (or stressor regions) can form consistently to produce targeted strain in the source and drain regions to improve carrier mobility and device performance for NMOS devices.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: September 19, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Hsiung Tsai, Wei-Yuan Lu, Chien-Tai Chan, Wei-Yang Lee, Da-Wen Lin
  • Patent number: 9735018
    Abstract: Techniques for achieving extremely thin package structures are disclosed. In some embodiments, a device comprises an integrated circuit connected to a leadframe or substrate via connections and EMC (Epoxy Molding Compound) surrounding the integrated circuit except at a backside of the integrated circuit and connecting areas via which the integrated circuit is connected to the leadframe or substrate.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: August 15, 2017
    Assignee: Silego Technology, Inc.
    Inventors: Chia Chuan Chen, Lung-Pao Chin, I-Kuo Lin
  • Patent number: 9502337
    Abstract: Flip-chip on leadframe (FCOL) semiconductor packaging structure and fabrication method thereof are provided. A semiconductor chip with copper pillars formed there-over is provided. A barrier layer is formed on the copper pillars. A solder material is coated on the barrier layer. A layer of soldering flux is coated on the solder material. A leadframe with electric leads formed thereon is provided. An insulating layer is formed an the leadframe and having a plurality of openings to expose portion of the electric leads. The semiconductor chip is placed upside down onto the leadframe to have the soldering flux in contact with the portion of the electric leads exposed in the openings. The solder material flows back to form conductive interconnections between the copper pillars and the portion of the electric leads exposed in the openings. The semiconductor chip is packaged with the leadframe using a mold compound.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: November 22, 2016
    Assignee: NANTONG FUJITSU MICROELECTRONICS CO., LTD.
    Inventor: Lei Shi
  • Patent number: 9398726
    Abstract: A heat-dissipating base is provided. The heat-dissipating base includes a main body and at least one first protrusion. The first protrusion is disposed on the main body. The first protrusion has at least one first protrusion top surface for thermally contacting at least one first component above the main body.
    Type: Grant
    Filed: November 23, 2014
    Date of Patent: July 19, 2016
    Assignee: DELTA ELECTRONICS (SHANGHAI) CO., LTD.
    Inventors: Pei-Ai You, Xing-Xian Lu, Gang Liu, Jin-Fa Zhang
  • Patent number: 9350356
    Abstract: According to one embodiment, a reconfigurable circuit includes first, second, third and fourth circuit blocks arranged with a matrix, a first conductive line shared by the first and second circuit blocks, a second conductive line shared by the third and fourth circuit blocks, a third conductive line shared by the first and third circuit blocks, the third conductive line crossing the first and second conductive lines, a fourth conductive line shared by the second and fourth circuit blocks, the fourth conductive line crossing the first and second conductive lines, a first controller controlling voltages to be applied to the first and second conductive lines, and a second controller controlling voltages to be applied to the third and fourth conductive lines.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: May 24, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kosuke Tatsumura, Masato Oda, Koichiro Zaitsu, Shinichi Yasuda
  • Patent number: 9034695
    Abstract: A method includes attaching a wafer on a carrier through an adhesive, and forming trenches in the carrier to convert the carrier into a heat sink. The heat sink, the carrier, and the adhesive are sawed into a plurality of packages.
    Type: Grant
    Filed: April 11, 2012
    Date of Patent: May 19, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Chieh Hsieh, Shang-Yun Hou, Shin-Puu Jeng
  • Patent number: 8981554
    Abstract: A lower package includes a semiconductor chip. A first upper package and a second upper package are disposed on the lower package. A heat spreader is disposed on the lower package. The heat spreader includes an upper plate and an extension part connected to the upper plate. At least a part of each of the first and second upper packages vertically overlaps the semiconductor chip. The upper plate may be arranged on the first upper package and the second upper package. The extension part may be arranged between the first upper package and the second upper package. The extension part has a vertical height that is greater than its horizontal width.
    Type: Grant
    Filed: November 14, 2013
    Date of Patent: March 17, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Hyun-Ki Kim
  • Patent number: 8981553
    Abstract: A power semiconductor module includes a first printed circuit board having a first insulation carrier, and a first upper metallization and a first lower metallization applied to the first insulation carrier on mutually opposite sides, and a second printed circuit board having a second insulation carrier and a second upper metallization applied to the second insulation carrier. The second printed circuit board is spaced apart from the first printed circuit board in a vertical direction oriented perpendicular to the opposite sides of the first insulation carrier. A semiconductor chip is disposed between the printed circuit boards and electrically conductively connected at least to the second upper metallization. The first lower metallization and the second upper metallization face one another. The first printed circuit board has a first thick conductor layer at least partly embedded in the first insulation carrier and which has a thickness of at least 100 ?m.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: March 17, 2015
    Assignee: Infineon Technologies AG
    Inventors: Ulrich Michael Georg Schwarzer, Daniel Bolowski
  • Patent number: 8975670
    Abstract: A semiconductor device, including: a semiconductor substrate with a first layer including first transistors; a shield layer overlaying the first layer; a second layer overlaying the shield layer, the second layer including second transistors; wherein the shield layer is a mostly continuous layer with a plurality of regions for connections between the first transistors and the second transistors, and where the second transistors include monocrystalline regions.
    Type: Grant
    Filed: July 22, 2012
    Date of Patent: March 10, 2015
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
  • Patent number: 8970030
    Abstract: The invention relates to an electronic module and to a method for producing same, comprising a mold body (2), a first circuit carrier (3; 13) having a first inner face (3a; 13a), on which electronic components (5) are arranged, and a first outer face (3b; 13b), a second circuit carrier (4; 14) having a second inner face (4a; 14a), on which electronic components (5) are arranged, and a second outer face (4b; 14b), and at least one spring device (6, 7; 16) which connects the inner faces (3a, 14a; 13a, 14a), or surfaces of electronic components (5) arranged thereon, of the first and second circuit carriers (3, 4; 13, 14), wherein the first and second outer faces (3a, 4a; 13a, 14a) are exposed towards the outside of the electronic module in order to emit heat directly to the outside, and wherein the first and second outer faces (3a, 4a; 13a, 14a) are parallel to each other.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: March 3, 2015
    Assignee: Robert Bosch GmbH
    Inventor: Matthias Keil
  • Patent number: 8963323
    Abstract: An apparatus 100 comprising a first substrate 130 having a first surface 125, a second substrate 132 having a second surface 127 facing the first surface and an array 170 of metallic raised features 170 being located on the first surface, each raised feature being in contact with the first surface to the second surface, a portion of the raised features being deformed via a compressive force 305.
    Type: Grant
    Filed: June 20, 2008
    Date of Patent: February 24, 2015
    Assignee: Alcatel Lucent
    Inventors: Roger Scott Kempers, Shankar Krishnan, Alan Michael Lyons, Todd Richard Salamon
  • Patent number: 8963321
    Abstract: A semiconductor device includes a semiconductor chip joined with a substrate and a base plate joined with the substrate. The base plate includes a first metal layer clad to a second metal layer. The second metal layer is deformed to provide a pin-fin or fin cooling structure. The second metal layer has a sub-layer that has no pins and no pin-fins. The first metal layer has a first thickness and the sub-layer has a second thickness. The ratio between the first thickness and the second thickness is at least 4:1.
    Type: Grant
    Filed: January 24, 2013
    Date of Patent: February 24, 2015
    Assignee: Infineon Technologies AG
    Inventors: Andreas Lenniger, Andre Uhlemann, Olaf Hohlfeld
  • Patent number: 8941232
    Abstract: The mechanisms for forming metal bumps to connect to a cooling device (or a heat sink) described herein enable substrates with devices to dissipate heat generated more efficiently. In addition, the metal bumps allow customization of bump designs to meet the needs of different chips. Further, the usage of metal bumps between the semiconductor chip and cooling device enables advanced cooling by passing a cooling fluid between the bumps.
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: January 27, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: You-Hua Chou, Yi-Jen Lai, Chun-Jen Chen, Perre Kao
  • Patent number: 8941234
    Abstract: A method includes preparing a bonding surface of a heat dissipating member, applying flux to the bonding surface of the heat dissipating member, and removing excess flux from the bonding surface so that minimal flux is provided. The method also includes preparing a die surface of an electronic device package, applying flux to the die surface, and removing excess flux from the die surface so that minimal flux is provided. The method further includes positioning a preform solder component on the die surface, positioning the heat dissipating member over the die surface and the preform solder component such that the flux layer of the bonding surface is in contact with the preform solder component, and reflowing the solder component using a reflow oven. A heat spreader is also described for use in the process.
    Type: Grant
    Filed: April 1, 2014
    Date of Patent: January 27, 2015
    Assignee: DY 4 Systems, Inc.
    Inventors: Ivan Straznicky, Peter Robert Lawrence Kaiser, Steven Drennan, Marc-Jason Renaud, Georges Francis Marquis
  • Patent number: 8933559
    Abstract: Disclosed are embodiments of an improved semiconductor wafer structure having protected clusters of carbon nanotubes (CNTs) on the back surface and a method of forming the improved semiconductor wafer structure. Also disclosed are embodiments of a semiconductor module with exposed CNTs on the back surface for providing enhanced thermal dissipation in conjunction with a heat sink and a method of forming the semiconductor module using the disclosed semiconductor wafer structure.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: January 13, 2015
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, Charles W. Koburger, III, Krishna V. Singh
  • Patent number: 8933557
    Abstract: A semiconductor module including a cooling unit by which a fine cooling effect is obtained is provided. A plurality of cooling flow paths (21c) which communicate with both of a refrigerant introduction flow path which extends from a refrigerant introduction inlet and a refrigerant discharge flow path which extends to a refrigerant discharge outlet are arranged in parallel with one another in a cooling unit (20). Fins (22) are arranged in each cooling flow path (21c). Semiconductor elements (32) and (33) are arranged over the cooling unit (20) so that the semiconductor elements (32) and (33) are thermally connected to the fins (22). By doing so, a semiconductor module (10) is formed. Heat generated by the semiconductor elements (32) and (33) is conducted to the fins (22) arranged in each cooling flow path (21c) and is removed by a refrigerant which flows along each cooling flow path (21c).
    Type: Grant
    Filed: July 28, 2010
    Date of Patent: January 13, 2015
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Hiromichi Gohara, Akira Morozumi, Keiichi Higuchi
  • Patent number: 8921998
    Abstract: A semiconductor module has a pair of semiconductor devices, a heat sink, a first electrode, an output electrode and a second electrode. The semiconductor devices are connected in series with each other and have first terminals that are electrically connected to a first power system and a second terminal that is electrically connected to a second power system. The first electrode is electrically connected both to one of the first terminal and to an electrode of one of the semiconductor devices. The output electrode is electrically connected both to the second terminal and to an electrode of the other of the semiconductor device. The second electrode is electrically connected to the other of the first terminals. The second electrode is connected to the heat sink via a first insulating member. The output electrode is connected to the second electrode via a second insulating member.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: December 30, 2014
    Assignees: Nissan Motor Co., Ltd., Sanken Electric Co., Ltd., Fuji Electric Co., Ltd.
    Inventors: Yusuke Zushi, Yoshinori Murakami, Satoshi Tanimoto, Shinji Sato, Kohei Matsui
  • Patent number: 8912670
    Abstract: An example includes a die package including a microelectronic die having a lower die surface, an upper die surface parallel to the lower die surface, and a die side, the microelectronic die including an active region and an inactive region. The example optionally includes a heat spreader having a lower heat spreader surface, an upper heat spreader surface parallel to the lower heat spreader surface, and at least one heat spreader side, the heat spreader disposed on the upper surface of the microelectronic die in thermal communication with the inactive region of the die and electrically insulated from the active region. The example optionally includes an encapsulation material encapsulating the die side and the heat spreader side and lower heat spreader surface, the encapsulation material including a lower surface substantially parallel to the die lower surface and an upper surface substantially parallel to the die upper surface.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: December 16, 2014
    Assignee: Intel Corporation
    Inventors: Weng Hong Teh, Deepak Kulkarni, Chia-Pin Chiu, Tannaz Harirchian, John S. Guzek
  • Patent number: 8890314
    Abstract: An electronic component includes a high voltage switching transistor encased in a package. The high voltage switching transistor comprises a source electrode, a gate electrode, and a drain electrode all on a first side of the high voltage switching transistor. The source electrode is electrically connected to a conducting structural portion of the package. Assemblies using the abovementioned transistor with another transistor can be formed, where the source of one transistor can be electrically connected to a conducting structural portion of a package containing the transistor and a drain of the second transistor is electrically connected to the second conductive structural portion of a package that houses the second transistor. Alternatively, the source of the second transistor is electrically isolated from its conductive structural portion, and the drain of the second transistor is electrically isolated from its conductive structural portion.
    Type: Grant
    Filed: October 25, 2013
    Date of Patent: November 18, 2014
    Assignee: Transphorm, Inc.
    Inventor: Yifeng Wu
  • Patent number: 8890310
    Abstract: A power module package includes a power circuit element, a control circuit element, a lead frame, an aluminum oxide substrate having a heat sink and an insulation layer, and a sealing resin. The control circuit element is electrically connected with the power circuit element to control chips within the power circuit element. The lead frame has external connection terminal leads in its edge and has a first surface to which the power circuit element and the control circuit element are attached and a second surface which is used as a heat transmission path. The heat sink is a plate made of metal such as aluminum and the electrical insulation layer is formed at least on an upper surface of the heat sink and made of aluminum oxide. The electrical insulation layer may be formed over an entire surface of the heat sink. Here, the insulation layer is attached to the second surface by an adhesive, on a region below where the power circuit element is attached, to the first surface of the lead frame.
    Type: Grant
    Filed: March 24, 2010
    Date of Patent: November 18, 2014
    Assignee: Fairchild Korea Semiconductor, Ltd.
    Inventors: Keunhyuk Lee, Oseob Jeon, Seungwon Lim
  • Patent number: 8890306
    Abstract: A light-emitting diode includes a carrier with a mounting face and includes a metallic basic body and at least two light-emitting diode chips affixed to the carrier at least indirectly at the mounting face, wherein an outer face of the metallic basic body includes the mounting face, the at least two light-emitting diode chips connect in parallel with one another, the at least two light-emitting diode chips are embedded in a reflective coating, the reflective coating covering the mounting face and side faces of the light-emitting diode chips, and the light-emitting diode chips protrude with their radiation exit surfaces out of the reflective coating, and the radiation exit surfaces face away from the carrier.
    Type: Grant
    Filed: May 24, 2011
    Date of Patent: November 18, 2014
    Assignee: OSRAM Opto Semiconductor GmbH
    Inventors: Joachim Reill, Georg Bogner, Stefan Grötsch
  • Patent number: 8877566
    Abstract: A heat spreader or lid for a microelectronic package, in which the heat spreader has an underside surface that includes at least one curvilinear contour, in which the curvilinear contour is selected from at least one positive or protruding curvilinear feature, at least one negative or recessed curvilinear feature, and a combination thereof. A microelectronic package that includes the heat spreader/lid, in which there is improved heat dissipation or reduced mechanical stress in an interface between the heat spreader/lid and a circuit chip.
    Type: Grant
    Filed: August 15, 2012
    Date of Patent: November 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Michael A. Gaynes, Maurice McGlashan-Powell, Soojae Park, Edward J. Yarmchuk
  • Patent number: 8872330
    Abstract: A thin-film semiconductor component having a carrier layer and a layer stack which is arranged on the carrier layer, the layer stack containing a semiconductor material and being provided for emitting radiation, wherein a heat dissipating layer provided for cooling the semiconductor component is applied on the carrier layer. A component assembly is also disclosed.
    Type: Grant
    Filed: July 16, 2007
    Date of Patent: October 28, 2014
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Siegfried Herrmann, Berthold Hahn
  • Patent number: 8866183
    Abstract: An LED module includes: a package having electrodes provided on the outer surface of opposing sidewalls, and a light-emitting element connected to the electrodes and mounted on the package; a base member having a copper metal; an insulating layer stacked on the surface of the base member and having an insulating material; and a conductive wiring pattern connected to the electrodes by soldering and formed on the surface of the insulating layer. The insulating layer has a through-hole formed by removing a part of the section where the package is positioned, and a heat dissipation unit formed by soldering between the back surface of the package and the base member, which face one another with the through-hole interposed therebetween.
    Type: Grant
    Filed: September 26, 2011
    Date of Patent: October 21, 2014
    Assignee: Panasonic Industrial Devices Sunx Co., Ltd.
    Inventors: Sachio Higuchi, Takashi Tanaka, Mitunori Mizoguti, Tsuyoshi Inui, Atsuo Fukuda
  • Patent number: 8866294
    Abstract: A semiconductor device has a semiconductor die with a plurality of bumps formed over a surface of the first semiconductor die. A penetrable adhesive layer is formed over a temporary carrier. The adhesive layer can include a plurality of slots. The semiconductor die is mounted to the carrier by embedding the bumps into the penetrable adhesive layer. The semiconductor die and interconnect structure can be separated by a gap. An encapsulant is deposited over the first semiconductor die. The bumps embedded into the penetrable adhesive layer reduce shifting of the first semiconductor die while depositing the encapsulant. The carrier is removed. An interconnect structure is formed over the semiconductor die. The interconnect structure is electrically connected to the bumps. A thermally conductive bump is formed over the semiconductor die, and a heat sink is mounted to the interconnect structure and thermally connected to the thermally conductive bump.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: October 21, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, Yaojian Lin, Jun Mo Koo
  • Patent number: 8836104
    Abstract: Various stress relief structures are provided for effectively reducing thermal stress on a semiconductor chip in a chip package. Trenches on a metal substrate are created in groups in two-dimension, where each trench is opened from top or bottom surface of the metal substrate and in various shapes. The metal substrate is partitioned into many smaller substrates depending on the number of trench groups and partitions, and is attached to a semiconductor chip for stress relief. In an alternative embodiment, a plurality of cylindrical metal structures are used together with a metal substrate in a chip package for the purpose of heat removal and thermal stress relief on a semiconductor chip. In another alternative embodiment, a metal foam is used together with a semiconductor chip to create a chip package. In another alternative embodiment, a semiconductor chip is sandwiched between a heat sink and a circuit board by solder bumps directly with underfill on the circuit board.
    Type: Grant
    Filed: March 3, 2012
    Date of Patent: September 16, 2014
    Inventor: Ho-Yuan Yu
  • Patent number: 8836110
    Abstract: A packaged semiconductor device includes a package substrate, an integrated circuit (IC) die mounted on the package substrate, and a heat spreader mounted on the package substrate. The heat spreader surrounds at least a portion of the IC die and includes a lid with a plurality of openings. An inner portion of the heat spreader includes a plurality of thermally conductive protrusions adjacent the die.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: September 16, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Sheila F. Chopin, Varughese Mathew
  • Patent number: 8810026
    Abstract: A semiconductor module which includes a semiconductor device; a wiring member that is connected to the semiconductor device; a cooling plate that includes a first surface on a side of the semiconductor device and a second surface on a side opposite to the first surface and has a fastening portion at an end thereof in a first direction; and a molded portion that is formed by molding a resin on the semiconductor device, the wiring member and the cooling plate, wherein the fastening portion is exposed out of the molded portion, and a terminal portion of the wiring member is exposed out of the molded portion such that the terminal portion of the wiring member extends in a second direction which is substantially perpendicular to the first direction.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: August 19, 2014
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Takuya Kadoguchi, Yoshikazu Suzuki, Masaya Kaji, Kiyofumi Nakajima, Tatsuya Miyoshi, Takanori Kawashima, Tomomi Okumura
  • Patent number: 8796840
    Abstract: A semiconductor assembly includes a first subassembly comprising a heat sink and a first patterned polymer layer disposed on a surface of the heat sink to define an exposed portion of the first surface. The exposed portion of the first surface extends radially inward along the heat sink surface from the first layer. The subassembly also includes a second patterned polymer layer disposed on a radially outer portion of the first patterned polymer layer. The first and second layers define a cell for accommodating a power semiconductor die. Solder material is disposed on the exposed portion of the heat sink surface and in the cell. A power semiconductor die is located within the cell on a radially inward portion of the first layer and thermally coupled to the heat sink by the solder material.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: August 5, 2014
    Assignee: Vishay General Semiconductor LLC
    Inventors: Wan-Lan Chiang, Kuang Hann Lin, Chih-Ping Peng
  • Patent number: 8796832
    Abstract: A wiring device for a semiconductor device, a composite wiring device for a semiconductor device and a resin-sealed semiconductor device are provided, each of which is capable of mounting thereon a semiconductor chip smaller than conventional chips and being manufactured at lower cost. The wiring device connects an electrode on a semiconductor chip with an external wiring device, and has an insulating layer, a metal substrate and a copper wiring layer. The wiring device has a semiconductor chip support portion provided on the side of the copper wiring layer with respect to the insulating layer. The copper wiring layer includes a first terminal, a second terminal and a wiring portion. The first terminal is connected with the electrode. The second terminal is connected with the external wiring device. The wiring portion connects the first terminal with the second terminal.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: August 5, 2014
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Susumu Baba, Masachika Masuda, Hiromichi Suzuki
  • Patent number: 8786067
    Abstract: A semiconductor package having a structure in which heat produced in the interior of the package is effectively spread to the outside of the package is provided. The semiconductor package includes one or more semiconductor chips, one or more substrates (PCBs) having the semiconductor chips respectively attached thereto, a plurality of conductive balls such as a plurality of solder balls to provide voltages and signals to the one or more semiconductor chips, and a heat sink positioned to spread heat produced in the interior of the package to the outside and directly connected to at least one of the plurality of solder balls.
    Type: Grant
    Filed: April 18, 2011
    Date of Patent: July 22, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Soo-Jin Paek, Woo-Seop Kim, Ki-Sung Kim
  • Patent number: 8779578
    Abstract: A multi-chip socket includes multiple cavities. The multiple cavities include support surfaces. The support surfaces may be disposed at different heights relative to a reference plane. The different heights may be based on a height of a first component to be disposed in the first cavity and a height of a second component to be disposed in a second cavity.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: July 15, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Kevin B. Leigh, George D. Megason
  • Patent number: 8779572
    Abstract: A three dimensional (3D) stacked chip structure with chips having on-chip heat spreader and method of forming are described. A 3D stacked chip structure comprises a first die having a first substrate with a dielectric layer formed on a front surface. One or more bonding pads and a heat spreader may be simultaneously formed in the dielectric layer. The first die is bonded with corresponding bond pads on a surface of a second die to form a stacked chip structure. Heat generated in the stacked chip structure may be diffused to the edges of the stacked chip structure through the heat spreader.
    Type: Grant
    Filed: November 5, 2013
    Date of Patent: July 15, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuan-Yi Lin, Ching-Chen Hao, Chen Cheng Chou, Sheng-Yuan Lin
  • Patent number: 8749052
    Abstract: An electric device with an insulating substrate consisting of an insulating layer and at least one metallization on a surface side of the insulating layer, the metallization being structured and having an electric component on the metallization. The metallization has a layer thickness that is stepped and is greater in an area adjoining the component.
    Type: Grant
    Filed: June 29, 2010
    Date of Patent: June 10, 2014
    Assignee: Curamik Electronics GmbH
    Inventors: Jürgen Schulz-Harder, Andreas Meyer
  • Patent number: 8742563
    Abstract: A component and a method for producing a component are disclosed. The component comprises an integrated circuit, a housing body, a wiring device overlapping the integrated circuit and the housing body, and one or more external contact devices in communication with the wiring device.
    Type: Grant
    Filed: November 29, 2010
    Date of Patent: June 3, 2014
    Assignee: Intel Mobile Communications GmbH
    Inventors: Thorsten Meyer, Harry Hedler, Markus Brunnbauer
  • Patent number: 8736047
    Abstract: A semiconductor device includes: a semiconductor substrate; a heat sink mounted on an upper surface of the semiconductor substrate; wirings formed on a lower surface of the semiconductor substrate; and the like. The heat sink is mounted on the upper surface of the semiconductor substrate, and a planar size thereof is approximately the same as that of the semiconductor substrate. Moreover, the heat sink has a thickness of 500 ?m to 2 mm, and may be formed to be thicker than the semiconductor substrate. By using the heat sink to reinforce the substrate, a thickness of the semiconductor substrate can be reduced to, for example, about 50 ?m. As a result, a thickness of the entire semiconductor device can be reduced.
    Type: Grant
    Filed: March 28, 2007
    Date of Patent: May 27, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Hideaki Yoshimi, Mitsuo Umemoto, Kazumi Onda, Kazumi Horinaka
  • Patent number: 8703536
    Abstract: An integrated heat spreader (IHS) lid over a semiconductor die connected to a substrate forms a cavity. A bead of foaming material may be placed within the IHS cavity. During an IHS cure and reflow process the foaming material will expand and fill the IHS cavity and the foam's shape conforms to the various surface features present, encapsulating a thermal interface material (TIM) material, and increasing contact area of the foam sealant.
    Type: Grant
    Filed: June 7, 2013
    Date of Patent: April 22, 2014
    Assignee: Intel Corporation
    Inventors: Paul R. Start, Rahul N. Manepalli
  • Patent number: 8703540
    Abstract: A method of packaging one or more semiconductor dies includes: providing a first die having a circuit surface and a connecting surface; providing a chip-scale frame having an inside surface and an outside surface, the chip-scale frame having a well region having an opening in the inside surface; coupling the first die to a wall of the well region using a first coupling mechanism for electrical and mechanical coupling; providing a substrate having a top surface and a bottom surface; coupling the inside surface of the chip-scale frame with the top surface of the substrate by a second coupling mechanism, wherein a gap is provided between the circuit surface of the first die and the top surface of the substrate; coupling a heat sink to the outside surface of the chip-scale frame; attaching a lid to the chip-scale frame to form a substantially airtight chamber around the first die.
    Type: Grant
    Filed: January 15, 2013
    Date of Patent: April 22, 2014
    Assignee: Semtech Corporation
    Inventors: Andrew J. Bonthron, Darren Jay Walworth
  • Patent number: 8698161
    Abstract: A semiconductor structure is bonded directly to a diamond substrate by Van der Waal forces. The diamond substrate is formed by polishing a surface of diamond to a first degree of smoothness; forming a material, such as diamond, BeO, GaN, MgO, or SiO2 or other oxides, over the polished surface to provide an intermediate structure; and re-polishing the material formed on the intermediate structure to a second degree of smoothness smoother than the first degree of smoothness. The diamond is bonded to the semiconductor structure, such as GaN, by providing a structure having bottom surfaces of a semiconductor on an underlying material; forming grooves through the semiconductor and into the underlying material; separating semiconductor along the grooves into a plurality of separate semiconductor structures; removing the separated semiconductor structures from the underlying material; and contacting the bottom surface of at least one of the separated semiconductor structures to the diamond substrate.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: April 15, 2014
    Assignee: Raytheon Company
    Inventors: Ralph Korenstein, Mary K. Herndon, Chae Doek Lee
  • Patent number: 8679899
    Abstract: A Thermal Interface Material (“TIM”) composition of matter with improved heat conductivity comprises solderable heat-conducting particles in a bondable resin matrix and at least some of the solderable heat-conducting particles comprise a solder surface. Positioning the TIM between a first surface having a solder adhesion layer and a second surface, and then heating it results in soldering some of the solderable heat-conducting particles to one another; and some to the solder-adhesion layer on the first surface as well as adhesively bonding the resin matrix to the first surface and the second surface. The first surface can comprise an electronic device, e.g., a semiconductor device and the second surface a heat sink, such as a solderable heat sink. A product comprises an article of manufacture made by the process.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: March 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: George Liang-Tai Chiu, Sung-Kwon Kang
  • Patent number: 8664758
    Abstract: A semiconductor package includes a printed circuit board, a chip, a protection frame, and a covering layer. The chip is mounted on the printed circuit board and is electrically connected to the printed circuit board through a number of first bonding wires. The protection frame includes a sidewall surrounding the chip and the bonding wires and defines a number of through holes passing through an inner surface and an outer surface of the sidewall. The protection frame is filled with adhesive. The adhesive adheres to the inner surface and covers the chip and the boding wires. The covering layer is coated on the outer surface and covers the through holes.
    Type: Grant
    Filed: August 8, 2012
    Date of Patent: March 4, 2014
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventor: Chih-Chen Lai
  • Patent number: 8653652
    Abstract: A semiconductor device includes: a case with an opening formed thereat; a semiconductor element housed inside the case; a first conductor plate housed inside the case and positioned at one surface side of the semiconductor element; a second conductor plate housed inside the case and positioned at another surface side of the semiconductor element; a positive bus bar electrically connected to the first conductor plate, through which DC power is supplied; a negative bus bar electrically connected to the second conductor plate, through which DC power is supplied; a first resin member that closes off the opening at the case; and a second resin member that seals the semiconductor element, the first conductor plate and the second conductor plate and is constituted of a material other than a material constituting the first resin member.
    Type: Grant
    Filed: August 24, 2010
    Date of Patent: February 18, 2014
    Assignee: Hitachi Automotive Systems, Ltd.
    Inventors: Takeshi Tokuyama, Kinya Nakatsu, Ryuichi Saito, Toshiya Satoh, Hideaki Ishikawa, Nobutake Tsuyuno, Shigeo Amagi
  • Patent number: 8648478
    Abstract: A heat sink includes a first adhesive layer, and a heat dissipation layer disposed on the first adhesive layer, and has ventilation ports that extend therethrough including through the first adhesive layer and the heat dissipation layer. The heat sink forms an outermost part of a semiconductor package. Thus, when the heat sink is bonded via its adhesive layer to underlying structure during a manufacturing process, the ventilation ports allow air to pass therethrough. As a result, air is not trapped in the form of bubbles between the heat sink and the underlying structure.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: February 11, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Wook Yoo, Kyoung-Sei Choi, Eun-Seok Cho, Mi-Na Choi, Hee-Jung Hwang, Se-Ran Bae
  • Patent number: 8633597
    Abstract: In a multi-module integrated circuit package having a package substrate and package contacts, a die is embedded in the package substrate with thermal vias that couple hotspots on the embedded die to some of the package contacts.
    Type: Grant
    Filed: March 1, 2010
    Date of Patent: January 21, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Fifin Sweeney, Milind P. Shah, Mario Francisco Velez, Damion B. Gastelum
  • Patent number: 8618653
    Abstract: An integrated circuit package system includes: providing a singulated, layered structure equivalent in size to an integrated circuit die and having an adhesive layer, an electrical insulator layer, and a heat slug; attaching the integrated circuit die to a base; attaching bond wires to a top of the base for electrical connection between the integrated circuit die and the base; attaching the singulated, layered structure to the integrated circuit die wherein the bond wires are surrounded by the adhesive layer; and encapsulating the integrated circuit die and a portion of the heat slug with a molding compound.
    Type: Grant
    Filed: January 30, 2008
    Date of Patent: December 31, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: WonJun Ko, Taeg Ki Lim, Sungmin Song
  • Patent number: 8618585
    Abstract: A semiconductor apparatus according to embodiments of the invention can include a first semiconductor device made of silicon, the first semiconductor devices being arranged collectively, whereby to form a first device group, and a second semiconductor device made of silicon carbide, the second semiconductor devices being arranged collectively, whereby to form a second device group. The apparatus can also include a wiring conductor connecting the first semiconductor device and the second semiconductor device, a cooling fin base comprising a projection formed thereon, whereby to dissipate heat generated from the first and second semiconductor devices, and the projections arranged under the second device group being spaced apart from each other more widely than the projections arranged under the first device group.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: December 31, 2013
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Kenichiro Sato