Abstract: A semiconductor package structure including a package substrate, at least one semiconductor die, a lid structure, a first electronic component and a heat sink is provided. The package substrate has a first surface and a second surface opposite to the first surface. The semiconductor die is on the first surface of the package substrate and is surrounded by an encapsulating layer. The lid structure surrounds and is spaced apart from the encapsulating layer. The lid structure includes a first opening that is covered by the first surface of the package substrate. The first electronic component is over the first surface of the package substrate and arranged within the first opening of the lid structure. The heat sink covers the lid structure and the semiconductor die.

Abstract: Disclosed is a semiconductor package including a base film that has a first surface and a second surface opposite to the first surface, a plurality of input/output lines on the first surface of the base film, a semiconductor chip disposed on the first surface of the base film and connected to the input/output lines and including a central portion and end portions on opposite sides of the central portion, and a heat radiation pattern on the second surface of the base film. The heat radiation pattern corresponds to the semiconductor chip and has a plurality of openings that correspond to the end portions of the semiconductor chip and that vertically overlap the end portions of the semiconductor chip.

Abstract: A semiconductor device package and a method for manufacturing a semiconductor device package are provided. The semiconductor device package includes a substrate, a clip, and a support structure. The clip is disposed on the substrate. The clip includes a first portion and a second portion separated from each other by a slit. The support structure is above the substrate and supports the clip. The support structure has a first surface and a second surface facing the first surface, and the first surface and the second surface define a gap.

Abstract: A package structure and a formation method of a package structure are provided. The package structure includes a circuit substrate and a die package bonded to the circuit substrate through bonding structures. The package structure also includes a warpage-control element attached to the circuit substrate. The warpage-control element has a protruding portion extending into the circuit substrate. The warpage-control element has height larger than that of the die package.

Abstract: A semiconductor package is provided. The semiconductor package comprises a first substrate, a second substrate disposed on the first substrate, a first semiconductor chip disposed on the second substrate, and a stiffener extending from an upper surface of the first substrate to an upper surface of the second substrate, the stiffener not being in contact with the first semiconductor chip, wherein a first height from the upper surface of the first substrate to an upper surface of the first semiconductor chip is greater than a second height from the upper surface of the first substrate to an uppermost surface of the stiffener.

Abstract: A semiconductor device, including a capacitor, a semiconductor module having a first power terminal formed on a front surface of a first insulating member, and a connecting member electrically connecting and mechanically coupling the semiconductor module and the capacitor to each other, the connecting member having a front surface and a rear surface opposite to each other, the rear surface being on a front surface of the first power terminal. The connecting member is bonded to the semiconductor module via a first welded portion, which penetrates the front and rear surfaces of the connecting member, and penetrates the front surface of the first power terminal, in a thickness direction of the semiconductor device, a distance in the thickness direction between a bottommost portion of first welded portion and the front surface of the first insulating member being 0.3 mm or more.

Abstract: A circuit board includes a composite structure layer, at least one conductive structure, a thermally conductive substrate, and a thermal interface material layer. The composite structure layer has a cavity and includes a first structure layer, a second structure layer, and a connecting structure layer. The first structure layer includes at least one first conductive member, and the second structure layer includes at least one second conductive member. The cavity penetrates the first structure layer and the connecting structure layer to expose the second conductive member. The conductive structure at least penetrates the connecting structure layer and is electrically connected to the first conductive member and the second conductive member. The thermal interface material layer is disposed between the composite structure layer and the thermally conductive substrate, and the second structure layer is connected to the thermally conductive substrate through the thermal interface material layer.

Abstract: A high-frequency module includes a mounting substrate having main surfaces 30a and 30b, a first circuit component mounted on the main surface 30a, a second circuit component mounted on the main surface 30b, an external connection terminal arranged on the main surface 30b side relative to the main surface 30a with respect to the mounting substrate, a long via conductor connected to the first circuit component, passing through the mounting substrate, and having a substantially long shape when the mounting substrate is viewed in a plan view, and a metal block arranged on the main surface 30b side relative to the main surface 30a with respect to the mounting substrate and connecting the long via conductor and the external connection terminal. When the mounting substrate is viewed in a plan view, the first circuit component overlaps the long via conductor and the metal block overlaps the long via conductor.

Abstract: Techniques for wafer-scale memory device and systems are provided. In an example, a wafer-scale memory device can include a large single substrate, multiple memory circuit areas including dynamic random-access memory (DRAM), the multiple memory circuit areas integrated with the substrate and configured to form an array on the substrate, and multiple streets separating the memory circuit areas. The streets can accommodate attaching the substrate to a wafer-scale processor. In certain examples, the large, single substrate can have a major surface area of more than 20,000 square millimeters (mm2).

Abstract: Aspects of the invention include a non-destructive bond line thickness measurement of thermal interface material on silicon packages. A non-limiting example computer-implemented method includes receiving a chip mounted on a laminate and depositing a high-density material on the chip. The computer-implemented method deposits a thermal interface material on the chip and lids the chip, and the laminate with a lid. The computer-implemented method X-rays the lid, the chip, and the laminate to produce an X-ray and measures, using a processor, from the X-ray a bond line thickness of the TIM as a distance from a bottom of the lid to a top surface of the high-density material.

Abstract: A backlight module includes a flexible circuit board and a light guide plate. A first light source assembly, a second light source assembly, and a positioning member are disposed on the flexible circuit board. The light guide plate is disposed over the flexible circuit board and includes a first single key light guide area, a second single key light guide area, and a connection area. The first single key light guide area has a first through hole accommodating the first light source assembly. The second single key light guide area has a second through hole accommodating the second light source assembly. The connection area is located between the first and second single key light guide areas and has an accommodating hole. The flexible circuit board is overlapped with the light guide plate with the positioning member being accommodated in the accommodating hole.

Abstract: A high efficiency satellite transmitter comprises an RF amplifier chip in thermal contact with a radiant cooling element via a heat conducting element. The RF amplifier chip comprises an active layer disposed on a high thermal conductivity substrate having a thermal conductivity greater than about 1000 W/mK, maximizing heat conduction out of the RF amplifier chip and ultimately into outer space when the chip is operating within a satellite under normal transmission conditions. In one embodiment, the active layer comprises materials selected from the group consisting of GaN, InGaN, AlGaN, and InGaAlN alloys. In one embodiment, the high thermal conductivity substrate comprises synthetic diamond.

Abstract: An apparatus for testing integrated circuits (ICs) , includes a first thermal contact structure having a first surface to interface with a heat source and an opposing second surface to interface with a device under test (DUT). A second thermal contact structure is above the first thermal contact structure and separated therefrom by a variable-resistance thermal interface (VRTI) structure operable to couple or decouple the first and second thermal contact structures from one another. The VRTI structure has a maximal thermal conductivity associated with a first state, and a minimal thermal conductivity associated with a second state.

Abstract: A semiconductor device includes a substrate, an electronic component, a ring structure and an adhesive layer. The substrate has a first surface. The electronic component is over the first surface of the substrate. The ring structure is over the first surface of the substrate, wherein the ring structure includes a first part having a first height, and a second part recessed from the bottom surface and having a second height lower than the first height. The adhesive layer is interposed between the first part of the ring structure and the substrate, and between the second part of the ring structure and the substrate.

Abstract: The present disclosure, in some embodiments, relates to a semiconductor package. The semiconductor package includes a first chip and a second chip attached to a substrate. A thermal conductivity layer is attached to the first chip. A molding compound laterally surrounds the first chip, the second chip, and the thermal conductivity layer. The second chip extends from the substrate to an imaginary horizontally extending line that extends along a horizontally extending surface of the thermal conductivity layer facing away from the substrate. The imaginary horizontally extending line is parallel to the horizontally extending surface.

Abstract: A corrosion-resistant dry film lubricant composition includes a lubricating pigment, a binder, and a solvent. The lubricating pigment comprises graphene platelets and is dispersed in the binder, and the solvent solubilizes the lubricant pigment and the binder. The graphene platelets are oxidized and functionalized with a silane. A method of producing a corrosion-resistant lubricant includes oxidizing exfoliated graphene to produce oxidized graphene platelets, functionalizing the oxidized graphene platelets with a silane to produce functionalized graphene platelets, and dispersing the functionalized graphene platelets in a lubricant composition, wherein the lubricant composition comprises a binder and a solvent.

Abstract: A semiconductor package includes a connection layer, a semiconductor chip disposed at a center portion of the connection layer, an adhesive layer disposed on the semiconductor chip, a heat spreader layer disposed on the adhesive layer, and a lower redistribution layer disposed on the connection layer and a bottom surface of the semiconductor chip. A width of the adhesive layer is the same as a width of the semiconductor chip, and a width of the heat spreader layer is less than the width of the adhesive layer.

Abstract: A semiconductor package includes a semiconductor die, a first thermal conductive pattern and a second thermal conductive pattern. The semiconductor die is encapsulated by an encapsulant. The first thermal conductive pattern is disposed aside the semiconductor die in the encapsulant. The second thermal conductive pattern is disposed over the semiconductor die, wherein the first thermal conductive pattern is thermally coupled to the semiconductor die through the second thermal conductive pattern and electrically insulated from the semiconductor die.

Abstract: A memory device including a base chip and a memory cube mounted on and connected with the base chip is described. The memory cube includes multiple stacked tiers, and each tier of the multiple stacked tiers includes semiconductor chips laterally wrapped by an encapsulant and a redistribution structure. The semiconductor chips of the multiple stacked tiers are electrically connected with the base chip through the redistribution structures in the multiple stacked tiers. The memory cube includes a thermal path structure extending through the multiple stacked tiers and connected to the base chip. The thermal path structure has a thermal conductivity larger than that of the encapsulant. The thermal path structure is electrically isolated from the semiconductor chips in the multiple stacked tiers and the base chip.

Abstract: A substrate that includes a core layer, at least one first dielectric layer located over a first surface of the core layer, at least one second dielectric layer located over a second surface of the core layer, a plurality of first interconnects located over a surface of the at least one first dielectric layer, a plurality of second interconnects located over the surface of the at least one first dielectric layer, a plurality of third interconnects located over the surface of the at least one first dielectric layer, and a solder resist layer located over the surface of the at least one second dielectric layer. The plurality of third interconnects and the plurality of second interconnects are co-planar to the plurality of first interconnects. The solder resist layer includes a first portion, a second portion, and a third portion.

Abstract: A display device is disclosed. The display device includes a display panel, a vapor chamber positioned behind the display panel, a board, which is positioned behind the vapor chamber and is coupled to the vapor chamber, and an adhesive member disposed between the display panel and the vapor chamber so as to be coupled thereto, wherein the vapor chamber includes a first plate, which defines a front surface thereof and faces the display panel, a second plate, which defines a rear surface thereof and is coupled to the first plate, and fluid flowing in a space defined between the first plate and the second plate, and wherein the first plate includes a coupler, which is depressed rearwards from the first plate and to which the adhesive member is coupled.

Abstract: Embodiments herein relate to integrating FIVR switching circuitry into a substrate that has a first side and a second side opposite the first side, where the first side of the substrate to electrically couple with a die and to provide voltage to the die and the second side of the substrate is to couple with an input voltage source. In embodiments, the FIVR switching circuitry may be printed onto the substrate using OFET, CNT, or other transistor technology, or may be included in a separate die that is incorporated within the substrate.

Abstract: The present disclosure relates to a heat sink pedestal including a composite material. The composite material may include at least one layer of a thermally conductive primary material and at least one layer of a thermally conductive secondary material. The composite material may include a conductivity ratio of lateral thermal conductivity (Kz) to planar thermal conductivity (Kx, Ky) of the composite material of at least 0. The heat sink pedestal may be conformable to a shape of a semiconductor chip.

Abstract: A method for manufacturing a semiconductor package, for example a package-on-package type semiconductor device package. As non-limiting examples, various aspects of this disclosure provide high-yield methods for manufacturing a package-on-package type semiconductor package, or a portion thereof.

Abstract: The disclosure relates to an optical transceiver and a manufacturing method thereof. The optical transceiver includes a substrate, a thermal-conductive substrate, a first metal wiring structure, a light-transceiving element and an optical fiber array. The substrate has an opening, and the thermal-conductive substrate is embedded within the opening. The first metal wiring structure is integrally formed on the substrate and the thermal-conductive substrate through an electroplating or a wire-printing process. The light-transceiving element is disposed on the thermal-conductive substrate and is electrically connected to the first metal wiring structure. The optical fiber array is arranged on the thermal-conductive substrate for communication with the light-transceiving element.

Abstract: A 3D device comprising: a first level comprising first transistors, said first level comprising a first interconnect; a second level comprising second transistors, said second level overlaying said first level; a third level comprising third transistors, said third level overlaying said second level; a plurality of electronic circuit units (ECUs), wherein each of said plurality of ECUs comprises a first circuit, said first circuit comprising a portion of said first transistors, wherein each of said plurality of ECUs comprises a second circuit, said second circuit comprising a portion of said second transistors, wherein each of said plurality of ECUs comprises a third circuit, said third circuit comprising a portion of said third transistors, wherein each of said ECUs comprises a vertical bus, wherein said vertical bus comprises greater than eight pillars and less than three hundred pillars and provides electrical connections between said first circuit and said second circuit.

Abstract: A semiconductor device of an aspect of the disclosure includes a switching element, a substrate, a front electroconductive layer, first through third terminals and a sealing resin. The first through third terminals project toward the same side from the sealing resin along a first direction crossing the substrate thickness direction. The first through third terminals are spaced apart in a second direction crossing the thickness and first directions. The first terminal is at an outermost side in the second direction among the first through third terminals. The sealing resin has root-side and tip-side parts. The root-side part is between the first and third terminals in the second direction and offset in the first direction toward the switching element side of the first and third terminals. The tip-side part is offset in the first direction toward the tip side of the first and third terminals exposed from the sealing resin.

Abstract: A packaging substrate includes a core layer including a glass substrate with a first surface and a second surface facing each other, and a plurality of core vias. The plurality of core vias penetrating through the glass substrate in a thickness direction, each comprising a circular core via having a circular opening part and a non-circular core via having a 1.2 or more aspect ratio in the x-y direction of an opening part. One or more electric power transmitting elements are disposed on the non-circular core via.

Abstract: An integrated circuit package having an electronic interposer comprising an upper section, a lower section and a middle section, a die side integrated circuit device electrically attached to the upper section of the electronic interposer, a die side heat dissipation device thermally contacting the die side integrated circuit device, a land side integrated circuit device electrically attached to the lower section of the electronic interposer, and a land side heat dissipation device thermally contacting the at least one die side integrated circuit device. The upper section and the lower section may each have between two and four layers and the middle section may be formed between the upper section and the lower section, and comprises up to eight layers, wherein a thickness of each layer of the middle section is thinner than a thickness of any of the layers of the upper section and the lower section.

Abstract: A carbon nanotube composite material includes a fixture sheet having a front side and a back side, and a carbon nanotube array sheet embedded in or bonded to both front and back sides of the fixture sheet.

Abstract: A module board of an embodiment includes a printed board having a through-hole, a semiconductor device mounted on the printed board so as to cover the through-hole, and a heat conductive polygonal column included in the through-hole. The semiconductor device includes a ground terminal or a power supply terminal, the polygonal column is supported by the through-hole at the corners of the polygonal column, and the polygonal column is connected to the ground terminal or the power supply terminal.

Abstract: A substrate connecting structure includes a substrate that includes a flat base material having a first surface and a second surface at a side opposite to the first surface, a first wiring layer arranged on the first surface, and a second wiring layer arranged on the second surface, a through hole extending through the base material, a connection metal body that includes a connecting portion connected to the second wiring layer and a projection inserted into the through hole, and a mounted component mounted on the substrate. The connection metal body is connected to the mounted component only at a distal end surface of the projection.

Abstract: A method for manufacturing a circuit board with a small size a communication unit comprising a radio frequency (RF) component, an antenna, and an encapsulation layer. The RF component is embedded in the encapsulation layer, the antenna is positioned on the encapsulation layer and electrically connected to the RF component. A rigid substrate is formed on a flexible substrate, and a receiving groove is defined in the rigid substrate to expose the flexible substrate. The communication unit is in the receiving groove, thus causing connection between the RF component and the flexible substrate, thereby the circuit board is formed.

Abstract: Microelectronic systems and components having integrated heat dissipation posts are disclosed, as are methods for fabricating such microelectronic systems and components. In various embodiments, the microelectronic system includes a substrate having a frontside, a socket cavity, and inner cavity sidewalls defining the socket cavity. A microelectronic component is seated on the frontside of the substrate such that a heat dissipation post, which projects from the microelectronic component, is received in the socket cavity and separated from the inner cavity sidewalls by a peripheral clearance. The microelectronic system further includes a bond layer contacting the inner cavity sidewalls, contacting an outer peripheral portion of the heat dissipation post, and at least partially filling the peripheral clearance.

Abstract: A semiconductor package device includes: (1) a substrate having a top surface; (2) a passive component disposed on the substrate and having a top surface; (3) an active component disposed on the substrate and having a top surface; and (4) a package body disposed on the substrate, the package body including a first portion covering the active component and the passive component, and a second portion covering the passive component, wherein a top surface of the second portion of the package body is higher than a top surface of the first portion of the package body, and the first portion and the second portion of the package body include different materials.

Abstract: According to some aspects of the present disclosure, heat sink assemblies are disclosed. Example heat sink assemblies include a printed circuit board having a first side and a second side. The printed circuit board defines an opening extending from the first side to the second side. The heat sink assembly also includes a heat sink coupled to the first side of the printed circuit board. The heat sink includes a protrusion extending through the through opening of the printed circuit board. The heat sink assembly further includes a surface mounted device coupled to the second side of the printed circuit board. The surface mounted device is in thermal contact with the protrusion of the heat sink to transfer heat from the surface mounted device to the heat sink. Example methods of manufacturing heat sink assemblies are also disclosed.

Abstract: In an example embodiment, a circuit interconnect includes a first printed circuit board (PCB), a second PCB, a spacer, and an electrically conductive solder joint. The first PCB includes a first electrically conductive pad. The second PCB includes a second electrically conductive pad. The spacer is configured to position the first PCB relative to the second PCB such that a space remains between the first PCB and the second PCB after the first electrically conductive pad and the second electrically conductive pad are conductively connected in a soldering process. The electrically conductive solder joint conductively connects the first electrically conductive pad and the second electrically conductive pad.

Abstract: Apparatus, systems, and processes for substrate breakage detection in a thermal processing system are provided. In one example implementation, a process can include: accessing data indicative of a plurality of temperature measurements for a substrate, the plurality of measurements obtained during a cool down period of a thermal process; estimating one or more metrics associated with a cooling model based at least in part on the data indicative of the plurality of temperature measurements; and determining a breakage detection signal based at least in part on the one or more metrics associated with the cooling model. The breakage detection signal is indicative of whether the substrate has broken during thermal processing.

Abstract: A mechanism is provided for cooling electronic components of a printed circuit board module and for supplying power to the electronic components of the printed circuit board module. The computer module comprises a printed circuit board module, wherein the electronic components are attached to a first side of the printed circuit board module, and a cooling module being attached to a second side of the printed circuit board, being arranged in parallel to the printed circuit board and having a first layer being thermally and electrically conductive. The first layer is arranged such that heat is dissipated from the printed circuit board module and that power from a power source is supplied to the electronic components of the printed circuit board module.

Abstract: A method is provided that includes forming a three-dimensional NAND stacked non-volatile memory array on a substrate, and forming a DRAM memory array on the substrate. The three-dimensional NAND stacked non-volatile memory array and the DRAM memory array are formed using a single integrated circuit fabrication process.

Abstract: Embodiments of mechanisms for forming dislocations in source and drain regions of finFET devices are provided. The mechanisms involve recessing fins and removing the dielectric material in the isolation structures neighboring fins to increase epitaxial regions for dislocation formation. The mechanisms also involve performing a pre-amorphous implantation (PAI) process either before or after the epitaxial growth in the recessed source and drain regions. An anneal process after the PAI process enables consistent growth of the dislocations in the source and drain regions. The dislocations in the source and drain regions (or stressor regions) can form consistently to produce targeted strain in the source and drain regions to improve carrier mobility and device performance for NMOS devices.

Abstract: Techniques for achieving extremely thin package structures are disclosed. In some embodiments, a device comprises an integrated circuit connected to a leadframe or substrate via connections and EMC (Epoxy Molding Compound) surrounding the integrated circuit except at a backside of the integrated circuit and connecting areas via which the integrated circuit is connected to the leadframe or substrate.

Abstract: Flip-chip on leadframe (FCOL) semiconductor packaging structure and fabrication method thereof are provided. A semiconductor chip with copper pillars formed there-over is provided. A barrier layer is formed on the copper pillars. A solder material is coated on the barrier layer. A layer of soldering flux is coated on the solder material. A leadframe with electric leads formed thereon is provided. An insulating layer is formed an the leadframe and having a plurality of openings to expose portion of the electric leads. The semiconductor chip is placed upside down onto the leadframe to have the soldering flux in contact with the portion of the electric leads exposed in the openings. The solder material flows back to form conductive interconnections between the copper pillars and the portion of the electric leads exposed in the openings. The semiconductor chip is packaged with the leadframe using a mold compound.

Abstract: A heat-dissipating base is provided. The heat-dissipating base includes a main body and at least one first protrusion. The first protrusion is disposed on the main body. The first protrusion has at least one first protrusion top surface for thermally contacting at least one first component above the main body.

Abstract: According to one embodiment, a reconfigurable circuit includes first, second, third and fourth circuit blocks arranged with a matrix, a first conductive line shared by the first and second circuit blocks, a second conductive line shared by the third and fourth circuit blocks, a third conductive line shared by the first and third circuit blocks, the third conductive line crossing the first and second conductive lines, a fourth conductive line shared by the second and fourth circuit blocks, the fourth conductive line crossing the first and second conductive lines, a first controller controlling voltages to be applied to the first and second conductive lines, and a second controller controlling voltages to be applied to the third and fourth conductive lines.

Abstract: A method includes attaching a wafer on a carrier through an adhesive, and forming trenches in the carrier to convert the carrier into a heat sink. The heat sink, the carrier, and the adhesive are sawed into a plurality of packages.

Abstract: A power semiconductor module includes a first printed circuit board having a first insulation carrier, and a first upper metallization and a first lower metallization applied to the first insulation carrier on mutually opposite sides, and a second printed circuit board having a second insulation carrier and a second upper metallization applied to the second insulation carrier. The second printed circuit board is spaced apart from the first printed circuit board in a vertical direction oriented perpendicular to the opposite sides of the first insulation carrier. A semiconductor chip is disposed between the printed circuit boards and electrically conductively connected at least to the second upper metallization. The first lower metallization and the second upper metallization face one another. The first printed circuit board has a first thick conductor layer at least partly embedded in the first insulation carrier and which has a thickness of at least 100 ?m.

Abstract: A lower package includes a semiconductor chip. A first upper package and a second upper package are disposed on the lower package. A heat spreader is disposed on the lower package. The heat spreader includes an upper plate and an extension part connected to the upper plate. At least a part of each of the first and second upper packages vertically overlaps the semiconductor chip. The upper plate may be arranged on the first upper package and the second upper package. The extension part may be arranged between the first upper package and the second upper package. The extension part has a vertical height that is greater than its horizontal width.

Abstract: A semiconductor device, including: a semiconductor substrate with a first layer including first transistors; a shield layer overlaying the first layer; a second layer overlaying the shield layer, the second layer including second transistors; wherein the shield layer is a mostly continuous layer with a plurality of regions for connections between the first transistors and the second transistors, and where the second transistors include monocrystalline regions.

Abstract: The invention relates to an electronic module and to a method for producing same, comprising a mold body (2), a first circuit carrier (3; 13) having a first inner face (3a; 13a), on which electronic components (5) are arranged, and a first outer face (3b; 13b), a second circuit carrier (4; 14) having a second inner face (4a; 14a), on which electronic components (5) are arranged, and a second outer face (4b; 14b), and at least one spring device (6, 7; 16) which connects the inner faces (3a, 14a; 13a, 14a), or surfaces of electronic components (5) arranged thereon, of the first and second circuit carriers (3, 4; 13, 14), wherein the first and second outer faces (3a, 4a; 13a, 14a) are exposed towards the outside of the electronic module in order to emit heat directly to the outside, and wherein the first and second outer faces (3a, 4a; 13a, 14a) are parallel to each other.