Abstract: The power module semiconductor device (2) includes: an insulating substrate (10); a first pattern (10a) (D) disposed on the insulating substrate (10); a semiconductor chip (Q) disposed on the first pattern; a power terminal (ST, DT) and a signal terminal (CS, G, SS) electrically connected to the semiconductor chip; and a resin layer (12) configured to cover the semiconductor chip and the insulating substrate. The signal terminal is disposed so as to be extended in a vertical direction with respect to a main surface of the insulating substrate.

Abstract: A semiconductor apparatus includes: a system substrate; a semiconductor package mounted on the system substrate and having a first length in a first horizontal direction; a conductive label flexible and arranged on the semiconductor package, the conductive label including: a first adhesive layer contacting the semiconductor package; a thermally-conductive layer attached to the semiconductor package by the first adhesive layer and having a second length in the first horizontal direction greater than the first length; and a second adhesive layer contacting a portion of a surface of the conductive layer, the portion not vertically overlapping the semiconductor package; a thermal interface material (TIM) arranged on the conductive layer to vertically overlap the semiconductor package; and a cover including: a first cover portion vertically overlapping the semiconductor package and contacting the TIM; and a second cover portion to which the thermally-conductive layer is attached by the second adhesive layer.

Abstract: A side wettable package includes a molding compound, a chip and multiple conductive pads exposed from a bottom surface of the molding compound. The conductive pads include peripheral conductive pads arranged near a side wall of the molding compound. Each of the peripheral conductive pads is over etched to form an undercut. When the side wettable package is connected to a circuit board via solder, the solder ascends to the undercut of the peripheral conductive pads for improving connection yield and facilitating inspection of soldering quality.

Abstract: Methods and systems for a semiconductor package with high routing density routing patch are disclosed and may include a semiconductor die bonded to a substrate and a high routing density patch bonded to the substrate and to the semiconductor die, wherein the high routing density patch comprises a denser trace line density than the substrate. The high routing density patch can be a silicon-less-integrated module (SLIM) patch, comprising a BEOL portion, and can be TSV-less. Metal contacts may be formed on a second surface of the substrate. A second semiconductor die may be bonded to the substrate and to the high routing density patch. The high routing density patch may provide electrical interconnection between the semiconductor die. The substrate may be bonded to a silicon interposer. The high routing density patch may have a thickness of 10 microns or less. The substrate may have a thickness of 10 microns or less.

Abstract: A semiconductor package includes a semiconductor chip structure that includes an image sensor chip and a logic chip that contact each other, a transparent substrate disposed on the semiconductor chip structure, and an adhesive structure disposed on an edge of the semiconductor chip structure and between the semiconductor chip structure and the transparent substrate. The adhesive structure includes a first adhesive segment disposed on a top surface of the semiconductor chip structure and a second adhesive segment disposed on a bottom surface of the transparent substrate. The second adhesive segment covers top and lateral surfaces of the first adhesive segment. The image sensor chip is closer to the transparent substrate than the logic chip.

Abstract: A thermoelectric semiconductor device includes a heat dissipating semiconductor module and a stack of flash memory dies mounted on a substrate. The heat dissipating module comprises a first semiconductor die such as a controller, and a second semiconductor die such as a thermoelectric semiconductor die to cool the first semiconductor die during operation. The thermoelectric semiconductor die may be mounted to the controller die at the wafer level.

Abstract: An external terminal electrode is attached to a frame, and the frame contains a first resin, and has a first adhered surface. A heat sink plate supports the frame, has an unmounted region where a power semiconductor element is to be mounted within the frame in plan view, is made of metal, and has a second adhered surface. An adhesive layer contains a second resin different from the first resin, and adheres the first adhered surface of the frame and the second adhered surface of the heat sink plate to each other. One of the first and second adhered surfaces includes a flat portion and a protruding portion. The protruding portion protrudes from the flat portion and opposes the other one of the first adhered surface and the second adhered surface with the adhesive layer therebetween.

Abstract: Systems and methods are disclosed for systems-in-packages that have multiple shielding components. In one embodiment, a system-in-package may include a substrate, an integrated circuit package disposed on the substrate, a system-on-a-chip disposed on the substrate, and a molding compound disposed over the integrated circuit package and the system-on-a-chip. The system-in-package may include a first electromagnetic interference shielding component disposed about the molding compound, and a second electromagnetic interference shielding component that at least partially forms an outer surface of the system-in-package. The second electromagnetic interference shielding component may have a patterned structure formed thereon.

Abstract: Disclosed herein are integrated circuit (IC) structures with a conductive element coupled to a first surface of a package substrate, where the conductive element has cavities for embedding components and the embedded components are electrically connected to the conductive element, as well as related apparatuses and methods. In some embodiments, embedded components have one terminal end, which may be positioned vertically, with the terminal end facing into the cavity, and coupled to the conductive element. In some embodiments, embedded components have two terminal ends, which may be positioned vertically with one terminal end coupled to the conductive element and the other terminal end coupled to the package substrate. In some embodiments, embedded components include passive devices, such as capacitors, resistors, and inductors. In some embodiments, a conductive element is a stiffener.

Abstract: The present disclosure relates to semiconductor core assemblies and methods of forming the same. The semiconductor core assemblies described herein may be utilized to form semiconductor package assemblies, PCB assemblies, PCB spacer assemblies, chip carrier assemblies, intermediate carrier assemblies (e.g., for graphics cards), and the like. In one embodiment, a silicon substrate core is structured by direct laser patterning. One or more conductive interconnections are formed in the substrate core and one or more redistribution layers are formed on surfaces thereof. The silicon substrate core may thereafter be utilized as a core structure for a semiconductor package, PCB, PCB spacer, chip carrier, intermediate carrier, or the like.

Abstract: A printed wiring-board island relieves added complexity to a printed circuit board. The printed wiring-board island creates an island form factor in the printed circuit board. Coupling of a semiconductive device package to the printed wiring-board island includes a ball-grid array. The ball-grid array can at least partially penetrate the printed wiring-board island.

Abstract: The device has a first support element forming a first thermal dissipation surface and carrying a first power component; a second support element forming a second thermal dissipation surface and carrying a second power component, a first contacting element superimposed to the first power component; a second contacting element superimposed to the second power component; a plurality of leads electrically coupled with the power components through the first and/or the second support elements; and a thermally conductive body arranged between the first and the second contacting elements. The first and the second support elements and the first and the second contacting elements are formed by electrically insulating and thermally conductive multilayers.

Abstract: Integrated power modules according to the present technology may include a printed circuit board characterized by a first surface and a second surface. The integrated power modules may include one or more surface-mounted components coupled with the first surface of the printed circuit board. The integrated power modules may include a heat-transfer substrate. The integrated power modules may include one or more gallium nitride transistors coupled between and soldered to each of the second surface of the printed circuit board and the heat-transfer substrate. The integrated power modules may include one or more spacers coupled between and soldered to each of the printed circuit board and the heat-transfer substrate.

Abstract: A fan-out semiconductor package includes a core member having a through hole, at least one dummy structure disposed in the core member, a semiconductor chip disposed in the through hole and including an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, an encapsulant sealing at least a portion of each of the core member and the semiconductor chip, and filing at least a portion of the through hole, and a connection member disposed on the core member and the active surface of the semiconductor chip, and including a redistribution layer electrically connected to the connection pad.

Abstract: The present description concerns a package for an electronic device. The package including a plate and a lateral wall, separated by a layer made of a bonding material and at least one region made of a material configured to form in the region an opening between the inside and the outside of the package when the package is heated.

Abstract: Structures and methods of forming fan-out packages are provided. The packages described herein may include a cavity substrate, one or more semiconductor devices located in a cavity of the cavity substrate, and one or more redistribution structures. Embodiments include a cavity preformed in a cavity substrate. Various devices, such as integrated circuit dies, packages, or the like, may be placed in the cavity. Redistribution structures may also be formed.

Abstract: A three-dimensional integrated circuit includes a first die structure having a first geometry. The first die structure includes a first region that operates with a first power density and a second region that operates with a second power density. The first power density is less than the second power density. The three-dimensional integrated circuit includes a second die structure having a second geometry. A stacked portion of the second die structure is aligned with the first region. The three-dimensional integrated circuit includes an additional die structure stacked with the first die structure and the second die structure. The additional die structure has the first geometry or the second geometry.

Abstract: A power semiconductor device includes a substrate and a semiconductor element bonded onto a first surface of the substrate through use of a sintered metal bonding material. The substrate has a plurality of dimples formed in the first surface and located outside a location immediately below a heat generation unit of the semiconductor element. The sintered metal bonding material is supplied onto the substrate after the formation of the dimples, and the semiconductor element is bonded to the substrate through application of heat and a pressure thereto.

Abstract: A semiconductor package of an embodiment includes a wiring substrate, a semiconductor chip provided on an upper surface of the wiring substrate, a sealing resin covering surfaces of the wiring substrate and the semiconductor chip, an infrared reflection layer containing any of aluminum, aluminum oxide, and titanium oxide, and an external terminal provided on a lower surface of the wiring substrate. The wiring substrate is electrically connectable with a printed wiring board through the external terminal. The infrared reflection layer is provided to the sealing resin on an upper side of a surface of the semiconductor chip on a side opposite to an upper surface of the wiring substrate.

Abstract: A semiconductor device module may include a leadframe spacer that provides the functions of both a leadframe and a spacer, while enabling a double-sided cooling configuration. Such a leadframe spacer may include a leadframe surface that provides a die attach pad (DAP) that is shared by at least two semiconductor devices. The leadframe spacer may include at least one downset, where the semiconductor devices may be attached within a recess defined by the at least one downset. A first substrate may be connected to a first side of the leadframe. A second substrate may be connected to downset surfaces of the at least one downset, and positioned for further connection to the semiconductor devices in a double-sided assembly.

Abstract: A backlight source and a manufacturing method thereof are provided. The backlight source includes a first substrate, a plurality of light sources, a driving circuit layer, and a conductive line. The light sources are distributed on an upper surface of the first substrate. The second substrate is disposed opposite to the first substrate. The driving circuit layer is disposed on a surface of a side of the second substrate away from the first substrate. An end of the conductive line is connected to one of the light sources, and another end of the conductive line is bonded to the driving circuit layer.

Abstract: A method of manufacturing a semiconductor package includes mounting a first semiconductor chip and a second semiconductor chip on a substrate, forming a first film on a top surface of the first semiconductor chip, and loading the first semiconductor chip and the second semiconductor chip mounted on the substrate between a lower mold frame and an upper mold frame. The method further includes providing a molding material between the lower mold frame and the upper mold frame, removing the lower mold frame and the upper mold frame, and removing the first film on the top surface of the first semiconductor chip to expose the top surface of the first semiconductor chip.

Abstract: A semiconductor package including a core substrate, a semiconductor chip in the core substrate and having chip pads, a redistribution wiring layer covering a lower surface of the core substrate and including redistribution wirings electrically connected to the chip pads and a pair of capacitor pads exposed from an outer surface of the redistribution wiring layer, conductive pastes on the capacitor pads, respectively, and a capacitor via the conductive pastes and having first and second outer electrodes on the capacitor pads, respectively, may be provided. Each of the capacitor pads includes a pad pattern exposed from the outer surface of the redistribution wiring layer, and at least one via pattern at a lower portion of the pad pattern and electrically connected to at least one of the redistribution wirings. The via pattern is eccentric by a distance from a center line of the pad pattern.

Abstract: In an embodiment, a method for manufacturing a semiconductor device includes forming a redistribution structure on a carrier substrate, connecting a plurality of core substrates physically and electrically to the redistribution structure with a first anisotropic conductive film, the first anisotropic conductive film including a dielectric material and conductive particles, and pressing the plurality of core substrates and the redistribution structure together to form conductive paths between the plurality of core substrates and the redistribution structure with the conductive particles in the first anisotropic conductive film. The method also includes encapsulating the plurality of core substrates with an encapsulant.

Abstract: A method of bonding semiconductor components is described. In one aspect a first component, for example a semiconductor die, is bonded to a second component, for example a semiconductor wafer or another die, by direct metal-metal bonds between metal bumps on one component and corresponding bumps or contact pads on the other component. In addition, a number of solder bumps are provided on one of the components, and corresponding contact areas on the other component, and fast solidified solder connections are established between the solder bumps and the corresponding contact areas, without realizing the metal-metal bonds. The latter metal-metal bonds are established in a heating step performed after the soldering step. This enables a fast bonding process applied to multiple dies bonded on different areas of the wafer and/or stacked one on top of the other, followed by a single heating step for realizing metal-metal bonds between the respective dies and the wafer or between multiple stacked dies.

Abstract: A package structure includes a redistribution structure and a core substrate. The redistribution structure includes a plurality of connection pads. The core substrate is disposed on the redistribution structure and electrically connected to the plurality of connection pads. The core substrate includes a first interconnection layer and a plurality of conductive terminals. The first interconnection layer has a first region, a second region surrounding the first region, and a third region surrounding the second region, and includes a plurality of bonding pads located in the first region, the second region and the third region. The conductive terminals are electrically connecting the plurality of bonding pads to the plurality of connection pads of the redistribution structure, wherein the plurality of conductive terminals located over the first region, the second region and the third region of the first interconnection layer have different heights.

Abstract: A first package is bonded to a first substrate with first external connections and second external connections. The second external connections are formed using materials that are different than the first external connections in order to provide a thermal pathway from the first package. In a particular embodiment the first external connections are solder balls and the second external connections are copper blocks.

Abstract: A composition for a sacrificial film includes a polymer, a solvent, and a plasticize compound having an aromatic ring structure. A package includes a die, through insulating vias (TIV), an encapsulant, and a redistribution structure. The die includes a sensing component. The TIVs surround the die. The encapsulant laterally encapsulates the die and the TIVs. The redistribution structure is over the die, the TIVs, and the encapsulant. The redistribution structure has an opening exposing the sensing component of the die. A top surface of the redistribution structure is slanted.

Abstract: A manufacturing method of a mounting structure, the method including: a step of preparing a mounting member including a first circuit member and a plurality of second circuit members placed on the first circuit member, the mounting member having a space between the first circuit member and the second circuit member; a step of preparing a laminate sheet including a first thermal-conductive layer and a second thermal-conductive layer, the first thermal-conductive layer disposed at least on one outermost side; a disposing step of disposing the laminate sheet on the mounting member such that the first thermal-conductive layer faces the second circuit members; and a sealing step of pressing the laminate sheet against the first circuit member and heating the laminate sheet, to seal the second circuit members so as to maintain the space, and to cure the laminate sheet.

Abstract: A wiring board includes an insulating substrate including a first surface and a mounting portion for an electronic component on the first surface, the insulating substrate having a rectangular shape in a plan view of the first surface; a via conductor located inside the insulating substrate and at a corner portion of the insulating substrate in a plane perspective, and extending in a thickness direction of the insulating substrate; a wiring conductor located on the first surface and connecting the mounting portion and the via conductor to each other; and a heat dissipation portion located inside the insulating substrate at a position overlapping the mounting portion in a plane perspective view, wherein the first surface includes, between the heat dissipation portion and the via conductor in a plane perspective view, a first region surrounded by the wiring conductor in a plan view.

Abstract: The present invention provides a packaging method and a packaging device for selectively encapsulating a packaging structure. The method includes: providing a substrate; mounting components on the substrate, the components including a component that needs to be encapsulated and a component that does not need to be encapsulated; forming a protective structure in an area of the component that does not need to be encapsulated so as to form a protective area for isolating the component that does not need to be encapsulated and an encapsulating area located outside the protective area; filling the encapsulating area with an injection molding material; and removing the protective structure. According to the present invention, any part of the packaging structure may be selectively encapsulated by self-adjustment as required. The operation is simple, and the process flow is simplified.

Abstract: Systems, apparatuses, and methods are described for clamping a heat generating device such as a thyristor in place. The use of spring washers in various configurations is described. A spring washing washer may be used to apply force to a pad which in turn applies the force to a plate above a heat generating device. The plate above the heat generating device may apply downward pressure, which may force the heat generating device against a lower surface. Related systems, apparatuses, and methods are also described.

Abstract: A stand-alone active thermal interposer device for use in testing a system-in-package device under test (DUT), the active thermal interposer device includes a body layer having a first surface and a second surface, wherein the first surface is operable to be disposed adjacent to a cold plate, and a plurality of heating zones defined across a second surface of the body layer, the plurality of heating zones operable to be controlled by a thermal controller to selectively heat and maintain respective temperatures thereof, the plurality of heating zones operable to heat a plurality of areas of the DUT when the second surface of the body layer is disposed adjacent to an interface surface of the DUT during testing of the DUT.

Abstract: Presented herein is a cold plate assembly including a sub-plate and a vapor chamber for use as part of a remote fin cooling system for an electronic device. The sub-plate includes a first surface, a second surface, and a plurality of pipes. The vapor chamber includes a first wall and a second wall opposite the first wall. The first wall and the second wall define an interior cavity having a first depth for one or more first portions of the vapor chamber and a second depth for one or more second portions of the vapor chamber. The second surface of the sub-plate is attached to the first wall of the vapor chamber.

Abstract: A structure includes a circuit substrate, a device, a metal layer, a lid and a thermal interface material layer. The device is disposed on and electrically connected to the circuit substrate. The device includes at least one semiconductor die laterally encapsulated by an insulating encapsulation. The metal layer is covering a back surface of the at least one semiconductor die and the insulating encapsulation. The lid is disposed on the circuit substrate, and the lid is adhered to the metal layer through the thermal interface material layer.

Abstract: A semiconductor device assembly comprises a substrate including internal contacts on a first side and first external contacts on a second side. The assembly further comprises one or more first dies disposed over the first side and electrically coupled to the internal contacts, and a interposer having a length and a width less than a length and a width of the substrate, having inner contacts on a first side, and having second external contacts on a second side. The interposer is coupled to the second side of the substrate by one or more of the inner contacts. The assembly further comprises a second die disposed between the substrate and the interposer. The assembly further comprises first solder balls on the first external contacts, and second solder balls on the second external contacts. The first and second solder balls are configured to bond with co-planar package contacts.

Abstract: A semiconductor package includes a support member, a semiconductor chip arranged in the support member such that a front surface and a backside surface of the semiconductor chip are exposed from a second surface of the support member and a first surface opposite to the second surface respectively, a lower redistribution wiring layer covering the second surface of the support member and including first redistribution wirings electrically connected to chip pads provided at the front surface of the semiconductor chip and vertical connection structures of the support member respectively, and an upper redistribution wiring layer covering the first surface of the support substrate, and including second redistribution wirings electrically connected to the vertical connection structures and a thermal pattern provided on the exposed backside surface of the semiconductor chip.

Abstract: A semiconductor package includes a redistribution structure including an insulating layer having an upper surface and a lower surface, a redistribution pad and a redistribution pattern on the lower surface of the insulating layer and electrically connected to each other, and a passivation layer on the lower surface of the insulating layer and having an opening exposing at least a portion of the redistribution pad; a semiconductor chip on the redistribution structure and including a connection pad electrically connected to the redistribution pad; an encapsulant on the redistribution structure and encapsulating the semiconductor chip; and a connection bump and a dummy bump on the passivation layer, wherein the redistribution pattern has a width narrower than a width of the redistribution pad, the connection bump vertically overlaps the redistribution pad, and the dummy bump vertically overlaps the redistribution pattern.

Abstract: A power electronics converter includes a carrier substrate, and a converter commutation cell including a power circuit. The power circuit includes at least one power semiconductor switching element. Each power semiconductor switching element is comprised in a power semiconductor prepackage. One or more terminals of each power semiconductor switching element are connected to at least one conductive layer of the carrier substrate at an electrical connection side of the respective power semiconductor prepackage. The electrical connection side is spaced apart from the carrier substrate by a gap. At least a portion of the gap is filled with an electrically insulating material with voids. A peak rated power output of the power electronics converter is greater than 25 kW, and a converter parameter, which is defined as a product of a dielectric strength of the electrically insulating material and a maximum void size, is less than or equal to 10,000 V.

Abstract: A method of manufacturing a carrier for semiconductor device packaging is provided. The method includes forming a carrier having a plurality of plateau regions separated by a plurality of channels. The carrier is configured and arranged to support a plurality of semiconductor die during a packaging operation. The plurality of channels is filled with a material configured to control warpage of the carrier.

Abstract: A semiconductor package includes a chip package disposed on a substrate, a plurality of electronic components disposed aside the chip package on the substrate and a stiffener structure disposed on the substrate. The stiffener structure includes a stiffener ring surrounding the chip package and the plurality of electronic components, a stiffener rib between the chip package and the plurality of electronic components, wherein the stiffener rib includes a first portion and a second portion on the first portion, and a width of the second portion is greater than a width of the first portion. The semiconductor package further includes a lid attached to the stiffener structure, the chip package and the plurality of electronic components. A method of forming the semiconductor package is also provided.

Abstract: A semiconductor package and a method of forming the same are provided. The semiconductor package includes a package substrate and a semiconductor device mounted on the surface of the package substrate. A first ring is disposed over the surface of the package substrate and surrounds the semiconductor device. A second ring is disposed over the top surface of the first ring. Also, a protruding part and a matching recessed part are formed on the top surface of the first ring and the bottom surface of the second ring, respectively. The protruding part extends into and engages with the recessed part to connect the first ring and the second ring. An adhesive layer is disposed between the surface of the package substrate and the bottom surface of the first ring for attaching the first ring and the overlying second ring to the package substrate.

Abstract: A method for packaging an integrated circuit chip includes the steps of: a) providing a plurality of dies and a lead frame which includes a plurality of bonding parts each having a die pad, a plurality of leads each having an end region disposed on and connected to the die pad, and a plurality of bumps each disposed on the end region of a respective one of the leads; b) transferring each of the dies to the die pad of a respective one of the bonding parts to permit each of the dies to be flipped on the respective bonding part; and c) hot pressing each of the dies and the die pad of a respective one of the bonding parts to permit each of the dies to be bonded to the bumps of the respective bonding part.

Abstract: Electronics assemblies and methods of manufacturing electronics assemblies having improved thermal performance. One example of these electronics assemblies includes a printed circuit board (PCB), an integrated circuit package mounted to the PCB, the integrated circuit packing having a heat generating component, and a heat spreader soldered to the PCB such that the heat spreader is thermally coupled to the heat generating component of the integrated circuit package to dissipate heat generated by the heat generating component.

Abstract: A thermal interface material (TIM) structure for directing heat in a three-dimensional space including a TIM sheet. The TIM sheet includes a lower portion along a lower plane; a first side portion along a first side plane; a first upper portion along an upper plane; a first fold between the lower portion and the first side portion positioning the first side portion substantially perpendicular to the lower portion; and a second fold between the first side portion and the first upper portion positioning the first upper portion substantially perpendicular to the first side portion and substantially parallel to the lower portion.

Abstract: An apparatus is formed. The apparatus includes a stack of semiconductor chips. The stack of semiconductor chips includes a logic chip and a memory stack, wherein, the logic chip includes at least one of a GPU and CPU. The apparatus also includes a semiconductor chip substrate. The stack of semiconductor chips are mounted on the semiconductor chip substrate. At least one other logic chip is mounted on the semiconductor chip substrate. The semiconductor chip substrate includes wiring to interconnect the stack of semiconductor chips to the at least one other logic chip.

Abstract: To achieve reductions in size and weight and a higher functionality of an imaging device, the imaging device comprises a first circuit board mounting a first heat-generating component for processing a signal from the imaging sensor, a first heat dissipation plate for transferring heat from the first heat-generating component to the housing; and a fan disposed adjacent to the first heat dissipation plate, air-cooling the first heat dissipation plate, wherein the fan is configured to take in the air in a rotation axis direction and discharges the air in an outer circumferential direction, and the discharged air is blown to heat dissipation fins of the heat sink of the first heat dissipation plate and discharged from the discharge port.

Abstract: A semiconductor package structure including a package substrate, at least one semiconductor die, a lid structure, a first electronic component and a heat sink is provided. The package substrate has a first surface and a second surface opposite to the first surface. The semiconductor die is on the first surface of the package substrate and is surrounded by an encapsulating layer. The lid structure surrounds and is spaced apart from the encapsulating layer. The lid structure includes a first opening that is covered by the first surface of the package substrate. The first electronic component is over the first surface of the package substrate and arranged within the first opening of the lid structure. The heat sink covers the lid structure and the semiconductor die.

Abstract: Disclosed is a semiconductor package including a base film that has a first surface and a second surface opposite to the first surface, a plurality of input/output lines on the first surface of the base film, a semiconductor chip disposed on the first surface of the base film and connected to the input/output lines and including a central portion and end portions on opposite sides of the central portion, and a heat radiation pattern on the second surface of the base film. The heat radiation pattern corresponds to the semiconductor chip and has a plurality of openings that correspond to the end portions of the semiconductor chip and that vertically overlap the end portions of the semiconductor chip.

Abstract: A package structure and a formation method of a package structure are provided. The package structure includes a circuit substrate and a die package bonded to the circuit substrate through bonding structures. The package structure also includes a warpage-control element attached to the circuit substrate. The warpage-control element has a protruding portion extending into the circuit substrate. The warpage-control element has height larger than that of the die package.