Abstract: A back-side lamination (BSL) is applied after thinning a microelectronic die. The BSL is configured to be a thermal-expansion complementary structure to a metal wiring interconnect layout that is disposed on the active side of the microelectronic die.
Abstract: The invention comprises a 3D chip stack with an intervening thermoelectric coupling (TEC) plate. Through silicon vias in the 3D chip stack transfer electronic signals among the chips in the 3D stack, power the TEC plate, as well as distribute heat in the stack from hotter chips to cooler chips.
Type:
Grant
Filed:
January 12, 2009
Date of Patent:
February 22, 2011
Assignee:
International Business Machines Corporation
Inventors:
Louis Lu-Chen Hsu, Ping-Chuan Wang, Xiaojin Wei, Huilong Zhu
Abstract: A thermally conductive structure for a semiconductor integrated circuit and a method for making the structure. The structure comprises one or more vertical and/or horizontal thermally conductive elements disposed proximate a device for improving thermal conductivity from the device to a substrate of the integrated circuit. In one embodiment a heat sink is affixed to the integrated circuit for heat flow from the integrated circuit. The method comprises forming openings in material layers overlying the semiconductor substrate, wherein the openings are disposed proximate the device and extend to the substrate. A thermally conductive material is formed in the openings to provide a thermal path from the device to the substrate.
Type:
Grant
Filed:
September 30, 2004
Date of Patent:
March 18, 2008
Assignee:
Agere Systems Inc.
Inventors:
Daniel Charles Kerr, Alan Sangone Chen, Edward Paul Martin, Jr., Amal Ma Hamad, William A. Russell
Abstract: A method for programming a routing layout design through one via layer includes forming a plurality of metal traces on a first routing layer and a second routing layer, and positioning a plurality of vias within a via layer disposed between the first and second routing layers for connecting the metal traces on the first and second routing layers according to a first current route defined by a predetermined circuit layout design to connect a first node and a second node so as to establish a second current route equivalent to the first current route.
Type:
Grant
Filed:
March 25, 2004
Date of Patent:
October 30, 2007
Assignee:
Faraday Technology Corp.
Inventors:
Hsin-Shih Wang, Shang-Jyh Shieh, Ming-Hsin Ku
Abstract: Embodiments of the present invention are directed to the formation of microprobe tips elements having a variety of configurations. In some embodiments tips are formed from the same building material as the probes themselves, while in other embodiments the tips may be formed from a different material and/or may include a coating material. In some embodiments, the tips are formed before the main portions of the probes and the tips are formed in proximity to or in contact with a temporary substrate.
Type:
Grant
Filed:
July 7, 2005
Date of Patent:
September 25, 2007
Assignee:
Microfabrica Inc.
Inventors:
Kieun Kim, Adam L. Cohen, Willa M. Larsen, Richard T. Chen, Ananda H. Kumar, Ezekiel J. J. Kruglick, Vacit Arat, Gang Zhang, Michael S. Lockard, Christopher A. Bang