Abstract: An inverter and a heat radiation structure thereof are provided. The heat radiation structure of the inverter includes a heat radiator for radiating heat from a heating element of the inverter, and a heat radiation fan for air-cooling the heat radiator. The heat radiator includes multiple heat radiation fins able to be air-cooled. The number of the heat radiator is at least two, and two adjacent heat radiators are a first heat radiator and a second heat radiator respectively. The heat radiation fan is provided between the first heat radiator and the second heat radiator, and the heat radiation fan is located on the tops of the heat radiation fins. In the heat radiation structure of the inverter, the heat radiation fan is capable of cooling the first heat radiator and the second heat radiator at the same time.

Abstract: According to an exemplary embodiment, a substrate having a first area and a second area is provided. The substrate includes a plurality of pads. Each of the pads has a pad size. The pad size in the first area is larger than the pad size in the second area.

Abstract: Provided is a SiC semiconductor element equipped with a SiC integrated circuit having a stable characteristic, which operates normally even in a radiation environment. A radiation resistant circuit device includes: a SiC semiconductor element equipped with a SiC integrated circuit, a printed board on which the SiC semiconductor element is provided, a conductive wiring that is arranged inside the printed board and has a predetermined surface facing a bottom surface of a substrate electrode of the SiC integrated circuit, and an insulating material arranged between the bottom surface of the substrate electrode of the SiC integrated circuit and the predetermined surface of the conductive wiring.

Abstract: The present invention is a method of manufacturing a ceramic substrate, the method including forming a mask on one surface of a metal layer, forming an inclined protrusion by etching the metal layer exposed by the mask, and bonding the metal layer on which the inclined protrusion is formed to a ceramic base material, and according to the present invention, the inclined protrusion is formed on an outer perimeter of the metal layer bonded to the ceramic base material to increase a bonding strength between the ceramic base material and the metal layer and facilitate a metal layer etching process.

Abstract: When forming layer stacks in the presence of solder material, uncontrolled flow of the solder material at the interface of two different layers of the layer stack may significantly be mitigated by providing an area of increased pressure in the material of the overlaying foil layer. For example, the area of increased pressure may be generated during the lamination process by providing a pressure inducing structure, for instance on the underlying foil layer, which laterally surrounds the solder material and therefore, in combination with the material of the overlying foil layer, reliably confines the solder material.

Abstract: A composition for solar cell electrodes, a solar cell electrode, and a method of manufacturing a solar cell, the composition including a conductive powder; a glass frit; and an organic vehicle, wherein the conductive powder includes a first silver powder having a cross-sectional particle porosity of about 0.1% to about 6%.

Abstract: To improve a TCT characteristic of a circuit substrate. The circuit substrate comprises a ceramic substrate including a first and second surfaces, and first and second metal plates respectively bonded to the first and second surfaces via first and second bonding layers. A three-point bending strength of the ceramic substrate is 500 MPa or more. At least one of L1/H1 of a first protruding portion of the first bonding layer and L2/H2 of a second protruding portion of the second bonding layer is 0.5 or more and 3.0 or less. At least one of an average value of first Vickers hardnesses of 10 places of the first protruding portion and an average value of second Vickers hardnesses of 10 places of the second protruding portion is 250 or less.

Abstract: A metal circuit board and a metal base plate are bonded to a ceramic substrate to form a metal-ceramic bonded substrate, then the metal base plate is arranged on one surface of the radiator via a brazing material with the metal base plate overlapping with the one surface of the radiator, a jig having a concave R surface is arranged on another surface of the radiator with the jig butting against the another surface of the radiator, a jig having a convex R surface protruding toward the metal-ceramic bonded substrate is brought into contact with another surface of the metal circuit board, and the metal-ceramic bonded substrate and the radiator are heat-bonded while they are pressurized by the radiator side jig and the metal-ceramic bonded substrate side jig, wherein a curvature radius R (mm) of the convex R surface and the concave R surface is 6500?R?surface pressure (N/mm2)×2000+12000.

Abstract: A double sided cooled power module package having a single phase leg topology includes two IGBT and two diode semiconductor dies. Each IGBT die is spaced apart from a diode semiconductor die, forming a switch unit. Two switch units are placed in a planar face-up and face-down configuration. A pair of DBC or other insulated metallic substrates is affixed to each side of the planar phase leg semiconductor dies to form a sandwich structure. Attachment layers are disposed on outer surfaces of the substrates and two heat exchangers are affixed to the substrates by rigid bond layers. The heat exchangers, made of copper or aluminum, have passages for carrying coolant. The power package is manufactured in a two-step assembly and heating process where direct bonds are formed for all bond layers by soldering, sintering, solid diffusion bonding or transient liquid diffusion bonding, with a specially designed jig and fixture.

Abstract: A clad material 1A for insulating substrates is provided with a Ni layer 4 made of Ni or a Ni alloy, a Ti layer 6 made of Ti or a Ti alloy and arranged on one side of the Ni layer, and a first Al layer 7 made of Al or an Al alloy and arranged on one side of the Ti layer 6 that is opposite to a side of the Ti layer 6 on which the Ni layer 4 is arranged. The Ni layer 4 and the Ti layer 6 are joined by clad rolling. A Ni—Ti series superelastic alloy layer 5 formed by alloying at least Ni of constituent elements of the Ni layer 4 and at least Ti of constituent elements of the Ti layer 6 is interposed between the Ni layer 4 and the Ti layer 6. The Ti layer 6 and the first Al layer 7 are joined by clad rolling in an adjoining manner.

Abstract: An integrated circuit package apparatus includes a packaging substrate, an integrated circuit coupled to an upper side of the packaging substrate, an array of contacts coupled to an underside of the packaging substrate for electrically coupling the integrated circuit to a circuit board, and a lid coupled to the upper side of the packaging substrate. In one form, the lid includes a central portion lying on a first plane, corner areas lying on a second plane, and arcuate wall portions disposed between and interconnecting the corner areas and the central portion. Other forms of the lid are provided.

Abstract: Disclosed is a luminaire, comprising a front convective heat sink, a rear convective heat sink, and a removable thin printed circuit board. The front convective heat sink has at least one optical aperture. The removable thin printed circuit board has an electrically-insulated back surface and a selectively electrically-insulated front surface. The front surface has exposed electrical contacts in at least one area corresponding to the at least one optical aperture. The removable thin printed circuit board is sandwiched between the front and rear convective heat sinks with a compressive force.

Abstract: A micromachined microphone or speaker embedded within, or positioned on top of, a substrate suitable for carrying microelectronic chips and components. The acoustic element converts sound energy into electrical energy which is then amplified by electronic components positioned on the surface of the substrate. Alternatively, the acoustic element may be driven by electronics to produce sound. The substrate can be used in standard microelectronic packaging applications.

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, forming dielectric material surrounding the die, forming buildup layers in the dielectric material to form a coreless bumpless buildup package structure, and patterning the carrier material to form microchannel structures on the package structure.

Abstract: An electric device with an insulating substrate consisting of an insulating layer and at least one metallization on a surface side of the insulating layer, the metallization being structured and having an electric component on the metallization. The metallization has a layer thickness that is stepped and is greater in an area adjoining the component.

Abstract: Power module semiconductor packages that contain a flexible circuit board and methods for making such packages are described. The semiconductor package contain a flexible circuit board, a conductive film on a first portion of the upper surface of the flexible circuit board, a land pad on a second portion of the upper surface of the flexible circuit board, a heat sink on a portion of the bottom surface of the flexible circuit board, a passive component, a discrete device, or an IC device connected to a portion of the conductive film, and a lead of a lead frame connected to the land pad. These packages can have a high degree of design flexibility of the layout of the package and simpler routing designs, reducing the time to design the packages and reducing the costs of the packages. Other embodiments are also described.

Abstract: A structure and method of fabricating the structure includes a semiconductor substrate having a top surface defining a horizontal direction and a plurality of interconnect levels stacked from a lowermost level proximate the top surface of the semiconductor substrate to an uppermost level furthest from the top surface. Each of the interconnect levels include vertical metal conductors physically connected to one another in a vertical direction perpendicular to the horizontal direction. The vertical conductors in the lowermost level being physically connected to the top surface of the substrate, and the vertical conductors forming a heat sink connected to the semiconductor substrate. A resistor is included in a layer immediately above the uppermost level. The vertical conductors being aligned under a downward vertical resistor footprint of the resistor, and each interconnect level further include horizontal metal conductors positioned in the horizontal direction and being connected to the vertical conductors.

Abstract: A method for the connection of two wafers in which a contact area is formed between the two wafers by placing the two wafers one on top of the other. The contact area is heated locally and for a limited time. A wafer arrangement comprises two wafers which have been placed one on top of the other and between whose opposite surfaces a contact area is located. The wafers are connected to one another at selected areas of the contact area.

Abstract: A ceramic assembly includes one or more electrically and thermally conductive pads to be thermally coupled to a heat generating device, each conductive pad is electrically isolated from each other. The ceramic assembly includes a ceramic layer to provide this electrical isolation. The ceramic layer has high thermal conductivity and high electrical resistivity. A top surface and a bottom surface of the ceramic layer are each bonded to a conductive layer, such as copper, using an intermediate joining material. A brazing process is performed to bond the ceramic layer to the conductive layer via a joining layer. The joining layer is a composite of the joining material, the ceramic layer, and the conductive layer. The top conductive layer and the joining layer are etched to form the electrically isolated conductive pads. The conductive layers are bonded to the ceramic layer using a bare ceramic approach or a metallized ceramic approach.

Abstract: A semiconductor package, containing two or more stacked IC devices attached to a substrate. Each of the IC devices has a plurality of electrical contact regions which are connected to the substrate by means of electrical connections.

Abstract: A semiconductor device includes an insulating substrate having a ceramic substrate and metal coating layers on opposite surfaces of the ceramic substrate, a semiconductor chip mounted on one surface of the insulating substrate, a heat sink directly or indirectly fixed to the other surface of the insulating substrate and thermally connected to the semiconductor chip through the insulating substrate and at least one anti-warping sheet disposed on at least one surface of the heat sink. The anti-warping sheet is made of a metal sheet having a coating layer and has coefficient of thermal expansion between those of the insulating substrate and the heat sink.

Abstract: A method of manufacturing a semiconductor device, the method including, providing a first monocrystalline layer including semiconductor regions, overlaying the first monocrystalline layer with an isolation layer, transferring a second monocrystalline layer comprising semiconductor regions to overlay the isolation layer, wherein the first monocrystalline layer and the second monocrystalline layer are formed from substantially different crystal materials; and subsequently etching the second monocrystalline layer as part of forming at least one transistor in the second monocrystalline layer.

Abstract: A micro electromechanical system (MEMS) spring element is disposed on a substrate, and includes a fixing portion and a moveable portion. The fixing portion is fixed on the substrate, and includes an insulating layer, a plurality of metal-fixing layers and a plurality of supporting-fixing layers. The insulating layer is disposed on the substrate. The metal-fixing layers are disposed above the insulating layer. The supporting-fixing layers are connected between the metal-fixing layers. The moveable portion has a first end and a second end. The first end is connected with the fixing portion, and the second end is suspended above the substrate. The moveable portion includes a plurality of metal layers and at least a supporting layer. The supporting layer is connected between the adjacent metal layers, and a hollow region is formed between the supporting layer and the adjacent metal layers.

Abstract: An electronic component module comprising at least one ceramic circuit carrier (2, 3) and a cooling device with at least one heat sink (4), a bonding region arranged between the ceramic circuit carrier (2, 3) and the cooling device adapted for bonding the circuit carrier (2, 3) to the cooling device (4). The bonding region (5, 7; 6, 8) comprises a bonding layer comprised of metal and a eutectic region (7, 8).

Abstract: A power semiconductor module is disclosed. One embodiment includes a multilayer substrate having a plurality of metal layers and a plurality of ceramic layers, where the ceramic layers are located between the metal layers.

Abstract: A method of making a semiconductor chip assembly includes providing a post and a base, mounting an adhesive on the base including inserting the post into an opening in the adhesive, mounting a conductive layer on the adhesive including aligning the post with an aperture in the conductive layer, then flowing the adhesive into and upward in a gap located in the aperture between the post and the conductive layer, solidifying the adhesive, then providing a conductive trace that includes a pad, a terminal and a selected portion of the conductive layer, providing a cap on the post, mounting a semiconductor device on a heat spreader that includes the post, the base and the cap, electrically connecting the semiconductor device to the conductive trace and thermally connecting the semiconductor device to the heat spreader.

Abstract: A semiconductor device has a first substrate with a central region. A plurality of bumps is formed around a periphery of the central region of the first substrate. A first semiconductor die is mounted to the central region of the first substrate. A second semiconductor die is mounted to the first semiconductor die over the central region of the first substrate. A height of the first and second die is less than or equal to a height of the bumps. A second substrate has a thermal conduction channel. A surface of the second semiconductor die opposite the first die is mounted to the thermal conductive channel of the second substrate. A thermal interface layer is formed over the surface of the second die. The bumps are electrically connected to contact pads on the second substrate. A conductive plane is formed over a surface of the second substrate.

Abstract: An insulated metal substrate composite has a patterned conductive layer on one surface and receives one or more electrodes of MOSFETs or other die on the patterned segments which lead to the edge of the IMS. The outer periphery of the IMS is cupped or bent to form a shallow can with two or more die fixed to and thermally coupled to the flat web of the can while electrodes on the die surfaces thermally coupled to the web of the can lead to terminals on the rim of the can which are coplanar with the bottom surfaces of the die. The electrodes can be externally or internally connected to form a half bridge circuit.

Abstract: A method of fabricating a leadframe-based semiconductor package, and a semiconductor package formed thereby, are disclosed. The semiconductor package includes a leadframe and one or more semiconductor die affixed to a die paddle of the leadframe. The leadframe is formed with a plurality of electrical terminals that get surface mounted to a host PCB. The leadframe further includes one or more extended leads, at least one of which includes an electrically conductive island which gets surface mounted to the host PCB with the electrical terminals. The islands effectively increase the number terminals within the package without adding footprint to the package.

Abstract: One aspect relates to a power semiconductor arrangement includes a power semiconductor module which is mechanically connected to a heat sink. In order to improve the thermal cycling stability of the connection between a baseplate of the module and a circuit carrier connected thereto, recesses are provided in the baseplate. One aspect further relates to a power semiconductor module.

Abstract: A semiconductor device has a substrate having a top and bottom surface and a plurality of metal layers. A first die is electrically coupled to the top surface of the substrate. A lid member is attached to a top surface of the die and to the top surface of the substrate. A layering is formed on portions of a top surface of the lid member. The layering will have a different coefficient of thermal expansion (CTE) than the lid member.

Abstract: A heat-conducting medium for placement between a heat source and heat sink to facilitate transfer of heat from the source to the sink is provided. The heat-conducting medium can include a flexible member made from an array of interweaving carbon nanotubes. The heat-conducting medium may also include an upper surface against which a heat source may be placed, an opposing lower surface and edges about the member designed for coupling to a heat sink toward which heat from the heat source can be directed. The heat-conducting medium may also include a pad placed on the upper surface to provide structural support to the member. A method for manufacturing the heat-conducting medium is also provided.

Abstract: A high reliability power module which includes a plurality of hermetically sealed packages each having electrical terminals formed from an alloy of tungsten copper and brazed onto a surface of a ceramic substrate.

Abstract: Disclosed is a method of forming a substrate having islands of diamond (or other material, such as diamond-like carbon), as well as integrated circuit devices formed from such a substrate. A diamond island can form part of the thermal solution for an integrated circuit formed on the substrate, and the diamond island can also provide part of a stress engineering solution to improve performance of the integrated circuit. Other embodiments are described and claimed.

Abstract: Various methods and apparatus for establishing a thermal pathway for a semiconductor device are disclosed. In one aspect, a method of manufacturing is provided that includes placing a gel-type thermal interface material in a preselected pattern on a semiconductor chip that is coupled to a substrate. The preselected pattern of gel-type thermal interface material is allowed to partially set up. Additional thermal interface material is placed on the semiconductor chip and cured.

Abstract: A method of manufacturing a micromechanical element wherein the method comprises the steps of providing a layer of base material, applying at least one at least partly sacrificial layer of an etchable material, patterning the at least partly sacrificial layer, to define at least a portion of the shape of the element, applying at least one structural layer of a mechanical material, patterning the structural layer to form at least a portion of the element, and removing at least partly the patterned at least partly sacrificial layer to release partly free the element. The mechanical material is selected from the group of conductive materials.

Abstract: A semiconductor device is provided which comprises a thermally radiative and electrically conductive support plate 1; and a regulatory semiconducting element 2 mounted on one main surface of support plate 1 through an insulator 3. Insulator 3 comprises an insulative layer 3a mounted on support plate 1 and an adiabatic layer 3b interposed between insulative layer 3a and regulatory semiconducting element 2 to fully protect regulatory semiconducting element 2 from heated environment therearound in the semiconductor device.

Abstract: A method of manufacturing a semiconductor device using a wiring substrate is provided which can facilitate the handling of the wiring substrate. The method includes the steps of forming a peelable resin layer on a silicon substrate, forming the wiring substrate on the peelable resin layer, mounting semiconductor chips on the wiring substrate, forming semiconductor devices by sealing the plurality of semiconductor chips by a sealing resin, individualizing the semiconductor devices by dicing the semiconductor devices from the sealing resin side but leaving the silicon substrate, peeling each of the individualized semiconductor devices from the silicon substrate between the silicon substrate and the peelable resin layer, and exposing terminals on the wiring substrate by forming openings through the peelable resin layer or by removing the peelable resin layer.

Abstract: The invention relates to a metal-ceramic substrate for electric circuits or modules, said substrate including a ceramic layer which is provided with at least one metallic layer of a first type applied to a surface of said ceramic layer in a plane manner. An insulating layer made up of a glass-containing material is applied to at least one partial region of a surface of the metallic layer of the first type, said surface opposing the ceramic layer, and a metallic layer of a second type is applied to the insulating layer, the insulating layer and the metallic layer of a second type respectively being thinner then the ceramic layer and the metallic layer of the first type.

Abstract: A heat dissipation plate having a lamination of a copper layer, a molybdenum layer and a graphite layer, and outer copper layers each provided on a surface of the lamination, is disclosed. And also a semiconductor device using the heat dissipation plate is disclosed.

Abstract: A method (20) of packaging integrated circuit dies (70) includes obtaining (22) a heat spreader substrate (24) having a top surface (38) with cavities (30) formed therein, each of the cavities (30) having a cavity floor (44). A surface (74) of each die (70) is attached (66) to one of the cavity floors (44) such that a surface (72) of each die (70) and the top surface (38) of the substrate (24) are coplanar. Build-up layers (88) with electrical interconnects (97) are formed (86) over the surface (72) of each die (80) and the surface (38) of the substrate (24) to form a panel (68) of IC dies (70). Following formation of the build-up layers (88), the panel (68) is separated (108) into multiple integrated circuit packages (28), each including electrical interconnects (97), a die (70), and the substrate (24) for dissipating heat away from the die (70) during operation.

Abstract: In some embodiments, an alternative to desmear for build-up roughening and copper adhesion promotion is presented. In this regard, a substrate in introduced having a dielectric layer, a plurality of polyelectrolyte multilayers on the dielectric layer, and a copper plating layer on the polyelectrolyte multilayers. Other embodiments are also disclosed and claimed.

Abstract: An electronic package which includes a substrate (e.g., a chip carrier substrate or a PCB), an electronic component (e.g., a semiconductor chip), a heatsink and a thermal interposer for effectively transferring heat from the chip to the heatsink. The interposer includes a compressible, resilient member (e.g., an elastomeric pad) and a plurality of thin, metallic sheets (e.g., copper foils) and the thickness thereof can be adjusted by altering the number of such foils.

Abstract: A package-on-package system includes: providing a base substrate; mounting an integrated circuit on the base substrate; positioning a stacking interposer over the integrated circuit; and forming a heat spreader base around the integrated circuit by coupling the base substrate and the stacking interposer to the heat spreader base.

Abstract: A packaged integrated circuit having a thermal pathway to exhaust heat from the integrated circuit. The integrated circuit is disposed on a package substrate, with an encapsulant disposed around the integrated circuit. A heat sink is disposed at least partially within the encapsulant, with at least a portion of one surface of the heat sink exposed outside of the encapsulant. The integrated circuit has an uppermost passivation layer, where the passivation layer is not electrically conductive, with a port disposed in the passivation layer. The port extends completely through the passivation layer to expose an underlying layer. A thermal pathway is disposed at least partially within the port, and makes thermal contact to both the underlying layer and the heat sink. The thermal transfer rate of the thermal pathway is greater than the thermal transfer rate either the passivation layer or the encapsulant.

Abstract: A package substrate for a multi-package module. The package substrate comprises a substrate having a die region and at least one thermal channel region outwardly extending to an edge of the substrate from the die region. An array of bumps is arranged on the substrate except in the die and thermal channel regions, in which the interval between the bumps is narrower than the width of the thermal channel region. An electronic device with a package substrate is also disclosed.

Abstract: A method may provide thermal interface material. The method comprises providing a first coating layer on a top side of a base metal layer and a second coating layer on a bottom side of the base metal layer, wherein the coating layer has a melting point lower than a melting point of the base metal layer; attaching the base metal layer to a die and a heat spreader; and melting the first coating layer and the second coating layer to bond to the die and the heat spreader.

Abstract: Disclosed is a method of forming a substrate having islands of diamond (or other material, such as diamond-like carbon), as well as integrated circuit devices formed from such a substrate. A diamond island can form part of the thermal solution for an integrated circuit formed on the substrate, and the diamond island can also provide part of a stress engineering solution to improve performance of the integrated circuit. Other embodiments are described and claimed.

Abstract: Techniques for integrated circuit device fabrication are provided. In one aspect, an integrated circuit device comprises a base, at least one die attached to the base, and a counterbalancing layer on at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die. In another aspect, warping of an integrated circuit device comprising at least one die attached to a base is controlled by applying a counterbalancing layer to at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die.

Abstract: A semiconductor device has a first substrate with a central region. A plurality of bumps is formed around a periphery of the central region of the first substrate. A first semiconductor die is mounted to the central region of the first substrate. A second semiconductor die is mounted to the first semiconductor die over the central region of the first substrate. A height of the first and second die is less than or equal to a height of the bumps. A second substrate has a thermal conduction channel. A surface of the second semiconductor die opposite the first die is mounted to the thermal conductive channel of the second substrate. A thermal interface layer is formed over the surface of the second die. The bumps are electrically connected to contact pads on the second substrate. A conductive plane is formed over a surface of the second substrate.