Metallic Materials (epo) Patents (Class 257/E23.109)
  • Patent number: 9862155
    Abstract: A method for making an electrothermal actuator requires a carbon nanotube paper being provided. The carbon nanotube paper is cut along a cutting-line to form a patterned carbon nanotube paper. At least two electrodes are formed on the patterned carbon nanotube paper. Finally, the electrothermal actuator is obtained by forming a flexible polymer layer on the patterned carbon nanotube paper.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: January 9, 2018
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Qing-Wei Li, Chang-Hong Liu, Shou-Shan Fan
  • Patent number: 8987895
    Abstract: A clad material 1A for insulating substrates is provided with a Ni layer 4 made of Ni or a Ni alloy, a Ti layer 6 made of Ti or a Ti alloy and arranged on one side of the Ni layer, and a first Al layer 7 made of Al or an Al alloy and arranged on one side of the Ti layer 6 that is opposite to a side of the Ti layer 6 on which the Ni layer 4 is arranged. The Ni layer 4 and the Ti layer 6 are joined by clad rolling. A Ni—Ti series superelastic alloy layer 5 formed by alloying at least Ni of constituent elements of the Ni layer 4 and at least Ti of constituent elements of the Ti layer 6 is interposed between the Ni layer 4 and the Ti layer 6. The Ti layer 6 and the first Al layer 7 are joined by clad rolling in an adjoining manner.
    Type: Grant
    Filed: October 25, 2011
    Date of Patent: March 24, 2015
    Assignee: Showa Denko K.K.
    Inventors: Atsushi Otaki, Shigeru Oyama
  • Patent number: 8921996
    Abstract: A power module substrate includes: a ceramics substrate having a surface; and a metal plate connected to the surface of the ceramics substrate, composed of aluminum, and including Cu at a joint interface between the ceramics substrate and the metal plate, wherein a Cu concentration at the joint interface is in the range of 0.05 to 5 wt %.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: December 30, 2014
    Assignee: Mitsubishi Materials Corporation
    Inventors: Yoshirou Kuromitsu, Yoshiyuki Nagatomo, Takeshi Kitahara, Hiroshi Tonomura, Kazuhiro Akiyama
  • Patent number: 8860209
    Abstract: Disclosed is a luminaire, comprising a front convective heat sink, a rear convective heat sink, and a removable thin printed circuit board. The front convective heat sink has at least one optical aperture. The removable thin printed circuit board has an electrically-insulated back surface and a selectively electrically-insulated front surface. The front surface has exposed electrical contacts in at least one area corresponding to the at least one optical aperture. The removable thin printed circuit board is sandwiched between the front and rear convective heat sinks with a compressive force.
    Type: Grant
    Filed: August 13, 2011
    Date of Patent: October 14, 2014
    Assignee: NuLEDs, Inc.
    Inventor: Chris Isaacson
  • Patent number: 8803305
    Abstract: A hybrid interconnect includes a through silicon via and a wire bond. Hybrid interconnects enable better layout of a stacked IC by combining benefits from both interconnect technologies. In one hybrid interconnect, wire bonds couples a second tier die mounted on a first tier die to a redistribution layer in the first tier die. Through silicon vias in the first tier die are coupled to the wire bonds to provide communication. In another hybrid interconnect, a wire bond couples a redistribution layer on a first tier die to a packaging substrate on which the first tier die is mounted. The redistribution layer couples to a second tier die mounted on the first tier die to provide a power supply to the second tier die. Through silicon vias in the first tier die couple to the second tier die to provide communication from the packaging substrate to the second tier die.
    Type: Grant
    Filed: November 18, 2009
    Date of Patent: August 12, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Ratibor Radojcic, Arvind Chandrasekaran, Ryan Lane
  • Patent number: 8765568
    Abstract: A structure and method of fabricating the structure includes a semiconductor substrate having a top surface defining a horizontal direction and a plurality of interconnect levels stacked from a lowermost level proximate the top surface of the semiconductor substrate to an uppermost level furthest from the top surface. Each of the interconnect levels include vertical metal conductors physically connected to one another in a vertical direction perpendicular to the horizontal direction. The vertical conductors in the lowermost level being physically connected to the top surface of the substrate, and the vertical conductors forming a heat sink connected to the semiconductor substrate. A resistor is included in a layer immediately above the uppermost level. The vertical conductors being aligned under a downward vertical resistor footprint of the resistor, and each interconnect level further include horizontal metal conductors positioned in the horizontal direction and being connected to the vertical conductors.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: July 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Joseph M. Lukaitis, Deborah M. Massey, Timothy D. Sullivan, Ping-Chuan Wang, Kimball M. Watson
  • Patent number: 8664759
    Abstract: An integrated circuit die includes a substrate having an upper surface, at least one active device formed in a first area of the upper surface of the substrate, and a plurality of layers formed on the upper surface of the substrate above the at least one active device. A first stacked heat conducting structure is provided, spanning from a point proximate the first area of the upper surface of the substrate through the plurality of layers. A lateral heat conducting structure is formed above the uppermost layer of the plurality of layers and in thermal contact with the first stacked heat conducting structure. The invention advantageously facilitates the dissipation of heat from the integrated circuit die, particularly from high-power sources or other localized hot spots.
    Type: Grant
    Filed: June 22, 2005
    Date of Patent: March 4, 2014
    Assignee: Agere Systems LLC
    Inventor: Vivian Ryan
  • Patent number: 8564118
    Abstract: A power module substrate includes: a ceramics substrate having a surface; and a metal plate connected to the surface of the ceramics substrate, composed of aluminum, and including Cu at a joint interface between the ceramics substrate and the metal plate, wherein a Cu concentration at the joint interface is in the range of 0.05 to 5 wt %.
    Type: Grant
    Filed: June 5, 2009
    Date of Patent: October 22, 2013
    Assignee: Mitsubishi Materials Corporation
    Inventors: Yoshirou Kuromitsu, Yoshiyuki Nagatomo, Takeshi Kitahara, Hiroshi Tonomura, Kazuhiro Akiyama
  • Patent number: 8441122
    Abstract: A semiconductor device includes a first protection film for covering a first metal wiring. A second protection film is disposed on the first protection film, which is covered with a solder layer. Even if a crack is generated in the second protection film before the solder layer is formed on the second protection film, the crack is restricted from proceeding into the first protection film.
    Type: Grant
    Filed: August 17, 2010
    Date of Patent: May 14, 2013
    Assignee: Denso Corporation
    Inventors: Daisuke Fukuoka, Takanori Teshima, Kuniaki Mamitsu, Ken Sakamoto, Tetsuo Fujii, Akira Tai, Kazuo Akamatsu, Masayoshi Nishihata
  • Publication number: 20130112993
    Abstract: A semiconductor device according to one embodiment of the present invention includes an insulating substrate, a wiring layer formed on a first main surface of the insulating substrate and having a conductive property, and a semiconductor element mounted on the wiring layer. In the semiconductor device, the insulating substrate is composed of cBN or diamond.
    Type: Application
    Filed: October 26, 2012
    Publication date: May 9, 2013
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventor: Sumitomo Electric Industries, Ltd.
  • Patent number: 8299604
    Abstract: A ceramic assembly includes one or more electrically and thermally conductive pads to be thermally coupled to a heat generating device, each conductive pad is electrically isolated from each other. The ceramic assembly includes a ceramic layer to provide this electrical isolation. The ceramic layer has high thermal conductivity and high electrical resistivity. A top surface and a bottom surface of the ceramic layer are each bonded to a conductive layer, such as copper, using an intermediate joining material. A brazing process is performed to bond the ceramic layer to the conductive layer via a joining layer. The joining layer is a composite of the joining material, the ceramic layer, and the conductive layer. The top conductive layer and the joining layer are etched to form the electrically isolated conductive pads. The conductive layers are bonded to the ceramic layer using a bare ceramic approach or a metallized ceramic approach.
    Type: Grant
    Filed: August 5, 2009
    Date of Patent: October 30, 2012
    Assignee: Cooligy Inc.
    Inventors: Madhav Datta, Mark McMaster
  • Patent number: 8283773
    Abstract: A semiconductor device includes an insulating substrate having a ceramic substrate and metal coating layers on opposite surfaces of the ceramic substrate, a semiconductor chip mounted on one surface of the insulating substrate, a heat sink directly or indirectly fixed to the other surface of the insulating substrate and thermally connected to the semiconductor chip through the insulating substrate and at least one anti-warping sheet disposed on at least one surface of the heat sink. The anti-warping sheet is made of a metal sheet having a coating layer and has coefficient of thermal expansion between those of the insulating substrate and the heat sink.
    Type: Grant
    Filed: February 2, 2010
    Date of Patent: October 9, 2012
    Assignee: Kabushiki Kaisha Toyota Jidoshokki
    Inventors: Shogo Mori, Eiji Kono, Keiji Toh
  • Patent number: 8159066
    Abstract: A semiconductor package having a heat dissipation member capable of efficiently conveying excess heat away from semiconductor chips is presented. The semiconductor package includes a semiconductor chip, through-electrodes, and a heat dissipation member. The semiconductor chip has a first surface, a second surface facing away from the first surface, and bonding pads which are disposed on the first surface. The through-electrodes are electrically connected with the bonding pads and passing through the first and second surfaces of the semiconductor chip, and protrude outward from the second surface. The heat dissipation member faces the second surface of the semiconductor chip and is coupled to the through-electrodes.
    Type: Grant
    Filed: December 16, 2009
    Date of Patent: April 17, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Seung Taek Yang
  • Patent number: 8026596
    Abstract: Gallium nitride material devices and methods associated with the devices are described. The devices may be designed to provide enhanced thermal conduction and reduced thermal resistance. The increased thermal conduction through and out of the gallium nitride devices enhances operability of the devices, including providing excellent RF operation, reliability, and lifetime.
    Type: Grant
    Filed: August 15, 2007
    Date of Patent: September 27, 2011
    Assignee: International Rectifier Corporation
    Inventors: Sameer Singhal, Andrew Edwards, Chul H. Park, Quinn Martin, Isik C. Kizilyalli
  • Patent number: 7928553
    Abstract: An electronic device and method is disclosed. In one embodiment, a method includes providing an electrically insulating substrate. A first electrically conductive layer is applied over the electrically insulating substrate. A first semiconductor chip is placed over the first electrically conductive layer. The first semiconductor chip comprises a first electrode on a first main surface and a second electrode on a second main surface. An electrically insulating layer is applied over the first electrically conductive layer. A second electrically conductive layer is applied over the electrically insulating layer. A through connection is provided in the electrically insulating layer to couple the first electrically conductive layer to the second electrically conductive layer.
    Type: Grant
    Filed: August 2, 2010
    Date of Patent: April 19, 2011
    Assignee: Infineon Technologies AG
    Inventors: Ralf Otremba, Oliver Haeberlen, Klaus Schiess
  • Publication number: 20110074010
    Abstract: A power module substrate includes: a ceramics substrate having a surface; and a metal plate connected to the surface of the ceramics substrate, composed of aluminum, and including Cu at a joint interface between the ceramics substrate and the metal plate, wherein a Cu concentration at the joint interface is in the range of 0.05 to 5 wt %.
    Type: Application
    Filed: June 5, 2009
    Publication date: March 31, 2011
    Applicant: MITSUBISHI MATERIALS CORPORATION
    Inventors: Yoshirou Kuromitsu, Yoshiyuki Nagatomo, Takeshi Kitahara, Hiroshi Tonomura, Kazuhiro Akiyama
  • Patent number: 7834443
    Abstract: A semiconductor includes a board, a semiconductor element mounted on the board, an electronic component, with the semiconductor element, mounted on the board, a heat radiation member provided so as to face the board, the heat radiation member configured to radiate heat of the semiconductor element, and a thermal connecting member being configured to thermally connect the heat radiation member and the semiconductor element. A metal material is used as the thermal connecting member, and an adhesion preventing member is provided so as to be separated from the electronic component, the adhesion preventing member being configured to prevent the metal material molten and flowing at a heating time being adhered to the electronic component.
    Type: Grant
    Filed: August 5, 2008
    Date of Patent: November 16, 2010
    Assignee: Fujitsu Limited
    Inventors: Tsuyoshi So, Hideo Kubo
  • Publication number: 20100237479
    Abstract: A method and apparatus are provided for manufacturing a lead frame based, over-molded semiconductor package (7) with an exposed pad or power die flag (70) having multiple integrated THT heat spreader pins (71) configured for insertion into one or more vias (77) formed in a printed circuit board (78). The through hole heat spreader pins (71) may be formed as an integral part of the exposed pad (52) or may be solidly connected with the exposed pad (62).
    Type: Application
    Filed: June 11, 2010
    Publication date: September 23, 2010
    Inventors: Robert Bauer, Anton Kolbeck
  • Patent number: 7799614
    Abstract: An electronic device and method is disclosed. In one embodiment, a method includes providing an electrically insulating substrate. A first electrically conductive layer is applied over the electrically insulating substrate. A first semiconductor chip is placed over the first electrically conductive layer. An electrically insulating layer is applied over the first electrically conductive layer. A second electrically conductive layer is applied over the electrically insulating layer. A through connection is formed in the electrically insulating layer to couple the second electrically conductive layer to the first electrically conductive layer.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: September 21, 2010
    Assignee: Infineon Technologies AG
    Inventors: Ralf Otremba, Oliver Haeberlen, Klaus Schiess
  • Patent number: 7755184
    Abstract: A metal thermal interface structure for dissipating heat from electronic components comprised a heat spreader lid, metal alloy that is liquid over the operating temperature range of the electronic component, and design features to promote long-term reliability and high thermal performance.
    Type: Grant
    Filed: December 8, 2006
    Date of Patent: July 13, 2010
    Inventors: Chris Macris, Robert George Ebel
  • Patent number: 7663227
    Abstract: A metal thermal interface structure for dissipating heat from electronic components comprised a heat spreader lid, metal alloy that is liquid over the operating temperature range of the electronic component, and design features to promote long-term reliability and high thermal performance.
    Type: Grant
    Filed: February 8, 2008
    Date of Patent: February 16, 2010
    Inventors: Chris G. Macris, Robert G. Ebel, John C. McCullough
  • Patent number: 7651938
    Abstract: Thermal interface materials and method of using the same in packaging are provided. In one aspect, a thermal interface material is provided that includes an indium preform that has a first surface and a second surface opposite to the first surface, an interior portion and a peripheral boundary. The indium preform has a channel extending from the peripheral boundary towards the interior portion. The channel enables flux to liberate during thermal cycling.
    Type: Grant
    Filed: June 7, 2006
    Date of Patent: January 26, 2010
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Seah Sun Too, Hsiang Wan Liau, Janet Kirkland, Tek Seng Tan, Maxat Touzelbaev, Raj N. Master
  • Publication number: 20090283879
    Abstract: A chip carrier includes first, second and third layers with the second layer situated between the first and third layers. The first and third layers are formed of a first material and the second layer is formed of a second material. The second layer has a plurality of holes extending therethrough and the first material fills the holes.
    Type: Application
    Filed: May 13, 2008
    Publication date: November 19, 2009
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Alexander Heinrich, Klaus Schiess, Joachim Mahler
  • Patent number: 7554190
    Abstract: A metal thermal interface structure for dissipating heat from electronic components comprised a heat spreader lid, metal alloy that is liquid over the operating temperature range of the electronic component, and design features to promote long-term reliability and high thermal performance.
    Type: Grant
    Filed: October 11, 2005
    Date of Patent: June 30, 2009
    Inventors: Chris Macris, Thomas R. Sanderson, Robert G. Ebel
  • Patent number: 7528482
    Abstract: A Chip-in Substrate Package (CiSP) includes a double-sided metal clad laminate including a dielectric interposer, a first metal foil laminated on a first side of the dielectric interposer, and a second metal foil laminated on a second side of the dielectric interposer. A recessed cavity is etched into the second metal foil and the dielectric interposer with a portion of the first metal foil as its bottom. A die is mounted within the recessed cavity and makes thermal contact with the first metal foil. A build-up material layer covers the second metal foil and an active surface of the die. The build-up material layer also fills the gap between the die and the dielectric interposer. At least one interconnection layer is provided on the build-up material layer and is electrically connected with a bonding pad disposed on the active surface of the die via a plated through hole.
    Type: Grant
    Filed: February 7, 2007
    Date of Patent: May 5, 2009
    Assignee: Nan Ya Printed Circuit Board Corporation
    Inventors: Cheng-Hung Huang, Hsien-Chieh Lin, Kuo-Chun Chiang, Shing-Fun Ho
  • Publication number: 20090108437
    Abstract: Various embodiments are directed to providing an electronic device with an integrated thermal heat spreader. In one embodiment, an electronic device may comprise an integrated circuit fabricated on a substrate and a heat spreader integrated with the electronic device after fabrication of the integrated circuit. The heat spreader may comprise one or more layers of composite plating material including solid particles incorporated into a metal plating material. The composite plating material may be patterned to the substrate to define the heat spreader. Other embodiments are described and claimed.
    Type: Application
    Filed: October 29, 2007
    Publication date: April 30, 2009
    Applicant: M/A-COM, INC.
    Inventor: Brook D. Raymond
  • Publication number: 20090045505
    Abstract: A package module is provided. The package module comprises a substrate having a surface comprising a die region. A die is disposed in the die region of the surface on the substrate. A flexible heat spreader conformally covers the surface of the substrate and the die. The invention also discloses an electronic device with the package module.
    Type: Application
    Filed: October 12, 2007
    Publication date: February 19, 2009
    Applicant: VIA TECHNOLOGIES, INC.
    Inventor: Chi-Hsing Hsu
  • Publication number: 20080266809
    Abstract: A thermal conducting mixture is provided which is used to make thermal conducting formulations such as a paste having a high thermal conductivity and a relatively low viscosity. The paste is used to provide a thermal conductor connection between an electronic component and a cooling device to increase the heat transfer rate between the component and the device cooling the electronic component. The formulation contains the mixture of thermally conductive particles in various particle size ranges typically dispersed in a non-aqueous dielectric carrier containing an antioxidant and a dispersant with the thermally conductive particles mixture being specially correlated in the mixture by volume % based on particle size range and by particle size ratio of each particle size range. The mixture may be used to make other similar products such as thermal gels, adhesives, slurries and composites, for electronic and cosmetics, pharmaceuticals, automotive, and like products.
    Type: Application
    Filed: April 25, 2007
    Publication date: October 30, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Rajneesh Kumar, Steven P. Ostrander
  • Patent number: 7427807
    Abstract: This invention discloses a manufacturing method and a structure for a chip heat dissipation. This heat dissipation structure includes a bottom plate of circuit structure, a die of central processing unit and a cap. The cover is often used in conducting the waste heat generated from the chip. The cover can be made of a special thermal conduction material, including a metal and a bracket structure of carbon element which have high thermal conductivity so as to improve the efficiency of heat conduction. The corresponding manufacturing method for this heat conduction material can be made with chemical vapor deposition, physical vapor deposition, electroplating or the other materials preparation method. The bracket structure of carbon element can be coated on the metal surface and also can be mixed into the metal.
    Type: Grant
    Filed: February 17, 2006
    Date of Patent: September 23, 2008
    Assignee: Mitac Technology Corp.
    Inventors: Ming-Hang Hwang, Yu-Chiang Cheng, Chao-Yi Chen, Ping-Feng Lee, Hsin-Lung Kuo, Bin-Wei Lee, Wei-Chung Hsiao
  • Patent number: 7388286
    Abstract: A semiconductor package comprising a semiconductor chip and a first heat spreader adhered to the upper surface of the semiconductor chip is provided. The first heat spreader comprises a flat metal plate and a plurality of metal balls adhered to the flat metal plate. A method of fabricating the semiconductor chip package is also provided.
    Type: Grant
    Filed: December 22, 2005
    Date of Patent: June 17, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-uk Kim, Yun-hyeok Im
  • Publication number: 20080136015
    Abstract: A high power semiconductor package includes a substrate including a base metal layer, a base insulation layer formed on the base metal layer, and a plurality of conductive patterns formed on the base insulation layer. In one embodiment one or more high power semiconductor chips are mounted on the substrate, each including a plurality of bonding pads, one or more first package leads having end portions that are electrically connected to the corresponding conductive patterns, and a second lead having an end portion electrically which may be connected to either the base insulation layer or the base metal layer.
    Type: Application
    Filed: December 6, 2007
    Publication date: June 12, 2008
    Applicant: Fairchild Korea Semiconductor, Ltd.
    Inventors: Keun-hyuk Lee, Seung-won Lim
  • Patent number: 7378730
    Abstract: Layered interface materials described herein include at least one pulse-plated thermally conductive material, such as an interconnect material, and at least one heat spreader component coupled to the at least one pulse-plated thermally conductive material. A plated layered interface material having a migration component is also described herein and includes at least one pulse-plated thermally conductive material; and at least one heat spreader component, wherein the migration component of the plated layered interface material is reduced by at least 51% as compared to the migration component of a reference layered interface material. Another layered interface material described herein includes: a) a thermal conductor; b) a protective layer; c) a layer of material accept solder and prevent the formation of oxides; and d) a layer of solder material.
    Type: Grant
    Filed: February 13, 2004
    Date of Patent: May 27, 2008
    Assignee: Honeywell International Inc.
    Inventors: Mark Fery, Jai Subramanian
  • Patent number: 7345364
    Abstract: A thermally conductive structure for a semiconductor integrated circuit and a method for making the structure. The structure comprises one or more vertical and/or horizontal thermally conductive elements disposed proximate a device for improving thermal conductivity from the device to a substrate of the integrated circuit. In one embodiment a heat sink is affixed to the integrated circuit for heat flow from the integrated circuit. The method comprises forming openings in material layers overlying the semiconductor substrate, wherein the openings are disposed proximate the device and extend to the substrate. A thermally conductive material is formed in the openings to provide a thermal path from the device to the substrate.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: March 18, 2008
    Assignee: Agere Systems Inc.
    Inventors: Daniel Charles Kerr, Alan Sangone Chen, Edward Paul Martin, Jr., Amal Ma Hamad, William A. Russell
  • Patent number: 7183641
    Abstract: Integrated heat spreader and die coupled with solder in a manner forming an intermetallic compound having a higher liquidus temperature than the liquidus temperature of the solder used to create the intermetallic compound are described herein.
    Type: Grant
    Filed: March 30, 2005
    Date of Patent: February 27, 2007
    Assignee: Intel Corporation
    Inventors: Mukul P. Renavikar, Susheel G. Jadhav
  • Publication number: 20070037346
    Abstract: A method for rapid thermal annealing of thin film layers is provided. The method directs a series of pulses or flashes of heat energy toward a targeted layer on a substrate. Each pulse may be at a first temperature range sufficient to anneal the targeted layer, but has a duration that is less than that necessary to render the targeted layer substantially annealed. Moreover, in succession, the series of pulses can incrementally raise the targeted layer to a temperature sufficient for annealing, while minimizing exposure of the remaining layers to the pulses of heat energy. A reactor for implementing the rapid thermal annealing process is also provided.
    Type: Application
    Filed: June 30, 2006
    Publication date: February 15, 2007
    Inventor: Robert Grant
  • Patent number: 7169650
    Abstract: To accommodate high power densities associated with high performance integrated circuits, an integrated circuit package includes a heat-dissipating structure in which heat is dissipated from a surface of a die to an integrated heat spreader (IHS) through a high capacity thermal interface formed of metal that has been injected in a semi-solid state. In one embodiment, vacuum and a shear-controlled viscosity enable semi-solid metallic material to fill a narrow chamber between the die surface and a specially shaped mold plate that doubles as an IHS, without inducing voids in the solidified metal. In another embodiment, an injection machine is disclosed. Methods of fabrication, as well as application of the package to an electronic assembly and to an electronic system, are also described.
    Type: Grant
    Filed: July 30, 2004
    Date of Patent: January 30, 2007
    Assignee: Intel Corporation
    Inventors: Agostino C. Rinella, Paul A. Koning
  • Publication number: 20060220226
    Abstract: Integrated heat spreader and die coupled with solder in a manner forming an intermetallic compound having a higher liquidus temperature than the liquidus temperature of the solder used to create the intermetallic compound are described herein.
    Type: Application
    Filed: March 30, 2005
    Publication date: October 5, 2006
    Applicant: Intel Corporation
    Inventors: Mukul Renavikar, Susheel Jadhav
  • Patent number: 7105922
    Abstract: The invention relates to a method of manufacturing a semiconductor device (10), wherein a semiconductor element (1) provided with a number of connection regions (2) is fitted between a first, electroconductive plate (3) and a second plate (4), wherein two connection conductors (3A, 3B) are formed, from the first plate (3), for the two connection regions (2A, 2B) of the element (1), wherein a passivating encapsulation (5) is provided between the plates (3, 4) and around the element (1), and wherein the device (10) is formed by applying a mechanical separating technique in two mutually perpendicular directions (L, M). In a method according to the invention, the connection conductors (3A, 3B) are formed by providing a mask (6) on the first conducting plate (3) in such a manner that a part (3C) of the plate (3) situated between the connection regions (2A, 2B) remains exposed, which part is subsequently removed by etching.
    Type: Grant
    Filed: February 24, 2005
    Date of Patent: September 12, 2006
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Johannus Wilhelmus Weekamp, Marc Andre De Samber, Durandus Kornelius Dijken
  • Publication number: 20060121732
    Abstract: A circuit package includes a substrate having an opening and a single unitary heat sink adapted to effectively dissipate heat is positioned in the opening to expose top and bottom surfaces which are respectively coplanar with top and bottom surfaces of the substrate. Selective plating includes applying first and second metal patterns to a substrate surface, creating a potential voltage difference between the first metal pattern and a metal source, and plating the first metal pattern by attracting a first metal type to the voltage potential of the first metal pattern. The voltage potential of the first metal pattern is less than the voltage potential of the metal source.
    Type: Application
    Filed: January 18, 2006
    Publication date: June 8, 2006
    Inventors: Xiaowei Yao, Tam Nguyen, Marc Finot, Rickie Lake, Jeffrey Bennett, Robert Kohler
  • Patent number: RE39992
    Abstract: A thermally conductive mechanically compliant pad including a quantity of gallium and/or indium alloy liquid at temperatures below about 120° C. and a boron nitride particulate solid blended into the liquid metal alloy to form a paste. The paste is then combined with a quantity of a matrix forming flowable plastic resin such as microwax, silicone wax, or other silicone polymer to form the thermally conductive mechanically compliant pad, the compliant pad comprising from between about 10% and 90% of metal alloy coated particulate, balance flowable plastic resin.
    Type: Grant
    Filed: May 4, 2005
    Date of Patent: January 1, 2008
    Assignee: The Bergquist Company
    Inventors: Sanjay Misra, GM Fazley Elahee