Abstract: A chip package structure, including a substrate, multiple chips and multiple discrete devices that are packaged on an upper surface of the substrate, and a heat dissipation apparatus, where the heat dissipation apparatus includes an insulation layer and a thermally conductive layer that are laminated. The insulation layer completely encloses and adheres to outer surfaces of the multiple chips, outer surfaces of the multiple discrete devices, and the upper surface of the substrate and configured to conduct heat generated by the multiple chips and the multiple discrete devices to the thermally conductive layer and the substrate such that the heat generated by the multiple chips and the multiple discrete devices dissipated using the thermally conductive layer and the substrate.

Abstract: Disclosed is a method of manufacturing a metal matrix composite in which oxide nanoparticles are dispersed. Metal matrix composite powders in which oxide nanoparticles are dispersed are prepared. Gibbs free energy of the oxide nanoparticles is greater than that of an oxide of a metal matrix. A bulk processed material is manufactured from the composite powders through hot forming or a cast material is manufactured by inputting the composite powder into a molten base metal and then rapidly stirring a resultant mixture. The bulk processed material or the cast material is heat-treated so that atoms of the metal matrix and atoms of the oxide nanoparticles mutually diffuse. Oxygen atoms originating from the oxide nanoparticles are diffused and dispersed in the metal matrix.

Abstract: An aluminum-diamond composite that exhibits both high thermal conductivity and a coefficient of thermal expansion close to that of semiconductor devices, and that can suppress the occurrence of swelling, etc., of a surface metal layer portion even in actual use under a high load. An aluminum-diamond composite includes 65-80 vol % of a diamond powder having a roundness of at least 0.94, for which a first peak in a volumetric distribution of grain size lies at 5-25 ?m, and a second peak lies at 55-195 ?m, and a ratio between the area of the volumetric distribution of grain sizes of 1-35 ?m and the area of the volumetric distribution of grain sizes of 45-205 ?m is from 1:9 to 4:6; the balance being composed of a metal containing aluminum.

Abstract: A heat sink can be attached to a heat-producing electronic device by aligning an adhesive material to a surface of the heat sink, applying the adhesive material to the surface to form an outer perimeter and applying, within the outer perimeter, a thermally conductive material to the surface. The surface of the heat sink and a surface of the heat-producing electronic device can then be aligned, and the heat sink can be assembled to the heat-producing electronic device by bringing the heat-producing electronic device surface into contact with the adhesive material. The heat sink can then be affixed to the heat-producing electronic device by applying a compressive force to the assembly to activate the adhesive material.

Abstract: [Problem] To provide a heat spreader capable of removing heat from an element more efficiently and immediately than an existing one, and also capable of satisfactorily responding to further enhancement in performance and output of various apparatuses, and a method for efficiently manufacturing the same. [Solution] A heat spreader includes a Cu—Mo layer made of a Cu—Mo composite material and having an average thickness of less than or equal to 0.6 mm and a variation in thickness of less than or equal to 0.1 mm, and a Cu layer directly stacked on each of both surfaces thereof. A method for manufacturing the heat spreader includes planarizing a plate material of the Cu—Mo composite material constituting the Cu—Mo layer, and roll-bonding a Cu plate constituting the Cu layer to each of both surfaces thereof.

Abstract: A castable, moldable, or extrudable structure using a metallic base metal or base metal alloy. One or more insoluble additives are added to the metallic base metal or base metal alloy so that the grain boundaries of the castable, moldable, or extrudable structure includes a composition and morphology to achieve a specific galvanic corrosion rates partially or throughout the structure or along the grain boundaries of the structure. The insoluble additives can be used to enhance the mechanical properties of the structure, such as ductility and/or tensile strength. The insoluble particles generally have a submicron particle size. The final structure can be enhanced by heat treatment, as well as deformation processing such as extrusion, forging, or rolling, to further improve the strength of the final structure as compared to the non-enhanced structure.

Abstract: A stacked semiconductor package includes a first semiconductor package including a first circuit board and a first semiconductor device mounted on the first circuit board; a second semiconductor package including a second circuit board and a second semiconductor device mounted on the second circuit board, the second semiconductor package being stacked on the first semiconductor package; and a heat transfer member provided on the first semiconductor device and a part of the first circuit board, the part being around the first semiconductor device.

Abstract: A thermal interface material (1) comprises a bulk polymer (2) within which is embedded sub-micron (c. 200 to 220 nm) composite material wires (3) having Ag and carbon nanotubes (“CNTs”) 4. The CNTs are embedded in the axial direction and have diameters in the range of 9.5 to 10 nm and have a length of about 0.7 ?m. In general the pore diameter can be in the range of 40 to 1200 nm. The material (1) has particularly good thermal conductivity because the wires (3) give excellent directionality to the nanotubes (4)—providing very low resistance heat transfer paths. The TIM is best suited for use between semiconductor devices (e.g. power semiconductor chip) and any type of thermal management systems for efficient removal of heat from the device.

Abstract: An active matrix substrate includes: a plurality of pixel electrodes arranged in a matrix pattern and each forming a pixel; a plurality of gate lines each provided between the corresponding pixel electrodes and extending in parallel with each other; a plurality of first source lines each provided between the corresponding pixel electrodes and extending in a direction crossing an extending direction of the gate lines; a plurality of TFTs provided corresponding to the respective pixel electrodes and connected to the respective pixel electrodes, the respective gate lines, and the respective first source lines; a plurality of capacitor lines each provided between the corresponding gate lines and extending in parallel with each other; and a plurality of second source lines each provided between the corresponding pixel electrodes and extending in parallel with the first source lines.

Abstract: A chip on film type semiconductor package includes a film, a plurality of leads formed over the film, a chip formed over the plurality of leads, an under-fill layer filled an space between the chip and the plurality of leads and an insulating heating sheet formed on an opposite side of the film contacting to the plurality of leads, wherein the insulating heating sheet is formed of a compound based on a glass fiber.

Abstract: A semiconductor device includes an insulating substrate and a TFT element disposed on the substrate. The TFT element includes a gate electrode, a gate insulating film, a semiconductor layer, and a source electrode and a drain electrode arranged in that order on the insulating substrate. The semiconductor layer includes an active layer composed of polycrystalline semiconductor and a contact layer segment interposed between the active layer and the source electrode and another contact layer segment interposed between the active layer and the drain electrode. The source and drain electrodes each have a first face facing the opposite face of the active layer from the interface with the gate insulating layer and a second face facing an etched side face of the active layer. Each contact layer segment is disposed between the active layer and each of the first and second faces of the source or drain electrode.

Abstract: This invention relates to a system in package including a plurality of integrated circuit chips and a substrate on which the plurality of integrated circuit chips are mounted and characterized in that a testability circuit for facilitating a test on at least one of the integrated circuit chips is incorporated into the substrate. The testability circuit incorporated into the substrate is formed by embedding a so-called WLCSP integrated circuit chip into the substrate. Alternatively, the testability circuit is formed by using a transistor element formed by using a semiconductor layer formed on the substrate. By incorporating the testability circuit into the substrate as described above, it is possible to realize a system in package facilitated in test without increases in size and cost.

Abstract: An active matrix substrate includes: a plurality of pixel electrodes arranged in a matrix pattern and each forming a pixel; a plurality of gate lines each provided between the corresponding pixel electrodes and extending in parallel with each other; a plurality of first source lines each provided between the corresponding pixel electrodes and extending in a direction crossing an extending direction of the gate lines; a plurality of TFTs provided corresponding to the respective pixel electrodes and connected to the respective pixel electrodes, the respective gate lines, and the respective first source lines; a plurality of capacitor lines each provided between the corresponding gate lines and extending in parallel with each other; and a plurality of second source lines each provided between the corresponding pixel electrodes and extending in parallel with the first source lines.

Abstract: A Cu—Mo substrate 10 according to the present invention includes: a Cu base 1 containing Cu as a main component; an Mo base having opposing first and second principal faces 2a, 2b and containing Mo as a main component, the second principal face 2b of the Mo base 2 being positioned on at least a portion of a principal face 1a of the Cu base 1; and a first Sn—Cu-type alloy layer 3 covering the first principal face 2a and side faces 2c and 2d of the Mo base 2, the first Sn—Cu-type alloy layer 3 containing no less than 1 mass % and no more than 13 mass % of Sn.

Abstract: One aspect of the invention pertains to a semiconductor package suitable for use in high stress environments, such as ones involving high pressures, temperatures and/or corrosive substances. In this aspect, a die and leadframe are fully encapsulated in a first plastic casing. The first plastic casing is fully encapsulated in turn with a second plastic casing. The two casings have different compositions. The first plastic casing, for example, may be made of a thermoset plastic material and the second plastic casing may be made of a thermoplastic material. The first plastic casing may have recesses, indentations and/or slots suitable for securing it to the second plastic casing. In some embodiments, a corrosion resistant coating is added to the second plastic casing. Methods for forming semiconductor packages suitable for use in high stress environments are also described.

Abstract: An electronic semiconductor package is described. The package has a wide band gap electronic semiconductor device requiring heat removal. On one side of the electronic semiconductor device is a first, thermally-conductive, electrically-insulative substrate having a predetermined electrically-conductive wire pattern affixed thereto. On the other side of the electronic semiconductor device is a second, thermally-conductive, electrically-insulative substrate. A heat removal device is mechanically-coupled to the second substrate. The heat removal device is made of a graphite-metal or metal-matrix composite material and a fin array structure of the same material. The coefficients of thermal expansion of the heat removal device and the first and second substrates are matched to minimize internal and external stresses.

Abstract: A micromechanical structure is described. A region of semiconductor material has a first surface, a second surface opposite to the first surface, and a lateral surface that surrounds the region of semiconductor material. Insulative material covers the first surface and the lateral surface of the region of semiconductor material to provide electrical isolation to the region of semiconductor material by forming a boundary. To form the micromechanical structure, a trench is etched in a semiconductor substrate to surround a region of the semiconductor substrate. A surface of the semiconductor substrate and the trench are oxidized to form a top oxide and a lateral oxide region. A backside of the semiconductor substrate is etched to expose a backside of the region of the semiconductor substrate and a portion of the lateral oxide.

Abstract: A carbon nanotube (CNT) array is patterned on a substrate. The substrate can be a microelectronic die or a heat sink for a die. The patterned CNT array is patterned by using a patterned catalyst on the substrate to form the CNT array by growing. The patterned CNT array can also be patterned by using a patterned mask on the substrate to form the CNT array by growing. A computing system that uses the CNT array for heat transfer from the die is also used.

Abstract: A flip chip assembly having reduced stress and warpage comprises a flip chip package including an organic substrate and an integrated circuit chip, a temporary structure having a coefficient of thermal expansion that is substantially similar to a coefficient of thermal expansion of the integrated circuit chip, and a cap member coupled to a top side of the organic substrate. A bottom side of the integrated circuit chip is bonded to the top side of the organic substrate with controlled chip collapse columns. Additionally, a bottom side of the organic substrate is soldered to a top side of the temporary structure with solder interconnections that are applied to a plurality of solder pads on the top side of the temporary structure, the position of the solder pads on the temporary structure mirroring the position of a plurality of solder pads on the bottom side of the organic substrate.

Abstract: A microelectronic cooling assembly and method for fabricating the same are described. In one example, a microelectronic cooling assembly includes a microelectronic device, a heat spreader, and a thermal interface material (TIM) that thermally joins the microelectronic device and heat spreader, the TIM comprising a sintered metallic nanopaste.

Abstract: The invention includes semiconductor packages having grooves within a semiconductor die backside; and includes semiconductor packages utilizing carbon nanostructures (such as, for example, carbon nanotubes) as thermally conductive interface materials. The invention also includes methods of cooling a semiconductor die in which coolant is forced through grooves in a backside of the die, and includes methods of making semiconductor packages.

Abstract: To isolate two active regions formed on a silicon-on-insulator (SOI) substrate, a shallow trench isolation region is filled with liquid phase deposited silicon dioxide (LPD-SiO2) while avoiding covering the active areas with the oxide. By selectively depositing the oxide in this manner, the polishing needed to planarize the wafer is significantly reduced as compared to a chemical-vapor deposited oxide layer that covers the entire wafer surface. Additionally, the LPD-SiO2 does not include the growth seams that CVD silicon dioxide does. Accordingly, the etch rate of the LPD-SiO2 is uniform across its entire expanse thereby preventing cavities and other etching irregularities present in prior art shallow trench isolation regions in which the etch rate of growth seams exceeds that of the other oxide areas.

Abstract: An integrated circuit chip has one or more electrically conductive nano-fibers formed on one or more contact pads of the integrated circuit chip. The one or more electrically conductive nano-fibers are configured to provide an adhesive force by intermolecular forces and establish an electrical connection with one or more contact pads disposed on the surface of a chip package.

Abstract: Methods and apparatus relating to thermally conductive molding compounds are described. In one embodiment, a molding compound may include thermally conductive particles to form a thermally conductive path in the molding compound (e.g., for improved heat dissipation through the molding compound). Other embodiments are also described.

Abstract: It is an object to provide an insulating film having a very low dielectric constant and a great mechanical strength. Moreover, it is another object to provide a semiconductor device capable of reducing both a capacity between wiring layers and a capacity between wirings also in microfabrication and an increase in integration in the semiconductor device. In order to attain the objects, there is provided an inorganic insulating film comprising a porous structure having a skeletal structure in which a vacancy is arranged periodically and a large number of small holes are included.

Abstract: Provided is a flexible heat sink article comprising a base comprising a polymer and a plurality of polymeric protrusions extending away from the base, each protrusion having a major dimension and a minor dimension. The base comprises thermally conductive particles, and the protrusions comprise non-spherical thermally conductive particles substantially aligned in the direction of the major dimension within the protrusions. A thermal interface material may be provided contiguous with the base. Also provided is a flexible heat sink article comprising a base comprising a polymer and having a first surface and a second surface, a plurality of polymeric protrusions extending away from the first surface of the base, each protrusion having a major and a minor dimension, and a metallic layer contiguous with the second surface of the base, wherein the base and the protrusions comprise thermally conductive particles. Also provided is a method of making a flexible heat sink.

Abstract: An electronic part mounting method, a semiconductor module, and a semiconductor device, which can reduce a mounting area and a device thickness. In an electronic part mounting method for bonding an electrode formed on a substrate and an electrode formed on an electronic part to each other, the method comprises the step of bonding both the electrodes through a metal layer made up of aggregated particles of at least one kind of metal. Then, the metal particles have an average particle size of 1 to 50 nm. Preferably, the metal particles form a metal layer having a thickness of 5 to 100 ?m.

Abstract: The present invention is directed to methods for making electronic devices with a thin anisotropic conducting layer interface layer formed between a substrate and an active device layer that is preferably patterned conductive layer. The interface layer preferably provides Ohmic and/or rectifying contact between the active device layer and the substrate and preferably provides good adhesion of the active device layer to the substrate. The active device layer is preferably fashioned from a nanoparticle ink solution that is patterned using embossing methods or other suitable printing and/or imaging methods. The active device layer is preferably patterned into an array of gate structures suitable for the fabrication of thin film transistors and the like.

Abstract: It is an object of the present invention to provide a high thermal conductive element that has improved thermal conductivity in the layer direction while retaining the high thermal conductivity characteristics in the planar direction possessed by graphite. The present invention is a high thermal conductive element in which carbon particles are dispersed in a graphite-based matrix, wherein (1) the c axis of the graphene layers constituting the graphite are substantially parallel, (2) the thermal conductivity ?? in a direction perpendicular to the c axis is at least 400 W/m·k and no more than 1000 W/m·k, and (3) the thermal conductivity ?? in a direction parallel to the c axis is at least 10 W/m·k and no more than 100 W/m·k.

Abstract: A method and structure for heat transport, cooling, sensing and power generation is described. A photonic bandgap structure (3) is employed to enhance emissive heat transport from heat sources such as integrated circuits (2) to heat spreaders (4). The photonic bandgap structure (3) is also employed to convert heat to electric power by enhanced emission absorption and to cool and sense radiation, such as infra-red radiation. These concepts may be applied to both heat loss and heat absorption, and may be applied to heat transport and absorption enhancement in a single device.

Abstract: The present invention provides a composite material such as a passive element, a passive element composite component, a substrate with a built-in passive element and a composite wiring substrate which are free from, for example, a layer peeling problem and enables high density packaging with ease. In the present invention, a porous base material is divided into plural functional regions and a material having different electromagnetic characteristics is filled in a pore of the porous base material of each functional region, to form a passive element or a wiring substrate. Among the aforementioned plural functional regions, at least one functional region is a conductive material region filled with a conductive material and other regions are filled with a high-dielectric material, a high-permeability material or a low-dielectric material.