Abstract: An improvement in heat radiation efficiency is achieved. A semiconductor device according to the present technology includes a substrate portion on which a semiconductor chip is mounted and in which an external connection terminal for performing electrical connection to the outside is formed on a rear surface on a side opposite to a front surface which is a surface on a side where the semiconductor chip is mounted, an outer wall portion that protrudes toward the front surface side in an outer circumferential portion of the substrate portion, a lid portion which is supported by the outer wall portion and covers the semiconductor chip, and a heat storage member which is disposed at a position further inside than the outer wall portion between the rear surface of the substrate portion and a rear surface of the lid portion.

Abstract: In an embodiment a connecting element includes a base configured to be fixed to a housing, an electrical conductor and a retainer for guiding and fixing the electrical conductor, the retainer being connected to the base, wherein the electrical conductor is in direct contact with the retainer, wherein the retainer is shaped such that a first contact face of the electrical conductor is configured to contact a first functional part of an electrical component and a second contact face of the electrical conductor is configured to contact a second functional part of the electrical component, the first functional part and the second functional part being located spatially distant from each other in an interior space of the housing, and wherein the connecting element is configured to connect the first functional part and the second functional part.

Abstract: A heat dissipation apparatus is provided. The heat dissipation apparatus includes a thermally conductive housing. The heat dissipation apparatus is connectable to a chip so that the chip is arrangeable on a chip placement region of the thermally conductive housing. A capillary structure is disposed on the thermally conductive housing and a working medium is placed in the capillary structure. The capillary structure includes a first capillary structure and a second capillary structure that are connected, and a maximum thickness of the first capillary structure is less than a minimum thickness of the second capillary structure.

Abstract: A photoelectric apparatus comprises a barrel-shaped container, an optical lens and a photoelectric imaging device arranged at two ends of the container, respectively. The container is filled with a light-transmitting and heat-conductive liquid. The heat-conductive liquid contains a plurality of nanostructures and particularly includes a plurality of nanorods. When an external voltage is applied between the photoelectric imaging device and the container, the nanorods are aligned with the electric field lines created by the external voltage, and form into nanorod chains. The nanorod chains link the photoelectric imaging device and the container, thereby increase the thermal conductivity of the heat-conductive liquid, and hence improve the heat dissipation efficiency of the photoelectric apparatus.

Abstract: A composite includes a plastic substrate and an electrical insulator layer formed on the plastic substrate. The electrical insulator layer contains boron nitride nanotubes (BNNTs), which may be unmodified or modified BNNTS. The composite is suitable for use in making printed electronic devices. A process includes providing a plastic substrate and forming on at least a portion of a surface of the plastic substrate a layer that contains the BNNTs. A metallic ink trace is formed on a portion of the layer, such that the metallic ink trace is spaced-apart from the substrate. Using photonic or thermal sintering techniques, the metallic ink trace is then sintered.

Abstract: A semiconductor package includes a substrate, a stacked structure, an encapsulation material, a lid structure, and a coupler. The stacked structure is disposed over and bonded to the substrate. The encapsulation material partially encapsulates the stacked structure. The lid structure is disposed on the substrate, wherein the lid structure surrounds the stacked structure and covers a top surface of the stacked structure. The coupler is bonded to the stacked structure, wherein a portion of the coupler penetrates through and extends out of the lid structure.

Abstract: A semiconductor package includes a substrate, a stacked structure, an encapsulation material, a lid structure, and a coupler. The stacked structure is disposed over and bonded to the substrate. The encapsulation material partially encapsulates the stacked structure. The lid structure is disposed on the substrate, wherein the lid structure surrounds the stacked structure and covers a top surface of the stacked structure. The coupler is bonded to the stacked structure, wherein a portion of the coupler penetrates through and extends out of the lid structure.

Abstract: A semiconductor device including a semiconductor chip having a first surface and a second surface opposite to the first surface, a first heat dissipation member on the second surface of the semiconductor chip, the first heat dissipation member having a vertical thermal conductivity in a direction perpendicular to the second surface, and a horizontal thermal conductivity in a direction parallel to the second surface, the first vertical thermal conductivity being smaller than the first horizontal thermal conductivity, and a second heat dissipation member comprising a vertical pattern penetrating the first heat dissipation member, the second heat dissipation member having a vertical thermal conductivity that is greater than the vertical thermal conductivity of the first heat dissipation member may be provided.

Abstract: Disclosed is a heat dissipation structure that includes a plurality of linear structures made of carbon, each of the linear structures having at least one of a first end and a second end being bent, and a coating layer formed on a surface of each of the linear structures, the coating layer having a part covering the other one of the first ends and the second ends of the linear structures, a thickness of the part allowing the corresponding linear structures to be plastically deformable.

Abstract: Semiconductor package are provided. In one embodiment, the semiconductor package may include a substrate such as a circuit substrate, a semiconductor chip mounted on the circuit substrate, a molding (or an encapsulant) covering the semiconductor chip and the circuit substrate and including a first temperature control member, and a heat dissipation member covering the molding.

Abstract: An integrated circuit includes a number of metallization levels separated by an insulating region disposed over a substrate. A housing includes walls formed from metal portions produced in various metallization levels. A metal device is housed in the housing. An aperture is produced in at least one wall of the housing. An external mechanism outside of the housing is configured so as to form an obstacle to diffusion of a fluid out of the housing through the at least one aperture. At least one through-metallization passes through the external mechanism and penetrates into the housing through the aperture in order to make contact with at least one element of the metal device.

Abstract: The present invention provides a technique for improving the reliability of a semiconductor device where spreading of cracking that occurs at the time of dicing to a seal ring can be restricted even in a semiconductor device with a low-k film used as an interlayer insulating film. Dummy vias are formed in each layer on a dicing region side. The dummy vias are formed at the same intervals in a matrix as viewed in a top view. Even in the case where cracking occurs at the time of dicing, the cracking can be prevented from spreading to a seal ring by the dummy vias. As a result, resistance to moisture absorbed in a circuit formation region can be improved, and deterioration in reliability can be prevented.

Abstract: An integrated circuit chip package is described. The integrated circuit package comprises a substrate, a chip attached to the substrate, and a heat spreader mounted over the chip for sealing the chip therein. The heat spreader includes a thermally-conductive element having a side opposed to the top of the chip for transmitting heat away from the chip to the heat spreader, and a compliant element having a first portion attached to and positioned around the periphery of the thermally-conductive element and a second portion affixed to a surface of the substrate.

Abstract: According to one embodiment, provided are a package utilized for a high frequency semiconductor device and a fabrication method for such the package, the package including: a conductive base plate including a CTE control layer composed of compound material, and a heat conduction layer disposed on the CTE control layer and composed of Cu.

Abstract: An electric device with an insulating substrate consisting of an insulating layer and at least one metallization on a surface side of the insulating layer, the metallization being structured and having an electric component on the metallization. The metallization has a layer thickness that is stepped and is greater in an area adjoining the component.

Abstract: A thermal interface material (1) comprises a bulk polymer (2) within which is embedded sub-micron (c. 200 to 220 nm) composite material wires (3) having Ag and carbon nanotubes (“CNTs”) 4. The CNTs are embedded in the axial direction and have diameters in the range of 9.5 to 10 nm and have a length of about 0.7 ?m. In general the pore diameter can be in the range of 40 to 1200 nm. The material (1) has particularly good thermal conductivity because the wires (3) give excellent directionality to the nanotubes (4)—providing very low resistance heat transfer paths. The TIM is best suited for use between semiconductor devices (e.g. power semiconductor chip) and any type of thermal management systems for efficient removal of heat from the device.

Abstract: In a package wherein a lead part coupled to a semiconductor element by wire bonding, an element retention member to retain the semiconductor element on the top face side and radiate heat on the bottom face side, and an insulative partition part to partition the lead part from the element retention member with an insulative resin appear, a creeping route ranging from the top face to retain the semiconductor element to a package bottom face on a boundary plane between the element retention member and an insulative partition part includes a bent route having a plurality of turns. Consequently, it is possible to inhibit an encapsulation resin to seal a region retaining the semiconductor element from exuding toward the bottom face side of the package.

Abstract: A semiconductor structure is bonded directly to a diamond substrate by Van der Waal forces. The diamond substrate is formed by polishing a surface of diamond to a first degree of smoothness; forming a material, such as diamond, BeO, GaN, MgO, or SiO2 or other oxides, over the polished surface to provide an intermediate structure; and re-polishing the material formed on the intermediate structure to a second degree of smoothness smoother than the first degree of smoothness. The diamond is bonded to the semiconductor structure, such as GaN, by providing a structure having bottom surfaces of a semiconductor on an underlying material; forming grooves through the semiconductor and into the underlying material; separating semiconductor along the grooves into a plurality of separate semiconductor structures; removing the separated semiconductor structures from the underlying material; and contacting the bottom surface of at least one of the separated semiconductor structures to the diamond substrate.

Abstract: An integrated circuit die includes a substrate having an upper surface, at least one active device formed in a first area of the upper surface of the substrate, and a plurality of layers formed on the upper surface of the substrate above the at least one active device. A first stacked heat conducting structure is provided, spanning from a point proximate the first area of the upper surface of the substrate through the plurality of layers. A lateral heat conducting structure is formed above the uppermost layer of the plurality of layers and in thermal contact with the first stacked heat conducting structure. The invention advantageously facilitates the dissipation of heat from the integrated circuit die, particularly from high-power sources or other localized hot spots.

Abstract: A semiconductor assembly includes a semiconductor device and a connecting structure. The semiconductor device includes an interconnect region over a semiconductor substrate and a pillar layer having a plurality of pillar contacts on the interconnect region. The pillar layer also includes a plurality of radial heat conductors that have at least a portion overlying a heat source that is within and overlies the semiconductor substrate. Each radial heat conductor extends a length radially from the heat source that is at least twice as great as the diameter of the pillars. The connecting structure includes a connecting substrate that supports a first corresponding pillar contact that is in contact with a first pillar contact of the plurality of pillar contacts. The first connecting structure further includes a heat conductor, supported by the substrate, in contact with a first radial heat conductor of the plurality of radial heat conductors.

Abstract: A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer.

Abstract: The invention includes semiconductor packages having grooves within a semiconductor die backside; and includes semiconductor packages utilizing carbon nanostructures (such as, for example, carbon nanotubes) as thermally conductive interface materials. The invention also includes methods of cooling a semiconductor die in which coolant is forced through grooves in a backside of the die, and includes methods of making semiconductor packages.

Abstract: In accordance with an embodiment, a semiconductor package includes a first surface configured to be mounted on a circuit board, and a region of thermally expandable material configured to push the first surface of the semiconductor package away from the circuit board when a temperature of the thermally expandable material exceeds a first temperature.

Abstract: A semiconductor device includes a semiconductor chip coupled to a substrate and a base plate coupled to the substrate. The base plate includes a first metal layer clad to a second metal layer. The second metal layer is deformed to provide a pin-fin or fin cooling structure.

Abstract: Semiconductor package are provided. In one embodiment, the semiconductor package may include a substrate such as a circuit substrate, a semiconductor chip mounted on the circuit substrate, a molding (or an encapsulant) covering the semiconductor chip and the circuit substrate and including a first temperature control member, and a heat dissipation member covering the molding.

Abstract: An underfill film for an electronic device includes a thermally conductive sheet. The electronic device may include a printed circuit board, an electrical component, an underfill, and the thermally conductive sheet. The underfill is situated between the circuit board and the component. The thermally conductive sheet is situated within the underfill, and together with the underfill, constitutes the underfill film. The device may include solder bumps affixing the component to the circuit board, the underfill film having holes within which the solder bumps are aligned. There may be solder bumps on the underside of the circuit board promoting heat dissipation. There may be heat sinks on the circuit board to which the thermally conductive sheet is affixed promoting heat dissipation. The thermally conductive sheet may be affixed to a chassis promoting heat dissipation. The thermally conductive sheet thus promotes heat dissipation from the component to at least the circuit board.

Abstract: A protection layer is coated or otherwise formed over the interconnect structure. The interconnect structure includes a metal line (such as top and bottom metal layers connected by a metal via) and a low-K material. The protection layer includes a vertically aligned dielectric or other material dispersed with carbon nanotubes. The protection layer could include one or multiple layers of carbon nanotubes, and the carbon nanotubes could have any suitable dispersion, alignment, and pattern in each layer of the protection layer. Among other things, the carbon nanotubes help to reduce or prevent damage to the interconnect structure, such as by reducing or preventing the collapse of the low-K material or delamination between the metal line and the low-K material.

Abstract: A method of manufacturing is provided that includes providing a semiconductor chip device that has a circuit board and a first semiconductor chip coupled thereto. A lid is placed on the circuit board. The lid includes an opening and an internal cavity. A liquid thermal interface material is placed in the internal cavity for thermal contact with the first semiconductor chip and the circuit board.

Abstract: An integrated circuit chip package is described. The integrated circuit package comprises a substrate, a chip attached to the substrate, and a heat spreader mounted over the chip for sealing the chip therein. The heat spreader includes a thermally-conductive element having a side opposed to the top of the chip for transmitting heat away from the chip to the heat spreader, and a compliant element having a first portion attached to and positioned around the periphery of the thermally-conductive element and a second portion affixed to a surface of the substrate.

Abstract: A pad structure of a semiconductor integrated circuit apparatus includes a semiconductor substrate upon which circuit patterns forming a device are disposed, a pad disposed on an uppermost part of the semiconductor substrate, and a plurality of fixing parts, each disposed along opposing edge portions of the pad to fix the pad and the semiconductor substrate to each other.

Abstract: A semiconductor package having a heat dissipation member capable of efficiently conveying excess heat away from semiconductor chips is presented. The semiconductor package includes a semiconductor chip, through-electrodes, and a heat dissipation member. The semiconductor chip has a first surface, a second surface facing away from the first surface, and bonding pads which are disposed on the first surface. The through-electrodes are electrically connected with the bonding pads and passing through the first and second surfaces of the semiconductor chip, and protrude outward from the second surface. The heat dissipation member faces the second surface of the semiconductor chip and is coupled to the through-electrodes.

Abstract: According to one embodiment, provided are a package utilized for a high frequency semiconductor device and a fabrication method for such the package, the package including: a conductive base plate including a CTE control layer composed of compound material, and a heat conduction layer disposed on the CTE control layer and composed of Cu.

Abstract: The invention concerns a module comprising a carrier element, a semiconductor device mounted on said carrier element and a silicon-based insulating layer. The silicon-based insulating layer is arranged on the side of the carrier element opposite to the semiconductor device. The invention further concerns a module comprising a semiconductor device, a mold compound at least partly covering the semiconductor device and a silicon-based passivation layer. The silicon-based passivation layer covers at least partly the periphery of the mold compound.

Abstract: There is provided an LED package having high heat dissipation efficiency. An LED package according to an aspect of the invention may include: a package body including a first groove portion being recessed into the package body and provided as a mounting area on the top of the package body; first and second lead frames arranged on a lower surface of the first groove portion while parts of the first and second lead frames are exposed; an LED chip mounted onto the lower surface of the first groove portion and electrically connected to the first and second lead frames; and a plurality of heat dissipation patterns provided on the bottom of the package body and formed of carbon nanotubes.

Abstract: A power semiconductor device according to the present invention includes a heat sink made of Cu and having a thickness of 2 to 3 mm, an insulating substrate bonded on the heat sink with interposition of a first bonding layer (under-substrate solder), and a power semiconductor element mounted on the insulating substrate. In the heat sink, a buffer slot is formed at a periphery of a region bonded to the insulating substrate.

Abstract: A semiconductor structure having a transistor and a thermo electronic structure. The transistor has a control electrode for controlling a flow of carriers through a semiconductor layer between a pair of electrodes. The thermo electronic structure has a first portion disposed on at least one of the pair of electrodes and a second portion disposed over a region of the semiconductor layer proximate the control electrode between the control electrode and said at least one of the pair of electrode. The thermo electronic structure extends from the first portion to the second portion for removing heat generated heat from said region in the semiconductor layer.

Abstract: An integrated circuit package system is provided including providing a substrate having a die attached and electrically bonded thereto. The system includes forming heat slug pillars on the substrate, positioning a heat slug on the heat slug pillars, and encapsulating the substrate, the die, the heat slug pillars, and the heat slug in a mold compound. The system includes singulating the substrate, the die, the heat slug, and the mold compound.

Abstract: The invention comprises a 3D chip stack with an intervening thermoelectric coupling (TEC) plate. Through silicon vias in the 3D chip stack transfer electronic signals among the chips in the 3D stack, power the TEC plate, as well as distribute heat in the stack from hotter chips to cooler chips.

Abstract: A melting temperature adjustable metal thermal interface material (TIM) and a packaged semiconductor including thereof are provided. The metal TIM includes about 20-98 wt % of In, about 0.03-4 wt % of Ga, and at least one element of Bi, Sn, Ag and Zn. The metal TIM has an initial melting temperature between about 60-144° C.

Abstract: A submount for red, green, and blue LEDs is described where the submount has thermally isolated trenches and/or holes in the submount so that the high heat generated by the green/blue AlInGaN LEDs is not conducted to the red AlInGaP LEDs. The submount contains conductors to interconnect the LEDs in a variety of configurations. In one embodiment, the AlInGaP LEDs are recessed in the submount so all LEDs have the same light exit plane. The submount may be used for LEDs generating other colors, such as yellow, amber, orange, and cyan.

Abstract: A semiconductor device has a wiring substrate provided with an external connecting terminal on a lower surface, a semiconductor chip mounted onto an upper surface of the wiring substrate, a cap-shaped heat dissipation member arranged on the upper surface of the wiring substrate so as to cover the semiconductor chip, a fixing pin for fixing the heat dissipation member onto the upper surface of the wiring substrate, and a heat transfer material sandwiched between a lower surface of the heat dissipation member just above the semiconductor chip and the upper surface of the semiconductor chip.

Abstract: A semiconductor device including at least one gate terminal in operational contact with an active layer or top surface of the semiconductor substrate includes a deposited layer of boron phosphide covering the gate terminal and at least a portion of the active layer or the top surface next to and extending from the gate terminal. According to an aspect, the layer of boron phosphide is deposited by a chemical vapor deposition (CVD) process. The boron phosphide layer will have a thickness less than or equal to about 10 microns. The boron phosphide provides a heat spreading coating across the die surface, thus increasing the surface area that conducts the heat from the die. Since the boron phosphide coating is in intimate contact with the gate terminal(s) and the immediately adjacent passivation surfaces of the device, generated heat can rapidly spread away from the active junction or channel.

Abstract: A thermal interface material is provided using composite particles. Advantages include increased thermal conductivity and improved mechanical properties such as lower viscosity. In selected embodiments free particles such as metallic particles or carbon nanotubes, etc. are included in a thermal interface material along with composite particles. An advantage of including free particles along with composite particles includes improved packing density within selected embodiments of thermal interface materials.

Abstract: A semiconductor package includes a substrate board and a semiconductor die attached to a top surface of that substrate board. A heat spreader is provided over the semiconductor die. A stiffening ring is positioned surrounding the semiconductor die, the stiffening ring being attached to the top surface of the substrate board and attached to a bottom surface of the plate portion of the heat spreader. Space is left on the board outside of the stiffening ring to support the installation of passive components to the substrate board. An external ring may be included, with that external ring being interconnected to the stiffening ring by a set of tie bars. Alternatively, the heat spreader includes an integrally formed peripheral sidewall portion.

Abstract: A flexible circuit electronic package including a heat sink, a flexible circuit having a semiconductor chip positioned thereon and electrically coupled thereto, and a quantity of heat shrunk adhesive securing the flexible circuit to the heat sink such that the flexible circuit is planar. This package is then adapted for being positioned on and electrically coupled to a circuitized substrate such as a printed circuit board. A method of making this package is also provided.

Abstract: A method of making a semiconductor chip assembly includes providing a metal base, a routing line, a bumped terminal and a filler, wherein the routing line contacts the bumped terminal and the filler, then mechanically attaching a semiconductor chip to the metal base, the routing line, the bumped terminal and the filler, then forming an encapsulant, then etching the metal base to expose the bumped terminal, and then forming an insulative base that covers a peripheral portion of the bumped terminal.

Abstract: Under one aspect, a method of cooling a circuit element includes providing a thermal reservoir having a temperature lower than an operating temperature of the circuit element; and providing a nanotube article in thermal contact with the circuit element and with the reservoir, the nanotube article including a non-woven fabric of nanotubes in contact with other nanotubes to define a plurality of thermal pathways along the article, the nanotube article having a nanotube density and a shape selected such that the nanotube article is capable of transferring heat from the circuit element to the thermal reservoir.

Abstract: A photodetector, comprises a first section comprising at least one p-n junction that converts photon energy into a separate charge carrier and hole carrier; and another section of semiconductors of opposing conductivity type connected electrically in series and thermally in parallel in a heat dissipating and electric generating relationship to the cell to augment generation of electric energy of the first section.

Abstract: An electronic semiconductor package is described. The package has a wide band gap electronic semiconductor device requiring heat removal. On one side of the electronic semiconductor device is a first, thermally-conductive, electrically-insulative substrate having a predetermined electrically-conductive wire pattern affixed thereto. On the other side of the electronic semiconductor device is a second, thermally-conductive, electrically-insulative substrate. A heat removal device is mechanically-coupled to the second substrate. The heat removal device is made of a graphite-metal or metal-matrix composite material and a fin array structure of the same material. The coefficients of thermal expansion of the heat removal device and the first and second substrates are matched to minimize internal and external stresses.

Abstract: Disclosed is a semiconductor device including a SiC substrate and a heat conductor formed in a hole in the SiC substrate and made of a linear structure of carbon elements.